/kernel/linux/linux-5.10/arch/powerpc/boot/ |
H A D | pq2.c | 31 u32 *immr; in pq2_get_clocks() local 35 immr = fsl_get_immr(); in pq2_get_clocks() 36 if (!immr) { in pq2_get_clocks() 41 sccr = in_be32(&immr[PQ2_SCCR]); in pq2_get_clocks() 42 scmr = in_be32(&immr[PQ2_SCMR]); in pq2_get_clocks()
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H A D | mpc8xx.c | 22 u32 *immr; in mpc885_get_clock() local 27 immr = fsl_get_immr(); in mpc885_get_clock() 28 if (!immr) { in mpc885_get_clock() 33 plprcr = in_be32(&immr[MPC8XX_PLPRCR]); in mpc885_get_clock()
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/kernel/linux/linux-6.6/arch/powerpc/boot/ |
H A D | pq2.c | 31 u32 *immr; in pq2_get_clocks() local 35 immr = fsl_get_immr(); in pq2_get_clocks() 36 if (!immr) { in pq2_get_clocks() 41 sccr = in_be32(&immr[PQ2_SCCR]); in pq2_get_clocks() 42 scmr = in_be32(&immr[PQ2_SCMR]); in pq2_get_clocks()
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H A D | mpc8xx.c | 22 u32 *immr; in mpc885_get_clock() local 27 immr = fsl_get_immr(); in mpc885_get_clock() 28 if (!immr) { in mpc885_get_clock() 33 plprcr = in_be32(&immr[MPC8XX_PLPRCR]); in mpc885_get_clock()
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/third_party/node/deps/v8/src/codegen/arm64/ |
H A D | assembler-arm64-inl.h | 922 Instr Assembler::ImmR(unsigned immr, unsigned reg_size) { in ImmR() argument 923 DCHECK(((reg_size == kXRegSizeInBits) && is_uint6(immr)) || in ImmR() 924 ((reg_size == kWRegSizeInBits) && is_uint5(immr))); in ImmR() 926 DCHECK(is_uint6(immr)); in ImmR() 927 return immr << ImmR_offset; in ImmR() 938 Instr Assembler::ImmRotate(unsigned immr, unsigned reg_size) { in ImmRotate() argument 940 DCHECK(((reg_size == kXRegSizeInBits) && is_uint6(immr)) || in ImmRotate() 941 ((reg_size == kWRegSizeInBits) && is_uint5(immr))); in ImmRotate() 943 return immr << ImmRotate_offset; in ImmRotate()
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H A D | assembler-arm64.h | 593 void bfm(const Register& rd, const Register& rn, int immr, int imms); 596 void sbfm(const Register& rd, const Register& rn, int immr, int imms); 599 void ubfm(const Register& rd, const Register& rn, int immr, int imms); 2178 inline static Instr ImmR(unsigned immr, unsigned reg_size); 2180 inline static Instr ImmRotate(unsigned immr, unsigned reg_size);
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H A D | assembler-arm64.cc | 982 void Assembler::bfm(const Register& rd, const Register& rn, int immr, in bfm() argument 986 Emit(SF(rd) | BFM | N | ImmR(immr, rd.SizeInBits()) | in bfm() 990 void Assembler::sbfm(const Register& rd, const Register& rn, int immr, in sbfm() argument 994 Emit(SF(rd) | SBFM | N | ImmR(immr, rd.SizeInBits()) | in sbfm() 998 void Assembler::ubfm(const Register& rd, const Register& rn, int immr, in ubfm() argument 1002 Emit(SF(rd) | UBFM | N | ImmR(immr, rd.SizeInBits()) | in ubfm() 4047 // N imms immr size S R in IsImmLogical()
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/kernel/linux/linux-6.6/tools/objtool/arch/x86/ |
H A D | decode.c | 616 struct reloc *immr, *disp; in arch_decode_instruction() local 620 immr = find_reloc_by_dest(elf, (void *)sec, offset+3); in arch_decode_instruction() 623 if (!immr || strcmp(immr->sym->name, "pv_ops")) in arch_decode_instruction() 626 idx = (reloc_addend(immr) + 8) / sizeof(void *); in arch_decode_instruction()
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/kernel/linux/linux-5.10/arch/arm64/kernel/ |
H A D | insn.c | 922 int immr, int imms, in aarch64_insn_gen_bitfield() 957 if (immr & ~mask) { in aarch64_insn_gen_bitfield() 958 pr_err("%s: invalid immr encoding %d\n", __func__, immr); in aarch64_insn_gen_bitfield() 970 insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_R, insn, immr); in aarch64_insn_gen_bitfield() 1546 unsigned int immr, imms, n, ones, ror, esz, tmp; in aarch64_encode_immediate() local 1627 * immr is the number of bits we need to rotate back to the in aarch64_encode_immediate() 1631 immr = (esz - ror) % esz; in aarch64_encode_immediate() 1634 insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_R, insn, immr); in aarch64_encode_immediate() 920 aarch64_insn_gen_bitfield(enum aarch64_insn_register dst, enum aarch64_insn_register src, int immr, int imms, enum aarch64_insn_variant variant, enum aarch64_insn_bitfield_type type) aarch64_insn_gen_bitfield() argument
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/kernel/linux/linux-6.6/arch/arm64/lib/ |
H A D | insn.c | 793 int immr, int imms, in aarch64_insn_gen_bitfield() 828 if (immr & ~mask) { in aarch64_insn_gen_bitfield() 829 pr_err("%s: invalid immr encoding %d\n", __func__, immr); in aarch64_insn_gen_bitfield() 841 insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_R, insn, immr); in aarch64_insn_gen_bitfield() 1319 unsigned int immr, imms, n, ones, ror, esz, tmp; in aarch64_encode_immediate() local 1400 * immr is the number of bits we need to rotate back to the in aarch64_encode_immediate() 1404 immr = (esz - ror) % esz; in aarch64_encode_immediate() 1407 insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_R, insn, immr); in aarch64_encode_immediate() 791 aarch64_insn_gen_bitfield(enum aarch64_insn_register dst, enum aarch64_insn_register src, int immr, int imms, enum aarch64_insn_variant variant, enum aarch64_insn_bitfield_type type) aarch64_insn_gen_bitfield() argument
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
H A D | AArch64InstPrinter.cpp | 121 int64_t immr = Op2.getImm(); in printInst() local 123 if (Opcode == AArch64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) { in printInst() 127 ((imms + 1 == immr))) { in printInst() 132 shift = immr; in printInst() 135 shift = immr; in printInst() 138 shift = immr; in printInst() 141 shift = immr; in printInst()
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H A D | AArch64AddressingModes.h | 212 /// the form N:immr:imms. 291 /// "N:immr:imms" (where the immr and imms fields are each 6 bits) into the 294 // Extract the N, imms, and immr fields. in decodeLogicalImmediate() 296 unsigned immr = (val >> 6) & 0x3f; in decodeLogicalImmediate() local 303 unsigned R = immr & (size - 1); in decodeLogicalImmediate() 319 /// in the form "N:immr:imms" (where the immr and imms fields are each 6 bits)
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/kernel/linux/linux-5.10/arch/arm64/net/ |
H A D | bpf_jit.h | 115 #define A64_BITFIELD(sf, Rd, Rn, immr, imms, type) \ 116 aarch64_insn_gen_bitfield(Rd, Rn, immr, imms, \
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/kernel/linux/linux-6.6/arch/arm64/net/ |
H A D | bpf_jit.h | 173 #define A64_BITFIELD(sf, Rd, Rn, immr, imms, type) \ 174 aarch64_insn_gen_bitfield(Rd, Rn, immr, imms, \
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/third_party/vixl/src/aarch64/ |
H A D | assembler-aarch64.h | 765 unsigned immr, 771 unsigned immr, 777 unsigned immr, 7295 static Instr SVEImmRotate(unsigned immr, unsigned lane_size) { 7296 VIXL_ASSERT(IsUintN(WhichPowerOf2(lane_size), immr)); 7298 return immr << SVEImmRotate_offset; 7344 static Instr ImmR(unsigned immr, unsigned reg_size) { 7345 VIXL_ASSERT(((reg_size == kXRegSize) && IsUint6(immr)) || 7346 ((reg_size == kWRegSize) && IsUint5(immr))); 7348 VIXL_ASSERT(IsUint6(immr)); [all...] |
H A D | assembler-aarch64.cc | 682 unsigned immr, in bfm() 686 Emit(SF(rd) | BFM | N | ImmR(immr, rd.GetSizeInBits()) | in bfm() 693 unsigned immr, in sbfm() 697 Emit(SF(rd) | SBFM | N | ImmR(immr, rd.GetSizeInBits()) | in sbfm() 704 unsigned immr, in ubfm() 708 Emit(SF(rd) | UBFM | N | ImmR(immr, rd.GetSizeInBits()) | in ubfm() 6528 // N imms immr size S R 680 bfm(const Register& rd, const Register& rn, unsigned immr, unsigned imms) bfm() argument 691 sbfm(const Register& rd, const Register& rn, unsigned immr, unsigned imms) sbfm() argument 702 ubfm(const Register& rd, const Register& rn, unsigned immr, unsigned imms) ubfm() argument
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H A D | macro-assembler-aarch64.h | 1178 unsigned immr, in Bfm() 1184 bfm(rd, rn, immr, imms); in Bfm() 2413 unsigned immr, in Sbfm() 2419 sbfm(rd, rn, immr, imms); in Sbfm() 2705 unsigned immr, in Ubfm() 2711 ubfm(rd, rn, immr, imms); in Ubfm() 1176 Bfm(const Register& rd, const Register& rn, unsigned immr, unsigned imms) Bfm() argument 2411 Sbfm(const Register& rd, const Register& rn, unsigned immr, unsigned imms) Sbfm() argument 2703 Ubfm(const Register& rd, const Register& rn, unsigned immr, unsigned imms) Ubfm() argument
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/kernel/linux/linux-5.10/arch/arm64/include/asm/ |
H A D | insn.h | 437 int immr, int imms,
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/kernel/linux/linux-6.6/arch/arm64/include/asm/ |
H A D | insn.h | 607 int immr, int imms,
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelDAGToDAG.cpp | 1797 int immr = SrlImm - ShlImm; in isBitfieldExtractOpFromShr() local 1798 Immr = immr < 0 ? immr + VT.getSizeInBits() : immr; in isBitfieldExtractOpFromShr()
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