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Searched refs:phase (Results 1 - 25 of 487) sorted by relevance

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/kernel/linux/linux-5.10/drivers/clk/hisilicon/
H A Dclk-hisi-phase.c5 * Simple HiSilicon phase clock implementation.
30 static int hisi_phase_regval_to_degrees(struct clk_hisi_phase *phase, in hisi_phase_regval_to_degrees() argument
35 for (i = 0; i < phase->phase_num; i++) in hisi_phase_regval_to_degrees()
36 if (phase->phase_regvals[i] == regval) in hisi_phase_regval_to_degrees()
37 return phase->phase_degrees[i]; in hisi_phase_regval_to_degrees()
44 struct clk_hisi_phase *phase = to_clk_hisi_phase(hw); in hisi_clk_get_phase() local
47 regval = readl(phase->reg); in hisi_clk_get_phase()
48 regval = (regval & phase->mask) >> phase->shift; in hisi_clk_get_phase()
50 return hisi_phase_regval_to_degrees(phase, regva in hisi_clk_get_phase()
53 hisi_phase_degrees_to_regval(struct clk_hisi_phase *phase, int degrees) hisi_phase_degrees_to_regval() argument
67 struct clk_hisi_phase *phase = to_clk_hisi_phase(hw); hisi_clk_set_phase() local
97 struct clk_hisi_phase *phase; clk_register_hisi_phase() local
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/kernel/linux/linux-6.6/drivers/clk/hisilicon/
H A Dclk-hisi-phase.c5 * Simple HiSilicon phase clock implementation.
30 static int hisi_phase_regval_to_degrees(struct clk_hisi_phase *phase, in hisi_phase_regval_to_degrees() argument
35 for (i = 0; i < phase->phase_num; i++) in hisi_phase_regval_to_degrees()
36 if (phase->phase_regvals[i] == regval) in hisi_phase_regval_to_degrees()
37 return phase->phase_degrees[i]; in hisi_phase_regval_to_degrees()
44 struct clk_hisi_phase *phase = to_clk_hisi_phase(hw); in hisi_clk_get_phase() local
47 regval = readl(phase->reg); in hisi_clk_get_phase()
48 regval = (regval & phase->mask) >> phase->shift; in hisi_clk_get_phase()
50 return hisi_phase_regval_to_degrees(phase, regva in hisi_clk_get_phase()
53 hisi_phase_degrees_to_regval(struct clk_hisi_phase *phase, int degrees) hisi_phase_degrees_to_regval() argument
67 struct clk_hisi_phase *phase = to_clk_hisi_phase(hw); hisi_clk_set_phase() local
97 struct clk_hisi_phase *phase; clk_register_hisi_phase() local
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/kernel/linux/linux-5.10/drivers/clk/sunxi-ng/
H A Dccu_phase.c15 struct ccu_phase *phase = hw_to_ccu_phase(hw); in ccu_phase_get_phase() local
22 reg = readl(phase->common.base + phase->common.reg); in ccu_phase_get_phase()
23 delay = (reg >> phase->shift); in ccu_phase_get_phase()
24 delay &= (1 << phase->width) - 1; in ccu_phase_get_phase()
58 struct ccu_phase *phase = hw_to_ccu_phase(hw); in ccu_phase_set_phase() local
110 spin_lock_irqsave(phase->common.lock, flags); in ccu_phase_set_phase()
111 reg = readl(phase->common.base + phase->common.reg); in ccu_phase_set_phase()
112 reg &= ~GENMASK(phase in ccu_phase_set_phase()
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/kernel/linux/linux-6.6/drivers/clk/sunxi-ng/
H A Dccu_phase.c15 struct ccu_phase *phase = hw_to_ccu_phase(hw); in ccu_phase_get_phase() local
22 reg = readl(phase->common.base + phase->common.reg); in ccu_phase_get_phase()
23 delay = (reg >> phase->shift); in ccu_phase_get_phase()
24 delay &= (1 << phase->width) - 1; in ccu_phase_get_phase()
58 struct ccu_phase *phase = hw_to_ccu_phase(hw); in ccu_phase_set_phase() local
110 spin_lock_irqsave(phase->common.lock, flags); in ccu_phase_set_phase()
111 reg = readl(phase->common.base + phase->common.reg); in ccu_phase_set_phase()
112 reg &= ~GENMASK(phase in ccu_phase_set_phase()
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/kernel/linux/linux-5.10/drivers/clk/sunxi/
H A Dclk-mod0.c175 struct mmc_phase *phase = to_mmc_phase(hw); in mmc_get_phase() local
181 value = readl(phase->reg); in mmc_get_phase()
182 delay = (value >> phase->offset) & 0x3; in mmc_get_phase()
217 struct mmc_phase *phase = to_mmc_phase(hw); in mmc_set_phase() local
268 spin_lock_irqsave(phase->lock, flags); in mmc_set_phase()
269 value = readl(phase->reg); in mmc_set_phase()
270 value &= ~GENMASK(phase->offset + 3, phase->offset); in mmc_set_phase()
271 value |= delay << phase->offset; in mmc_set_phase()
272 writel(value, phase in mmc_set_phase()
326 struct mmc_phase *phase; sunxi_mmc_setup() local
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/kernel/linux/linux-6.6/drivers/clk/sunxi/
H A Dclk-mod0.c173 struct mmc_phase *phase = to_mmc_phase(hw); in mmc_get_phase() local
179 value = readl(phase->reg); in mmc_get_phase()
180 delay = (value >> phase->offset) & 0x3; in mmc_get_phase()
215 struct mmc_phase *phase = to_mmc_phase(hw); in mmc_set_phase() local
266 spin_lock_irqsave(phase->lock, flags); in mmc_set_phase()
267 value = readl(phase->reg); in mmc_set_phase()
268 value &= ~GENMASK(phase->offset + 3, phase->offset); in mmc_set_phase()
269 value |= delay << phase->offset; in mmc_set_phase()
270 writel(value, phase in mmc_set_phase()
324 struct mmc_phase *phase; sunxi_mmc_setup() local
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/kernel/linux/linux-5.10/drivers/gpu/drm/tidss/
H A Dtidss_dispc_regs.h120 #define DISPC_VID_FIR_COEF_H0(phase) (0x6c + (phase) * 4)
122 #define DISPC_VID_FIR_COEF_H0_C(phase) (0x90 + (phase) * 4)
125 #define DISPC_VID_FIR_COEF_H12(phase) (0xb4 + (phase) * 4)
127 #define DISPC_VID_FIR_COEF_H12_C(phase) (0xf4 + (phase) * 4)
130 #define DISPC_VID_FIR_COEF_V0(phase) (0x134 + (phase) *
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/kernel/linux/linux-6.6/drivers/gpu/drm/tidss/
H A Dtidss_dispc_regs.h120 #define DISPC_VID_FIR_COEF_H0(phase) (0x6c + (phase) * 4)
122 #define DISPC_VID_FIR_COEF_H0_C(phase) (0x90 + (phase) * 4)
125 #define DISPC_VID_FIR_COEF_H12(phase) (0xb4 + (phase) * 4)
127 #define DISPC_VID_FIR_COEF_H12_C(phase) (0xf4 + (phase) * 4)
130 #define DISPC_VID_FIR_COEF_V0(phase) (0x134 + (phase) *
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/kernel/linux/linux-5.10/drivers/hwmon/pmbus/
H A Dmp2975.c3 * Hardware monitoring driver for MPS Multi-phase Digital VR Controllers
90 mp2975_read_word_helper(struct i2c_client *client, int page, int phase, u8 reg, in mp2975_read_word_helper() argument
93 int ret = pmbus_read_word_data(client, page, phase, reg); in mp2975_read_word_helper()
122 int page, int phase, u8 reg) in mp2975_read_phase()
126 ret = pmbus_read_word_data(client, page, phase, reg); in mp2975_read_phase()
130 if (!((phase + 1) % MP2975_PAGE_NUM)) in mp2975_read_phase()
141 * - Rcs is the internal phase current sense resistor which is constant in mp2975_read_phase()
147 * Current phase sensing, providing by the device is not accurate in mp2975_read_phase()
150 * case phase current is represented as the maximum between the value in mp2975_read_phase()
153 ret = pmbus_read_word_data(client, page, phase, PMBUS_READ_IOU in mp2975_read_phase()
121 mp2975_read_phase(struct i2c_client *client, struct mp2975_data *data, int page, int phase, u8 reg) mp2975_read_phase() argument
162 mp2975_read_phases(struct i2c_client *client, struct mp2975_data *data, int page, int phase) mp2975_read_phases() argument
217 mp2975_read_word_data(struct i2c_client *client, int page, int phase, int reg) mp2975_read_word_data() argument
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H A Dir35221.c25 int phase, int reg) in ir35221_read_word_data()
31 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
35 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
39 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
43 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
47 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
51 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
55 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
59 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
24 ir35221_read_word_data(struct i2c_client *client, int page, int phase, int reg) ir35221_read_word_data() argument
/kernel/linux/linux-6.6/drivers/hwmon/pmbus/
H A Dmp2888.c3 * Hardware monitoring driver for MPS Multi-phase Digital VR Controllers
83 * Obtain resolution selector for total and phase current report and protection. in mp2888_current_sense_gain_and_resolution_get()
84 * 0: original resolution; 1: half resolution (in such case phase current value should in mp2888_current_sense_gain_and_resolution_get()
94 mp2888_read_phase(struct i2c_client *client, struct mp2888_data *data, int page, int phase, u8 reg) in mp2888_read_phase() argument
98 ret = pmbus_read_word_data(client, page, phase, reg); in mp2888_read_phase()
102 if (!((phase + 1) % 2)) in mp2888_read_phase()
113 * - Rcs is the internal phase current sense resistor. This parameter depends on hardware in mp2888_read_phase()
116 * If phase current resolution bit is set to 1, READ_CSx value should be doubled. in mp2888_read_phase()
117 * Note, that current phase sensing, providing by the device is not accurate. This is in mp2888_read_phase()
128 mp2888_read_phases(struct i2c_client *client, struct mp2888_data *data, int page, int phase) in mp2888_read_phases() argument
154 mp2888_read_word_data(struct i2c_client *client, int page, int phase, int reg) mp2888_read_word_data() argument
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H A Dir35221.c25 int phase, int reg) in ir35221_read_word_data()
31 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
35 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
39 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
43 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
47 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
51 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
55 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
59 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
24 ir35221_read_word_data(struct i2c_client *client, int page, int phase, int reg) ir35221_read_word_data() argument
H A Dmp2975.c3 * Hardware monitoring driver for MPS Multi-phase Digital VR Controllers
130 mp2975_read_word_helper(struct i2c_client *client, int page, int phase, u8 reg, in mp2975_read_word_helper() argument
133 int ret = pmbus_read_word_data(client, page, phase, reg); in mp2975_read_word_helper()
197 int page, int phase, u8 reg) in mp2975_read_phase()
201 ret = pmbus_read_word_data(client, page, phase, reg); in mp2975_read_phase()
205 if (!((phase + 1) % MP2975_PAGE_NUM)) in mp2975_read_phase()
216 * - Rcs is the internal phase current sense resistor which is constant in mp2975_read_phase()
222 * Current phase sensing, providing by the device is not accurate in mp2975_read_phase()
225 * case phase current is represented as the maximum between the value in mp2975_read_phase()
228 ret = pmbus_read_word_data(client, page, phase, PMBUS_READ_IOU in mp2975_read_phase()
196 mp2975_read_phase(struct i2c_client *client, struct mp2975_data *data, int page, int phase, u8 reg) mp2975_read_phase() argument
237 mp2975_read_phases(struct i2c_client *client, struct mp2975_data *data, int page, int phase) mp2975_read_phases() argument
292 mp2973_read_word_data(struct i2c_client *client, int page, int phase, int reg) mp2973_read_word_data() argument
380 mp2975_read_word_data(struct i2c_client *client, int page, int phase, int reg) mp2975_read_word_data() argument
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/kernel/linux/linux-5.10/include/trace/events/
H A Dclk.h156 TP_PROTO(struct clk_core *core, int phase),
158 TP_ARGS(core, phase),
162 __field( int, phase )
167 __entry->phase = phase;
170 TP_printk("%s %d", __get_str(name), (int)__entry->phase)
175 TP_PROTO(struct clk_core *core, int phase),
177 TP_ARGS(core, phase)
182 TP_PROTO(struct clk_core *core, int phase),
184 TP_ARGS(core, phase)
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/kernel/linux/linux-5.10/drivers/mmc/host/
H A Dsdhci-sirf.c77 int phase; in sdhci_sirf_execute_tuning() local
88 phase = 0; in sdhci_sirf_execute_tuning()
92 clock_setting | phase, in sdhci_sirf_execute_tuning()
98 dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n", in sdhci_sirf_execute_tuning()
99 mmc_hostname(mmc), phase); in sdhci_sirf_execute_tuning() local
101 start = phase; in sdhci_sirf_execute_tuning()
102 end = phase; in sdhci_sirf_execute_tuning()
104 if (phase == (SIRF_TUNING_COUNT - 1) in sdhci_sirf_execute_tuning()
108 dev_dbg(mmc_dev(mmc), "%s: Found bad phase = %d\n", in sdhci_sirf_execute_tuning()
109 mmc_hostname(mmc), phase); in sdhci_sirf_execute_tuning() local
130 mmc_hostname(mmc), phase); sdhci_sirf_execute_tuning() local
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/kernel/linux/linux-5.10/drivers/char/
H A Dppdev.c20 * SETPHASE set the IEEE 1284 phase of a particular mode. Not to be
37 * GETPHASE gets the current IEEE1284 phase
397 pp->saved_state.phase = info->phase; in pp_do_ioctl()
399 info->phase = pp->state.phase; in pp_do_ioctl()
428 pp->state.phase = init_phase(mode); in pp_do_ioctl()
432 pp->pdev->port->ieee1284.phase = pp->state.phase; in pp_do_ioctl()
452 int phase; in pp_do_ioctl() local
467 int phase; pp_do_ioctl() local
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/kernel/linux/linux-5.10/drivers/gpu/drm/imx/dcss/
H A Ddcss-scaler.c176 int phase; in dcss_scaler_gaussian_filter() local
181 for (phase = 0; phase < PSC_STORED_PHASES; phase++) { in dcss_scaler_gaussian_filter()
182 coef[phase][0] = 0; in dcss_scaler_gaussian_filter()
183 coef[phase][PSC_NUM_TAPS - 1] = 0; in dcss_scaler_gaussian_filter()
223 /* override phase 0 with identity filter if specified */ in dcss_scaler_gaussian_filter()
230 for (phase = 0; phase < PSC_STORED_PHASES; phase in dcss_scaler_gaussian_filter()
572 int i, phase; dcss_scaler_program_5_coef_set() local
607 int i, phase; dcss_scaler_program_7_coef_set() local
[all...]
/kernel/linux/linux-6.6/drivers/char/
H A Dppdev.c20 * SETPHASE set the IEEE 1284 phase of a particular mode. Not to be
37 * GETPHASE gets the current IEEE1284 phase
397 pp->saved_state.phase = info->phase; in pp_do_ioctl()
399 info->phase = pp->state.phase; in pp_do_ioctl()
428 pp->state.phase = init_phase(mode); in pp_do_ioctl()
432 pp->pdev->port->ieee1284.phase = pp->state.phase; in pp_do_ioctl()
452 int phase; in pp_do_ioctl() local
467 int phase; pp_do_ioctl() local
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/kernel/linux/linux-6.6/drivers/gpu/drm/imx/dcss/
H A Ddcss-scaler.c178 int phase; in dcss_scaler_gaussian_filter() local
183 for (phase = 0; phase < PSC_STORED_PHASES; phase++) { in dcss_scaler_gaussian_filter()
184 coef[phase][0] = 0; in dcss_scaler_gaussian_filter()
185 coef[phase][PSC_NUM_TAPS - 1] = 0; in dcss_scaler_gaussian_filter()
225 /* override phase 0 with identity filter if specified */ in dcss_scaler_gaussian_filter()
232 for (phase = 0; phase < PSC_STORED_PHASES; phase in dcss_scaler_gaussian_filter()
589 int i, phase; dcss_scaler_program_5_coef_set() local
624 int i, phase; dcss_scaler_program_7_coef_set() local
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/kernel/linux/linux-5.10/drivers/parport/
H A Dieee1284_ops.c52 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA; in parport_ieee1284_write_compat()
138 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE; in parport_ieee1284_write_compat()
171 port->ieee1284.phase = IEEE1284_PH_REV_DATA; in parport_ieee1284_read_nibble()
217 /* Go to reverse idle phase. */ in parport_ieee1284_read_nibble()
221 port->physport->ieee1284.phase = IEEE1284_PH_REV_IDLE; in parport_ieee1284_read_nibble()
224 port->physport->ieee1284.phase = IEEE1284_PH_HBUSY_DAVAIL; in parport_ieee1284_read_nibble()
259 port->physport->ieee1284.phase = IEEE1284_PH_REV_DATA; in parport_ieee1284_read_byte()
302 /* Go to reverse idle phase. */ in parport_ieee1284_read_byte()
306 port->physport->ieee1284.phase = IEEE1284_PH_REV_IDLE; in parport_ieee1284_read_byte()
309 port->physport->ieee1284.phase in parport_ieee1284_read_byte()
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/kernel/linux/linux-6.6/drivers/parport/
H A Dieee1284_ops.c52 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA; in parport_ieee1284_write_compat()
138 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE; in parport_ieee1284_write_compat()
171 port->ieee1284.phase = IEEE1284_PH_REV_DATA; in parport_ieee1284_read_nibble()
217 /* Go to reverse idle phase. */ in parport_ieee1284_read_nibble()
221 port->physport->ieee1284.phase = IEEE1284_PH_REV_IDLE; in parport_ieee1284_read_nibble()
224 port->physport->ieee1284.phase = IEEE1284_PH_HBUSY_DAVAIL; in parport_ieee1284_read_nibble()
259 port->physport->ieee1284.phase = IEEE1284_PH_REV_DATA; in parport_ieee1284_read_byte()
302 /* Go to reverse idle phase. */ in parport_ieee1284_read_byte()
306 port->physport->ieee1284.phase = IEEE1284_PH_REV_IDLE; in parport_ieee1284_read_byte()
309 port->physport->ieee1284.phase in parport_ieee1284_read_byte()
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/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gem/
H A Di915_gem_pm.c49 }, **phase; in i915_gem_suspend_late() local
75 for (phase = phases; *phase; phase++) { in i915_gem_suspend_late()
78 while ((obj = first_mm_object(*phase))) { in i915_gem_suspend_late()
96 list_splice_tail(&keep, *phase); in i915_gem_suspend_late()
/kernel/linux/linux-6.6/lib/zstd/compress/
H A Dzstd_cwksp.h153 ZSTD_cwksp_alloc_phase_e phase; member
268 * Moves the cwksp to the next phase, and does any necessary allocations.
269 * cwksp initialization must necessarily go through each phase in order.
273 ZSTD_cwksp_internal_advance_phase(ZSTD_cwksp* ws, ZSTD_cwksp_alloc_phase_e phase) in ZSTD_cwksp_internal_advance_phase() argument
275 assert(phase >= ws->phase); in ZSTD_cwksp_internal_advance_phase()
276 if (phase > ws->phase) { in ZSTD_cwksp_internal_advance_phase()
278 if (ws->phase < ZSTD_cwksp_alloc_buffers && in ZSTD_cwksp_internal_advance_phase()
279 phase > in ZSTD_cwksp_internal_advance_phase()
324 ZSTD_cwksp_reserve_internal(ZSTD_cwksp* ws, size_t bytes, ZSTD_cwksp_alloc_phase_e phase) ZSTD_cwksp_reserve_internal() argument
364 const ZSTD_cwksp_alloc_phase_e phase = ZSTD_cwksp_alloc_aligned; ZSTD_cwksp_reserve_table() local
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/kernel/linux/linux-6.6/drivers/net/wwan/iosm/
H A Diosm_ipc_imem_ops.c19 ipc_imem_phase_get_string(ipc_imem->phase), if_id); in ipc_imem_sys_wwan_open()
21 /* The network interface is only supported in the runtime phase. */ in ipc_imem_sys_wwan_open()
23 dev_err(ipc_imem->dev, "net:%d : refused phase %s", if_id, in ipc_imem_sys_wwan_open()
24 ipc_imem_phase_get_string(ipc_imem->phase)); in ipc_imem_sys_wwan_open()
66 if (ipc_imem->phase != IPC_P_RUN) { in ipc_imem_sys_wwan_transmit()
67 dev_dbg(ipc_imem->dev, "phase %s transmit", in ipc_imem_sys_wwan_transmit()
68 ipc_imem_phase_get_string(ipc_imem->phase)); in ipc_imem_sys_wwan_transmit()
146 enum ipc_phase phase; in ipc_imem_is_channel_active() local
148 /* Update the current operation phase. */ in ipc_imem_is_channel_active()
149 phase in ipc_imem_is_channel_active()
349 enum ipc_phase phase; ipc_imem_sys_devlink_open() local
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn21/
H A Ddcn21_dccg.c53 int phase; in dccg21_update_dpp_dto() local
57 * program DPP DTO phase and modulo as below in dccg21_update_dpp_dto()
58 * phase = ceiling(dpp_pipe_clk_mhz / 10) in dccg21_update_dpp_dto()
64 * ceiling phase and truncate modulo guarentees the divided in dccg21_update_dpp_dto()
67 phase = (req_dppclk + 9999) / 10000; in dccg21_update_dpp_dto()
69 if (phase > modulo) { in dccg21_update_dpp_dto()
70 /* phase > modulo result in screen corruption in dccg21_update_dpp_dto()
71 * ie phase = 30, mod = 29 for 4k@60 HDMI in dccg21_update_dpp_dto()
74 phase = modulo; in dccg21_update_dpp_dto()
78 * set phase t in dccg21_update_dpp_dto()
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