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/third_party/node/deps/openssl/openssl/crypto/asn1/
H A Da_utf8.c60 if (value < 0x800) in UTF8_getc()
104 if (value < 0x800) { in UTF8_putc()
/third_party/openssl/crypto/asn1/
H A Da_utf8.c60 if (value < 0x800) in UTF8_getc()
104 if (value < 0x800) { in UTF8_putc()
/kernel/linux/linux-5.10/drivers/net/ethernet/chelsio/cxgb4/
H A Dcxgb4_tc_u32.c188 /* Ensure that uhtid is either root u32 (i.e. 0x800) in cxgb4_config_knode()
191 if (uhtid != 0x800 && uhtid >= t->size) in cxgb4_config_knode()
213 if (uhtid != 0x800) { in cxgb4_config_knode()
299 if (uhtid != 0x800 && t->table[uhtid - 1].link_handle) { in cxgb4_config_knode()
345 if (uhtid != 0x800 && t->table[uhtid - 1].link_handle) in cxgb4_config_knode()
424 /* Ensure that uhtid is either root u32 (i.e. 0x800) in cxgb4_delete_knode()
427 if (uhtid != 0x800 && uhtid >= t->size) in cxgb4_delete_knode()
431 if (uhtid != 0x800) { in cxgb4_delete_knode()
/kernel/linux/linux-5.10/include/video/
H A Dsamsung_fimd.h162 #define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800) >> 11) << 23)
168 #define VIDTCON2_HOZVAL_E(_x) ((((_x) & 0x800) >> 11) << 22)
244 #define VIDOSDxA_TOPLEFT_X_E(_x) ((((_x) & 0x800) >> 11) << 23)
250 #define VIDOSDxA_TOPLEFT_Y_E(_x) ((((_x) & 0x800) >> 11) << 22)
256 #define VIDOSDxB_BOTRIGHT_X_E(_x) ((((_x) & 0x800) >> 11) << 23)
262 #define VIDOSDxB_BOTRIGHT_Y_E(_x) ((((_x) & 0x800) >> 11) << 22)
/kernel/linux/linux-6.6/include/video/
H A Dsamsung_fimd.h162 #define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800) >> 11) << 23)
168 #define VIDTCON2_HOZVAL_E(_x) ((((_x) & 0x800) >> 11) << 22)
244 #define VIDOSDxA_TOPLEFT_X_E(_x) ((((_x) & 0x800) >> 11) << 23)
250 #define VIDOSDxA_TOPLEFT_Y_E(_x) ((((_x) & 0x800) >> 11) << 22)
256 #define VIDOSDxB_BOTRIGHT_X_E(_x) ((((_x) & 0x800) >> 11) << 23)
262 #define VIDOSDxB_BOTRIGHT_Y_E(_x) ((((_x) & 0x800) >> 11) << 22)
/kernel/linux/linux-6.6/drivers/net/ethernet/chelsio/cxgb4/
H A Dcxgb4_tc_u32.c188 /* Ensure that uhtid is either root u32 (i.e. 0x800) in cxgb4_config_knode()
191 if (uhtid != 0x800 && uhtid >= t->size) in cxgb4_config_knode()
213 if (uhtid != 0x800) { in cxgb4_config_knode()
299 if (uhtid != 0x800 && t->table[uhtid - 1].link_handle) { in cxgb4_config_knode()
345 if (uhtid != 0x800 && t->table[uhtid - 1].link_handle) in cxgb4_config_knode()
424 /* Ensure that uhtid is either root u32 (i.e. 0x800) in cxgb4_delete_knode()
427 if (uhtid != 0x800 && uhtid >= t->size) in cxgb4_delete_knode()
431 if (uhtid != 0x800) { in cxgb4_delete_knode()
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Dgf119.c40 const u32 hoff = 0x800 * head; in gf119_sor_hda_device_entry()
88 const u32 hoff = head * 0x800; in gf119_sor_dp_watermark()
97 const u32 hoff = head * 0x800; in gf119_sor_dp_audio_sym()
107 const u32 hoff = 0x800 * head; in gf119_sor_dp_audio()
122 const u32 hoff = head * 0x800; in gf119_sor_dp_vcpi()
209 const u32 hoff = head * 0x800; in gf119_sor_hdmi_infoframe_vsi()
235 const u32 hoff = head * 0x800; in gf119_sor_hdmi_infoframe_avi()
259 const u32 hoff = head * 0x800; in gf119_sor_hdmi_ctrl()
402 const u32 hoff = head->id * 0x800; in gf119_head_vblank_put()
410 const u32 hoff = head->id * 0x800; in gf119_head_vblank_get()
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_8_0_sh_mask.h1057 #define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK 0x800
1183 #define CB_DEBUG_BUS_18__DAG_BUSY_MASK 0x800
1225 #define CB_DEBUG_BUS_19__DD_BUSY_MASK 0x800
1463 #define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800
1493 #define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800
1523 #define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800
1553 #define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800
1583 #define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800
1613 #define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800
1643 #define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_8_0_sh_mask.h1057 #define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK 0x800
1183 #define CB_DEBUG_BUS_18__DAG_BUSY_MASK 0x800
1225 #define CB_DEBUG_BUS_19__DD_BUSY_MASK 0x800
1463 #define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800
1493 #define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800
1523 #define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800
1553 #define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800
1583 #define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800
1613 #define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800
1643 #define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Dsorgf119.c32 const u32 hoff = head * 0x800; in gf119_sor_dp_watermark()
40 const u32 hoff = head * 0x800; in gf119_sor_dp_audio_sym()
49 const u32 hoff = 0x800 * head; in gf119_sor_dp_audio()
64 const u32 hoff = head * 0x800; in gf119_sor_dp_vcpi()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_2_sh_mask.h145 #define UVD_CGC_GATE__LRBBM_MASK 0x800
185 #define UVD_CGC_STATUS__RBC_SCLK_MASK 0x800
227 #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x800
289 #define UVD_CGC_UDEC_STATUS__DB_VCLK_MASK 0x800
355 #define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x800
403 #define UVD_LMI_STATUS__UMC_AVP_IDLE_MASK 0x800
593 #define UVD_SOFT_RESET__MPRD_SOFT_RESET_MASK 0x800
707 #define UVD_CGC_MEM_CTRL__SCPU_LS_EN_MASK 0x800
731 #define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT_MASK 0x800
H A Duvd_3_1_sh_mask.h145 #define UVD_CGC_GATE__LRBBM_MASK 0x800
185 #define UVD_CGC_STATUS__RBC_SCLK_MASK 0x800
227 #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x800
289 #define UVD_CGC_UDEC_STATUS__DB_VCLK_MASK 0x800
351 #define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x800
399 #define UVD_LMI_STATUS__UMC_AVP_IDLE_MASK 0x800
587 #define UVD_SOFT_RESET__MPRD_SOFT_RESET_MASK 0x800
701 #define UVD_CGC_MEM_CTRL__SCPU_LS_EN_MASK 0x800
725 #define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT_MASK 0x800
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_3_1_sh_mask.h145 #define UVD_CGC_GATE__LRBBM_MASK 0x800
185 #define UVD_CGC_STATUS__RBC_SCLK_MASK 0x800
227 #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x800
289 #define UVD_CGC_UDEC_STATUS__DB_VCLK_MASK 0x800
351 #define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x800
399 #define UVD_LMI_STATUS__UMC_AVP_IDLE_MASK 0x800
587 #define UVD_SOFT_RESET__MPRD_SOFT_RESET_MASK 0x800
701 #define UVD_CGC_MEM_CTRL__SCPU_LS_EN_MASK 0x800
725 #define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT_MASK 0x800
H A Duvd_4_2_sh_mask.h145 #define UVD_CGC_GATE__LRBBM_MASK 0x800
185 #define UVD_CGC_STATUS__RBC_SCLK_MASK 0x800
227 #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x800
289 #define UVD_CGC_UDEC_STATUS__DB_VCLK_MASK 0x800
355 #define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x800
403 #define UVD_LMI_STATUS__UMC_AVP_IDLE_MASK 0x800
593 #define UVD_SOFT_RESET__MPRD_SOFT_RESET_MASK 0x800
707 #define UVD_CGC_MEM_CTRL__SCPU_LS_EN_MASK 0x800
731 #define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT_MASK 0x800
/kernel/linux/linux-5.10/drivers/misc/habanalabs/include/goya/asic_reg/
H A Ddma_qm_0_masks.h48 #define DMA_QM_0_GLBL_CFG1_DMA_FLUSH_MASK 0x800
92 #define DMA_QM_0_GLBL_ERR_CFG_DMA_STOP_ON_ERR_MASK 0x800
156 #define DMA_QM_0_GLBL_STS1_DMA_WR_MSG_ERR_MASK 0x800
H A Dmme_cmdq_masks.h48 #define MME_CMDQ_GLBL_CFG1_DMA_FLUSH_MASK 0x800
92 #define MME_CMDQ_GLBL_ERR_CFG_DMA_STOP_ON_ERR_MASK 0x800
156 #define MME_CMDQ_GLBL_STS1_DMA_WR_MSG_ERR_MASK 0x800
H A Dmme_qm_masks.h48 #define MME_QM_GLBL_CFG1_DMA_FLUSH_MASK 0x800
92 #define MME_QM_GLBL_ERR_CFG_DMA_STOP_ON_ERR_MASK 0x800
156 #define MME_QM_GLBL_STS1_DMA_WR_MSG_ERR_MASK 0x800
H A Dtpc0_cmdq_masks.h48 #define TPC0_CMDQ_GLBL_CFG1_DMA_FLUSH_MASK 0x800
92 #define TPC0_CMDQ_GLBL_ERR_CFG_DMA_STOP_ON_ERR_MASK 0x800
156 #define TPC0_CMDQ_GLBL_STS1_DMA_WR_MSG_ERR_MASK 0x800
H A Dtpc0_qm_masks.h48 #define TPC0_QM_GLBL_CFG1_DMA_FLUSH_MASK 0x800
92 #define TPC0_QM_GLBL_ERR_CFG_DMA_STOP_ON_ERR_MASK 0x800
156 #define TPC0_QM_GLBL_STS1_DMA_WR_MSG_ERR_MASK 0x800
/kernel/linux/linux-5.10/drivers/pcmcia/
H A Dvrc4173_cardu.h84 #define EXCA_REGS_BASE 0x800
85 #define EXCA_REGS_SIZE 0x800
188 #define CARDBUS_SOCKET_REGS_SIZE 0x800
/kernel/linux/linux-6.6/drivers/accel/habanalabs/include/goya/asic_reg/
H A Dtpc0_qm_masks.h48 #define TPC0_QM_GLBL_CFG1_DMA_FLUSH_MASK 0x800
92 #define TPC0_QM_GLBL_ERR_CFG_DMA_STOP_ON_ERR_MASK 0x800
156 #define TPC0_QM_GLBL_STS1_DMA_WR_MSG_ERR_MASK 0x800
H A Ddma_qm_0_masks.h48 #define DMA_QM_0_GLBL_CFG1_DMA_FLUSH_MASK 0x800
92 #define DMA_QM_0_GLBL_ERR_CFG_DMA_STOP_ON_ERR_MASK 0x800
156 #define DMA_QM_0_GLBL_STS1_DMA_WR_MSG_ERR_MASK 0x800
H A Dmme_qm_masks.h48 #define MME_QM_GLBL_CFG1_DMA_FLUSH_MASK 0x800
92 #define MME_QM_GLBL_ERR_CFG_DMA_STOP_ON_ERR_MASK 0x800
156 #define MME_QM_GLBL_STS1_DMA_WR_MSG_ERR_MASK 0x800
H A Dmme_cmdq_masks.h48 #define MME_CMDQ_GLBL_CFG1_DMA_FLUSH_MASK 0x800
92 #define MME_CMDQ_GLBL_ERR_CFG_DMA_STOP_ON_ERR_MASK 0x800
156 #define MME_CMDQ_GLBL_STS1_DMA_WR_MSG_ERR_MASK 0x800
H A Dtpc0_cmdq_masks.h48 #define TPC0_CMDQ_GLBL_CFG1_DMA_FLUSH_MASK 0x800
92 #define TPC0_CMDQ_GLBL_ERR_CFG_DMA_STOP_ON_ERR_MASK 0x800
156 #define TPC0_CMDQ_GLBL_STS1_DMA_WR_MSG_ERR_MASK 0x800

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