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/third_party/rust/crates/libc/src/unix/linux_like/linux/uclibc/mips/
H A Dmod.rs140 pub const MAP_ANON: ::c_int = 0x800;
141 pub const MAP_ANONYMOUS: ::c_int = 0x800;
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_11_0_sh_mask.h105 #define DCPG_INTERRUPT_STATUS__DCFE5_POWER_DOWN_INT_OCCURRED_MASK 0x800
137 #define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_DOWN_INT_CLEAR_MASK 0x800
571 #define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x800
595 #define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x800
1313 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x800
2011 #define DMIF_CONTROL__DMIF_UNDERFLOW_RECOVERY_EN_MASK 0x800
2171 #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE_MASK 0x800
2279 #define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS_MASK 0x800
2307 #define DCI_MEM_PWR_STATUS__DMCU_IRAM_MEM_PWR_STATE_MASK 0x800
2369 #define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS_MASK 0x800
[all...]
H A Ddce_8_0_sh_mask.h553 #define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x800
577 #define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x800
1319 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x800
1513 #define DCCG_GATE_DISABLE_CNTL__SYMCLKD_GATE_DISABLE_MASK 0x800
2381 #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE_MASK 0x800
2459 #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT1_RDWR_TIMEOUT_DIS_MASK 0x800
2479 #define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT6_RDWR_TIMEOUT_DIS_MASK 0x800
2551 #define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS_MASK 0x800
2599 #define DCCG_VPCLK_CNTL__DMIF3_LIGHT_SLEEP_DIS_MASK 0x800
2657 #define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x800
[all...]
H A Ddce_10_0_sh_mask.h433 #define DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS_MASK 0x800
609 #define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x800
633 #define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x800
1409 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x800
2091 #define DMIF_CONTROL__DMIF_UNDERFLOW_RECOVERY_EN_MASK 0x800
2219 #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE_MASK 0x800
2329 #define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS_MASK 0x800
2359 #define DCI_MEM_PWR_STATUS__DMCU_IRAM_MEM_PWR_STATE_MASK 0x800
2421 #define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS_MASK 0x800
2471 #define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS_MASK 0x800
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_11_0_sh_mask.h105 #define DCPG_INTERRUPT_STATUS__DCFE5_POWER_DOWN_INT_OCCURRED_MASK 0x800
137 #define DCPG_INTERRUPT_CONTROL__DCFE2_POWER_DOWN_INT_CLEAR_MASK 0x800
571 #define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x800
595 #define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x800
1313 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x800
2011 #define DMIF_CONTROL__DMIF_UNDERFLOW_RECOVERY_EN_MASK 0x800
2171 #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE_MASK 0x800
2279 #define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS_MASK 0x800
2307 #define DCI_MEM_PWR_STATUS__DMCU_IRAM_MEM_PWR_STATE_MASK 0x800
2369 #define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS_MASK 0x800
[all...]
H A Ddce_8_0_sh_mask.h553 #define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x800
577 #define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x800
1319 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x800
1513 #define DCCG_GATE_DISABLE_CNTL__SYMCLKD_GATE_DISABLE_MASK 0x800
2381 #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE_MASK 0x800
2459 #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT1_RDWR_TIMEOUT_DIS_MASK 0x800
2479 #define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT6_RDWR_TIMEOUT_DIS_MASK 0x800
2551 #define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS_MASK 0x800
2599 #define DCCG_VPCLK_CNTL__DMIF3_LIGHT_SLEEP_DIS_MASK 0x800
2657 #define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x800
[all...]
H A Ddce_10_0_sh_mask.h433 #define DCFE_MEM_PWR_CTRL__DCP_CURSOR_MEM_PWR_DIS_MASK 0x800
609 #define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x800
633 #define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x800
1409 #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x800
2091 #define DMIF_CONTROL__DMIF_UNDERFLOW_RECOVERY_EN_MASK 0x800
2219 #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE_MASK 0x800
2329 #define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS_MASK 0x800
2359 #define DCI_MEM_PWR_STATUS__DMCU_IRAM_MEM_PWR_STATE_MASK 0x800
2421 #define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS_MASK 0x800
2471 #define DCI_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS_MASK 0x800
[all...]
/device/soc/rockchip/rk3588/kernel/drivers/soc/rockchip/
H A Dclk.h286 #define RK3588_CLKGATE_CON(x) ((x) * 0x4 + 0x800)
298 #define RK3588_PHP_CLKGATE_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE + 0x800)
303 #define RK3588_PMU_CLKGATE_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0x800)
308 #define RK3588_BIGCORE0_CLKGATE_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0x800)
312 #define RK3588_BIGCORE1_CLKGATE_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0x800)
316 #define RK3588_DSU_CLKGATE_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0x800)
/device/soc/rockchip/rk3588/kernel/drivers/clk/rockchip/
H A Dclk.h286 #define RK3588_CLKGATE_CON(x) ((x) * 0x4 + 0x800)
298 #define RK3588_PHP_CLKGATE_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE + 0x800)
303 #define RK3588_PMU_CLKGATE_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0x800)
308 #define RK3588_BIGCORE0_CLKGATE_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0x800)
312 #define RK3588_BIGCORE1_CLKGATE_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0x800)
316 #define RK3588_DSU_CLKGATE_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0x800)
/kernel/linux/linux-6.6/drivers/clk/rockchip/
H A Dclk.h250 #define RK3588_CLKGATE_CON(x) ((x) * 0x4 + 0x800)
262 #define RK3588_PHP_CLKGATE_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE + 0x800)
267 #define RK3588_PMU_CLKGATE_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0x800)
272 #define RK3588_BIGCORE0_CLKGATE_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0x800)
276 #define RK3588_BIGCORE1_CLKGATE_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0x800)
280 #define RK3588_DSU_CLKGATE_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0x800)
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Dnv50.c357 nvkm_mask(device, 0x614200 + (head->id * 0x800), 0x0000000f, div); in nv50_head_rgclk()
364 const u32 hoff = head->id * 0x800; in nv50_head_rgpos()
1512 tmp = nvkm_rd32(device, 0x616100 + (head->id * 0x800)); in nv50_disp_init()
1514 tmp = nvkm_rd32(device, 0x616104 + (head->id * 0x800)); in nv50_disp_init()
1516 tmp = nvkm_rd32(device, 0x616108 + (head->id * 0x800)); in nv50_disp_init()
1518 tmp = nvkm_rd32(device, 0x61610c + (head->id * 0x800)); in nv50_disp_init()
1524 tmp = nvkm_rd32(device, 0x61a000 + (i * 0x800)); in nv50_disp_init()
1530 tmp = nvkm_rd32(device, 0x61c000 + (i * 0x800)); in nv50_disp_init()
1536 tmp = nvkm_rd32(device, 0x61e000 + (i * 0x800)); in nv50_disp_init()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_7_1_sh_mask.h69 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP3_MASK 0x800
99 #define MC_ARB_RET_CREDITS2__HDP_RDRET_URG_MASK 0x800
139 #define MC_ARB_GECC2_STATUS__RSVD2_MASK 0x800
187 #define MC_ARB_GECC2_MISC__WRRDWR_REPLAY_AGAIN_MASK 0x800
285 #define MC_ARB_WCDR_2__DEBUG_2_MASK 0x800
395 #define MC_ARB_MISC2__POP_IDLE_REPLAY_MASK 0x800
473 #define MC_ARB_RAMCFG__RSV_3_MASK 0x800
559 #define MC_ARB_WTM_CNTL_RD__ACP_HARSH_PRI_MASK 0x800
585 #define MC_ARB_WTM_CNTL_WR__ACP_HARSH_PRI_MASK 0x800
777 #define MC_ARB_RFSH_CNTL__ACCUM_MASK 0x800
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_7_1_sh_mask.h69 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP3_MASK 0x800
99 #define MC_ARB_RET_CREDITS2__HDP_RDRET_URG_MASK 0x800
139 #define MC_ARB_GECC2_STATUS__RSVD2_MASK 0x800
187 #define MC_ARB_GECC2_MISC__WRRDWR_REPLAY_AGAIN_MASK 0x800
285 #define MC_ARB_WCDR_2__DEBUG_2_MASK 0x800
395 #define MC_ARB_MISC2__POP_IDLE_REPLAY_MASK 0x800
473 #define MC_ARB_RAMCFG__RSV_3_MASK 0x800
559 #define MC_ARB_WTM_CNTL_RD__ACP_HARSH_PRI_MASK 0x800
585 #define MC_ARB_WTM_CNTL_WR__ACP_HARSH_PRI_MASK 0x800
777 #define MC_ARB_RFSH_CNTL__ACCUM_MASK 0x800
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_2_4_sh_mask.h235 #define SEM_STATUS__VCE_MAILBOX_PENDING_MASK 0x800
327 #define SRBM_STATUS2__SDMA3_BUSY_MASK 0x800
363 #define SRBM_STATUS__MCC_BUSY_MASK 0x800
407 #define SRBM_STATUS3__MCD3_BUSY_MASK 0x800
437 #define SRBM_SOFT_RESET__SOFT_RESET_MC_MASK 0x800
567 #define SRBM_DEBUG_SNAPSHOT__REGBB_RDY_MASK 0x800
681 #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE0_MASK 0x800
1011 #define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x800
1137 #define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x800
1609 #define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x800
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_2_4_sh_mask.h235 #define SEM_STATUS__VCE_MAILBOX_PENDING_MASK 0x800
327 #define SRBM_STATUS2__SDMA3_BUSY_MASK 0x800
363 #define SRBM_STATUS__MCC_BUSY_MASK 0x800
407 #define SRBM_STATUS3__MCD3_BUSY_MASK 0x800
437 #define SRBM_SOFT_RESET__SOFT_RESET_MC_MASK 0x800
567 #define SRBM_DEBUG_SNAPSHOT__REGBB_RDY_MASK 0x800
681 #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE0_MASK 0x800
1011 #define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x800
1137 #define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x800
1609 #define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x800
[all...]
/kernel/linux/linux-5.10/drivers/net/ethernet/atheros/atl1c/
H A Datl1c_hw.h834 #define ANACTRL_LCKDET_PHY 0x800
886 #define SRDSYSMOD_PLL_EN 0x800
907 #define HIBNEG_GATE_25M_EN 0x800
921 #define TST10BTCFG_DIV_MAN_MLT3_EN 0x800
/kernel/linux/linux-6.6/drivers/net/ethernet/atheros/atl1c/
H A Datl1c_hw.h870 #define ANACTRL_LCKDET_PHY 0x800
922 #define SRDSYSMOD_PLL_EN 0x800
943 #define HIBNEG_GATE_25M_EN 0x800
957 #define TST10BTCFG_DIV_MAN_MLT3_EN 0x800
/third_party/rust/crates/libc/src/unix/linux_like/linux/gnu/b32/
H A Dpowerpc.rs184 pub const O_NDELAY: ::c_int = 0x800;
304 pub const EFD_NONBLOCK: ::c_int = 0x800;
336 pub const TAB2: ::tcflag_t = 0x800;
359 pub const CREAD: ::tcflag_t = 0x800;
/third_party/rust/crates/libc/src/unix/linux_like/linux/gnu/b32/sparc/
H A Dmod.rs203 pub const O_EXCL: ::c_int = 0x800;
370 pub const TAB1: ::tcflag_t = 0x800;
398 pub const CLOCAL: ::tcflag_t = 0x800;
399 pub const ECHOKE: ::tcflag_t = 0x800;
/third_party/rust/crates/libc/src/unix/linux_like/linux/gnu/b64/sparc64/
H A Dmod.rs210 pub const O_EXCL: ::c_int = 0x800;
449 pub const TAB1: ::tcflag_t = 0x800;
477 pub const CLOCAL: ::tcflag_t = 0x800;
478 pub const ECHOKE: ::tcflag_t = 0x800;
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/smu/
H A Dsmu_7_0_0_sh_mask.h97 #define GCK_DFS_BYPASS_CNTL__BYPASSSCLK_MASK 0x800
113 #define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE_MASK 0x800
129 #define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_MASK 0x800
191 #define CG_SPLL_FUNC_CNTL_5__PLLBYPASS_MASK 0x800
477 #define RCU_UC_EVENTS__FCH_HALT_MASK 0x800
601 #define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE_MASK 0x800
2183 #define FEATURE_STATUS__LHTC_ON_MASK 0x800
2951 #define GENERAL_PWRMGT__SPARE11_MASK 0x800
3001 #define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D1_MASK 0x800
3069 #define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/smu/
H A Dsmu_7_0_0_sh_mask.h97 #define GCK_DFS_BYPASS_CNTL__BYPASSSCLK_MASK 0x800
113 #define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE_MASK 0x800
129 #define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_MASK 0x800
191 #define CG_SPLL_FUNC_CNTL_5__PLLBYPASS_MASK 0x800
477 #define RCU_UC_EVENTS__FCH_HALT_MASK 0x800
601 #define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE_MASK 0x800
2183 #define FEATURE_STATUS__LHTC_ON_MASK 0x800
2951 #define GENERAL_PWRMGT__SPARE11_MASK 0x800
3001 #define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D1_MASK 0x800
3069 #define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
[all...]
/device/soc/hisilicon/common/platform/wifi/hi3881v100/driver/oal/
H A Dplat_board_adapt.h50 #define REG_PAD_CTRL_BASE (g_io_mux_base + 0x800)
/device/soc/hisilicon/common/platform/dmac/
H A Ddmac_hi35xx.h94 #define HIDMAC_CX_LLI_OFFSET_L(x) (0x800 + (x) * 0x40)
/device/soc/hisilicon/hi3861v100/sdk_liteos/platform/os/Huawei_LiteOS/components/lib/libc/musl/include/net/
H A Dif.h161 #define IFF_SLAVE 0x800

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