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/kernel/linux/linux-5.10/drivers/pcmcia/
H A Dyenta_socket.c142 u8 val = readb(socket->base + 0x800 + reg); in exca_readb()
150 val = readb(socket->base + 0x800 + reg); in exca_readw()
151 val |= readb(socket->base + 0x800 + reg + 1) << 8; in exca_readw()
159 writeb(val, socket->base + 0x800 + reg); in exca_writeb()
160 readb(socket->base + 0x800 + reg); /* PCI write posting... */ in exca_writeb()
166 writeb(val, socket->base + 0x800 + reg); in exca_writew()
167 writeb(val >> 8, socket->base + 0x800 + reg + 1); in exca_writew()
170 readb(socket->base + 0x800 + reg); in exca_writew()
171 readb(socket->base + 0x800 + reg + 1); in exca_writew()
/kernel/linux/linux-5.10/arch/arm64/include/asm/
H A Dunistd.h39 #define __ARM_NR_COMPAT_END (__ARM_NR_COMPAT_BASE + 0x800)
/kernel/linux/linux-5.10/arch/powerpc/include/asm/book3s/32/
H A Dhash.h31 #define _PAGE_SPECIAL 0x800 /* software: Special page */
/kernel/linux/linux-6.6/arch/arm64/include/asm/
H A Dbrk-imm.h18 * 0x800: kernel-mode BUG() and WARN() traps
29 #define BUG_BRK_IMM 0x800
/third_party/musl/arch/i386/bits/
H A Dfenv.h12 #define FE_UPWARD 0x800
/third_party/musl/arch/x32/bits/
H A Dfenv.h12 #define FE_UPWARD 0x800
/third_party/musl/arch/x86_64/bits/
H A Dfenv.h12 #define FE_UPWARD 0x800
/kernel/linux/linux-5.10/drivers/bus/fsl-mc/
H A Dfsl-mc-private.h48 #define DPMCP_CMDID_CLOSE DPMCP_CMD(0x800)
91 #define DPRC_CMDID_CLOSE DPRC_CMD(0x800)
452 #define DPBP_CMDID_CLOSE DPBP_CMD(0x800)
491 #define DPCON_CMDID_CLOSE DPCON_CMD(0x800)
/kernel/linux/linux-5.10/drivers/misc/habanalabs/include/gaudi/asic_reg/
H A Dmme0_qm_masks.h154 #define MME0_QM_GLBL_STS1_CP_FENCE3_OVF_ERR_MASK 0x800
184 #define MME0_QM_GLBL_STS1_4_CP_FENCE3_OVF_ERR_MASK 0x800
216 #define MME0_QM_GLBL_MSG_EN_CP_FENCE3_OVF_ERR_MASK 0x800
246 #define MME0_QM_GLBL_MSG_EN_4_CP_FENCE3_OVF_ERR_MASK 0x800
H A Ddma0_qm_masks.h154 #define DMA0_QM_GLBL_STS1_CP_FENCE3_OVF_ERR_MASK 0x800
184 #define DMA0_QM_GLBL_STS1_4_CP_FENCE3_OVF_ERR_MASK 0x800
216 #define DMA0_QM_GLBL_MSG_EN_CP_FENCE3_OVF_ERR_MASK 0x800
246 #define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE3_OVF_ERR_MASK 0x800
H A Dtpc0_qm_masks.h154 #define TPC0_QM_GLBL_STS1_CP_FENCE3_OVF_ERR_MASK 0x800
184 #define TPC0_QM_GLBL_STS1_4_CP_FENCE3_OVF_ERR_MASK 0x800
216 #define TPC0_QM_GLBL_MSG_EN_CP_FENCE3_OVF_ERR_MASK 0x800
246 #define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE3_OVF_ERR_MASK 0x800
/kernel/linux/linux-5.10/drivers/net/ethernet/atheros/atl1e/
H A Datl1e_hw.h74 #define SPI_FLASH_CTRL_START 0x800
117 #define TWSI_CTRL_SW_LDSTART 0x800
181 #define GPHY_CTRL_HIB_PULSE 0x800
546 #define ISR_DMAW_TO_RST 0x800
/kernel/linux/linux-5.10/sound/soc/codecs/
H A Drt715-sdw.c190 reg |= 0x800; in rt715_sdw_read()
385 if (verb & 0x800) /* get command */ in hda_to_sdw()
393 if ((verb & 0x800) == 0x800) { /* read */ in hda_to_sdw()
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Dgv100.c351 tmp = nvkm_rd32(device, 0x61c000 + (i * 0x800)); in gv100_disp_init()
361 tmp = nvkm_rd32(device, 0x616300 + (id * 0x800)); in gv100_disp_init()
366 tmp = nvkm_rd32(device, 0x616100 + (id * 0x800) + j); in gv100_disp_init()
375 tmp = nvkm_rd32(device, 0x630050 + (i * 0x800) + j); in gv100_disp_init()
/kernel/linux/linux-6.6/drivers/net/ethernet/atheros/atl1e/
H A Datl1e_hw.h74 #define SPI_FLASH_CTRL_START 0x800
117 #define TWSI_CTRL_SW_LDSTART 0x800
181 #define GPHY_CTRL_HIB_PULSE 0x800
546 #define ISR_DMAW_TO_RST 0x800
/kernel/linux/linux-6.6/drivers/accel/habanalabs/include/gaudi/asic_reg/
H A Ddma0_qm_masks.h154 #define DMA0_QM_GLBL_STS1_CP_FENCE3_OVF_ERR_MASK 0x800
184 #define DMA0_QM_GLBL_STS1_4_CP_FENCE3_OVF_ERR_MASK 0x800
216 #define DMA0_QM_GLBL_MSG_EN_CP_FENCE3_OVF_ERR_MASK 0x800
246 #define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE3_OVF_ERR_MASK 0x800
H A Dmme0_qm_masks.h154 #define MME0_QM_GLBL_STS1_CP_FENCE3_OVF_ERR_MASK 0x800
184 #define MME0_QM_GLBL_STS1_4_CP_FENCE3_OVF_ERR_MASK 0x800
216 #define MME0_QM_GLBL_MSG_EN_CP_FENCE3_OVF_ERR_MASK 0x800
246 #define MME0_QM_GLBL_MSG_EN_4_CP_FENCE3_OVF_ERR_MASK 0x800
H A Dtpc0_qm_masks.h154 #define TPC0_QM_GLBL_STS1_CP_FENCE3_OVF_ERR_MASK 0x800
184 #define TPC0_QM_GLBL_STS1_4_CP_FENCE3_OVF_ERR_MASK 0x800
216 #define TPC0_QM_GLBL_MSG_EN_CP_FENCE3_OVF_ERR_MASK 0x800
246 #define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE3_OVF_ERR_MASK 0x800
H A Dnic0_qm0_masks.h154 #define NIC0_QM0_GLBL_STS1_CP_FENCE3_OVF_ERR_MASK 0x800
184 #define NIC0_QM0_GLBL_STS1_4_CP_FENCE3_OVF_ERR_MASK 0x800
216 #define NIC0_QM0_GLBL_MSG_EN_CP_FENCE3_OVF_ERR_MASK 0x800
246 #define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE3_OVF_ERR_MASK 0x800
/kernel/linux/linux-6.6/sound/soc/codecs/
H A Drt715-sdw.c191 reg |= 0x800; in rt715_sdw_read()
386 if (verb & 0x800) /* get command */ in hda_to_sdw()
394 if ((verb & 0x800) == 0x800) { /* read */ in hda_to_sdw()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_5_0_sh_mask.h153 #define HW_DEBUG__HW_11_DEBUG_MASK 0x800
285 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK 0x800
323 #define BIF_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK 0x800
447 #define GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x800
471 #define GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x800
571 #define BACO_CNTL__PWRGOOD_MEM_MASK 0x800
735 #define GARLIC_FLUSH_CNTL__VCE_RB_WPTR2_MASK 0x800
843 #define GPU_GARLIC_FLUSH_REQ__SDMA1_MASK 0x800
871 #define GPU_GARLIC_FLUSH_DONE__SDMA1_MASK 0x800
1071 #define STATUS__SIGNAL_TARGET_ABORT_MASK 0x800
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_5_0_sh_mask.h153 #define HW_DEBUG__HW_11_DEBUG_MASK 0x800
285 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK 0x800
323 #define BIF_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK 0x800
447 #define GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x800
471 #define GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x800
571 #define BACO_CNTL__PWRGOOD_MEM_MASK 0x800
735 #define GARLIC_FLUSH_CNTL__VCE_RB_WPTR2_MASK 0x800
843 #define GPU_GARLIC_FLUSH_REQ__SDMA1_MASK 0x800
871 #define GPU_GARLIC_FLUSH_DONE__SDMA1_MASK 0x800
1071 #define STATUS__SIGNAL_TARGET_ABORT_MASK 0x800
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_8_1_sh_mask.h1037 #define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION_MASK 0x800
1067 #define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK 0x800
1169 #define CB_DEBUG_BUS_1__CB_TAP_WRREQ_VALIDB_READY_MASK 0x800
1217 #define CB_DEBUG_BUS_2__FOP_FMASK_BYPASS_STALL_MASK 0x800
1265 #define CB_DEBUG_BUS_3__LQUAD_NO_TILE_MASK 0x800
1313 #define CB_DEBUG_BUS_4__FC_CACHE_REPLACE_PENDING_EVICT_STALL_MASK 0x800
1407 #define CB_DEBUG_BUS_9__TWO_PROBE_QUAD_FRAGMENT_MASK 0x800
1449 #define CB_DEBUG_BUS_10__CMASK_WRITE_DATA_0XE_MASK 0x800
1497 #define CB_DEBUG_BUS_11__FOP_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE_MASK 0x800
1545 #define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_1_MASK 0x800
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_8_1_sh_mask.h1037 #define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION_MASK 0x800
1067 #define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK 0x800
1169 #define CB_DEBUG_BUS_1__CB_TAP_WRREQ_VALIDB_READY_MASK 0x800
1217 #define CB_DEBUG_BUS_2__FOP_FMASK_BYPASS_STALL_MASK 0x800
1265 #define CB_DEBUG_BUS_3__LQUAD_NO_TILE_MASK 0x800
1313 #define CB_DEBUG_BUS_4__FC_CACHE_REPLACE_PENDING_EVICT_STALL_MASK 0x800
1407 #define CB_DEBUG_BUS_9__TWO_PROBE_QUAD_FRAGMENT_MASK 0x800
1449 #define CB_DEBUG_BUS_10__CMASK_WRITE_DATA_0XE_MASK 0x800
1497 #define CB_DEBUG_BUS_11__FOP_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE_MASK 0x800
1545 #define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_1_MASK 0x800
[all...]
/kernel/linux/linux-5.10/arch/arm/mach-imx/
H A Dcpu-imx27.c21 #define SYSCTRL_OFFSET 0x800 /* Offset from CCM base address */

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