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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_3_1_sh_mask.h141 #define UVD_CGC_GATE__MPC_MASK 0x200
181 #define UVD_CGC_STATUS__REGS_SCLK_MASK 0x200
285 #define UVD_CGC_UDEC_STATUS__DB_SCLK_MASK 0x200
349 #define UVD_LMI_CTRL__REQ_MODE_MASK 0x200
395 #define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x200
543 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x200
583 #define UVD_SOFT_RESET__FWV_SOFT_RESET_MASK 0x200
697 #define UVD_CGC_MEM_CTRL__SYS_LS_EN_MASK 0x200
721 #define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP_MASK 0x200
H A Duvd_4_2_sh_mask.h141 #define UVD_CGC_GATE__MPC_MASK 0x200
181 #define UVD_CGC_STATUS__REGS_SCLK_MASK 0x200
285 #define UVD_CGC_UDEC_STATUS__DB_SCLK_MASK 0x200
353 #define UVD_LMI_CTRL__REQ_MODE_MASK 0x200
399 #define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x200
547 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x200
589 #define UVD_SOFT_RESET__FWV_SOFT_RESET_MASK 0x200
703 #define UVD_CGC_MEM_CTRL__SYS_LS_EN_MASK 0x200
727 #define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP_MASK 0x200
H A Duvd_6_0_sh_mask.h155 #define UVD_CGC_GATE__MPC_MASK 0x200
199 #define UVD_CGC_STATUS__REGS_SCLK_MASK 0x200
311 #define UVD_CGC_UDEC_STATUS__DB_SCLK_MASK 0x200
387 #define UVD_LMI_CTRL__REQ_MODE_MASK 0x200
433 #define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x200
581 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x200
623 #define UVD_SOFT_RESET__JPEG_SCLK_RESET_STATUS_MASK 0x200
743 #define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x200
769 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK 0x200
863 #define UVD_CGC_MEM_CTRL__SYS_LS_EN_MASK 0x200
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H A Duvd_5_0_sh_mask.h153 #define UVD_CGC_GATE__MPC_MASK 0x200
197 #define UVD_CGC_STATUS__REGS_SCLK_MASK 0x200
309 #define UVD_CGC_UDEC_STATUS__DB_SCLK_MASK 0x200
385 #define UVD_LMI_CTRL__REQ_MODE_MASK 0x200
431 #define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x200
579 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x200
621 #define UVD_SOFT_RESET__JPEG_SCLK_RESET_STATUS_MASK 0x200
741 #define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x200
771 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK 0x200
873 #define UVD_CGC_MEM_CTRL__SYS_LS_EN_MASK 0x200
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/kernel/linux/linux-5.10/arch/powerpc/platforms/52xx/
H A Dlite5200_pm.c78 cdm = mbar + 0x200; in lite5200_pm_prepare()
97 static char spci[0x200];
107 _memcpy_fromio(spci, pci, 0x200); in lite5200_save_regs()
118 _memcpy_toio(pci, spci, 0x200); in lite5200_restore_regs()
/kernel/linux/linux-6.6/arch/powerpc/platforms/52xx/
H A Dlite5200_pm.c77 cdm = mbar + 0x200; in lite5200_pm_prepare()
96 static char spci[0x200];
106 _memcpy_fromio(spci, pci, 0x200); in lite5200_save_regs()
117 _memcpy_toio(pci, spci, 0x200); in lite5200_restore_regs()
/kernel/linux/linux-5.10/drivers/net/ethernet/marvell/octeontx2/nic/
H A Dotx2_reg.h21 #define RVU_PF_BLOCK_ADDRX_DISC(a) (0x200 | (a) << 3)
56 #define RVU_VF_BLOCK_ADDRX_DISC(a) (0x200 | (a) << 3)
81 #define NPA_LF_ERR_INT (NPA_LFBASE | 0x200)
99 #define NIX_LF_GINT (NIX_LFBASE | 0x200)
/kernel/linux/linux-6.6/drivers/net/ethernet/marvell/octeontx2/nic/
H A Dotx2_reg.h18 #define RVU_PF_BLOCK_ADDRX_DISC(a) (0x200 | (a) << 3)
55 #define RVU_VF_BLOCK_ADDRX_DISC(a) (0x200 | (a) << 3)
81 #define NPA_LF_ERR_INT (NPA_LFBASE | 0x200)
100 #define NIX_LF_GINT (NIX_LFBASE | 0x200)
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_5_0_sh_mask.h153 #define UVD_CGC_GATE__MPC_MASK 0x200
197 #define UVD_CGC_STATUS__REGS_SCLK_MASK 0x200
309 #define UVD_CGC_UDEC_STATUS__DB_SCLK_MASK 0x200
385 #define UVD_LMI_CTRL__REQ_MODE_MASK 0x200
431 #define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x200
579 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x200
621 #define UVD_SOFT_RESET__JPEG_SCLK_RESET_STATUS_MASK 0x200
741 #define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x200
771 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK 0x200
873 #define UVD_CGC_MEM_CTRL__SYS_LS_EN_MASK 0x200
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H A Duvd_6_0_sh_mask.h155 #define UVD_CGC_GATE__MPC_MASK 0x200
199 #define UVD_CGC_STATUS__REGS_SCLK_MASK 0x200
311 #define UVD_CGC_UDEC_STATUS__DB_SCLK_MASK 0x200
387 #define UVD_LMI_CTRL__REQ_MODE_MASK 0x200
433 #define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x200
581 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x200
623 #define UVD_SOFT_RESET__JPEG_SCLK_RESET_STATUS_MASK 0x200
743 #define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x200
769 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK 0x200
863 #define UVD_CGC_MEM_CTRL__SYS_LS_EN_MASK 0x200
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/kernel/linux/linux-6.6/arch/microblaze/lib/
H A Duaccess_old.S120 addik r6, r6, 0x200
121 addik r7, r7, -0x200
123 addik r5, r5, 0x200
/kernel/linux/linux-5.10/drivers/misc/habanalabs/include/goya/asic_reg/
H A Ddma_qm_0_masks.h44 #define DMA_QM_0_GLBL_CFG1_CQF_FLUSH_MASK 0x200
88 #define DMA_QM_0_GLBL_ERR_CFG_DMA_ERR_INT_EN_MASK 0x200
152 #define DMA_QM_0_GLBL_STS1_DMA_WR_ERR_MASK 0x200
H A Dmme_cmdq_masks.h44 #define MME_CMDQ_GLBL_CFG1_CQF_FLUSH_MASK 0x200
88 #define MME_CMDQ_GLBL_ERR_CFG_DMA_ERR_INT_EN_MASK 0x200
152 #define MME_CMDQ_GLBL_STS1_DMA_WR_ERR_MASK 0x200
H A Dmme_qm_masks.h44 #define MME_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x200
88 #define MME_QM_GLBL_ERR_CFG_DMA_ERR_INT_EN_MASK 0x200
152 #define MME_QM_GLBL_STS1_DMA_WR_ERR_MASK 0x200
H A Dtpc0_cmdq_masks.h44 #define TPC0_CMDQ_GLBL_CFG1_CQF_FLUSH_MASK 0x200
88 #define TPC0_CMDQ_GLBL_ERR_CFG_DMA_ERR_INT_EN_MASK 0x200
152 #define TPC0_CMDQ_GLBL_STS1_DMA_WR_ERR_MASK 0x200
H A Dtpc0_qm_masks.h44 #define TPC0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x200
88 #define TPC0_QM_GLBL_ERR_CFG_DMA_ERR_INT_EN_MASK 0x200
152 #define TPC0_QM_GLBL_STS1_DMA_WR_ERR_MASK 0x200
/kernel/linux/linux-5.10/drivers/soc/fsl/qe/
H A Dqe_tdm.c166 &siram[siram_entry_id * 32 + 0x200 + i]); in ucc_tdm_init()
169 &siram[siram_entry_id * 32 + 0x200 + i]); in ucc_tdm_init()
174 qe_setbits_be16(&siram[(siram_entry_id * 32) + 0x200 + (utdm->num_of_ts - 1)], in ucc_tdm_init()
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/pm/
H A Dgf100.c204 ret = nvkm_perfdom_new(pm, "hub", 0, 0x1b0000, 0, 0x200, in gf100_pm_new_()
215 0x1000, 0x200, func->doms_gpc); in gf100_pm_new_()
225 0x1000, 0x200, func->doms_part); in gf100_pm_new_()
/kernel/linux/linux-6.6/drivers/accel/habanalabs/include/goya/asic_reg/
H A Dtpc0_qm_masks.h44 #define TPC0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x200
88 #define TPC0_QM_GLBL_ERR_CFG_DMA_ERR_INT_EN_MASK 0x200
152 #define TPC0_QM_GLBL_STS1_DMA_WR_ERR_MASK 0x200
H A Ddma_qm_0_masks.h44 #define DMA_QM_0_GLBL_CFG1_CQF_FLUSH_MASK 0x200
88 #define DMA_QM_0_GLBL_ERR_CFG_DMA_ERR_INT_EN_MASK 0x200
152 #define DMA_QM_0_GLBL_STS1_DMA_WR_ERR_MASK 0x200
H A Dmme_qm_masks.h44 #define MME_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x200
88 #define MME_QM_GLBL_ERR_CFG_DMA_ERR_INT_EN_MASK 0x200
152 #define MME_QM_GLBL_STS1_DMA_WR_ERR_MASK 0x200
H A Dmme_cmdq_masks.h44 #define MME_CMDQ_GLBL_CFG1_CQF_FLUSH_MASK 0x200
88 #define MME_CMDQ_GLBL_ERR_CFG_DMA_ERR_INT_EN_MASK 0x200
152 #define MME_CMDQ_GLBL_STS1_DMA_WR_ERR_MASK 0x200
H A Dtpc0_cmdq_masks.h44 #define TPC0_CMDQ_GLBL_CFG1_CQF_FLUSH_MASK 0x200
88 #define TPC0_CMDQ_GLBL_ERR_CFG_DMA_ERR_INT_EN_MASK 0x200
152 #define TPC0_CMDQ_GLBL_STS1_DMA_WR_ERR_MASK 0x200
/kernel/linux/linux-6.6/drivers/soc/fsl/qe/
H A Dqe_tdm.c164 &siram[siram_entry_id * 32 + 0x200 + i]); in ucc_tdm_init()
167 &siram[siram_entry_id * 32 + 0x200 + i]); in ucc_tdm_init()
172 qe_setbits_be16(&siram[(siram_entry_id * 32) + 0x200 + (utdm->num_of_ts - 1)], in ucc_tdm_init()
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/engine/pm/
H A Dgf100.c204 ret = nvkm_perfdom_new(pm, "hub", 0, 0x1b0000, 0, 0x200, in gf100_pm_new_()
215 0x1000, 0x200, func->doms_gpc); in gf100_pm_new_()
225 0x1000, 0x200, func->doms_part); in gf100_pm_new_()

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