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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/mmhub/
H A Dmmhub_9_1_sh_mask.h771 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
788 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
805 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
1877 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
1894 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
1911 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
2483 #define DAGB0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
2494 #define DAGB0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
2505 #define DAGB0_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
4105 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/mmhub/
H A Dmmhub_9_1_sh_mask.h771 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
788 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
805 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
1877 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
1894 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
1911 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
2483 #define DAGB0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
2494 #define DAGB0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
2505 #define DAGB0_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
4105 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/sdma4/
H A Dsdma4_4_2_2_sh_mask.h184 #define SDMA4_PUB_REG_TYPE0__SDMA4_CHICKEN_BITS__SHIFT 0x1d
244 #define SDMA4_PUB_REG_TYPE1__SDMA4_UTCL1_WATERMK__SHIFT 0x1d
309 #define SDMA4_PUB_REG_TYPE2__SDMA4_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d
379 #define SDMA4_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
403 #define SDMA4_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
703 #define SDMA4_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d
744 #define SDMA4_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d
800 #define SDMA4_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d
928 #define SDMA4_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d
1054 #define SDMA4_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/sdma7/
H A Dsdma7_4_2_2_sh_mask.h184 #define SDMA7_PUB_REG_TYPE0__SDMA7_CHICKEN_BITS__SHIFT 0x1d
244 #define SDMA7_PUB_REG_TYPE1__SDMA7_UTCL1_WATERMK__SHIFT 0x1d
309 #define SDMA7_PUB_REG_TYPE2__SDMA7_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d
379 #define SDMA7_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
403 #define SDMA7_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
703 #define SDMA7_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d
744 #define SDMA7_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d
800 #define SDMA7_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d
928 #define SDMA7_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d
1054 #define SDMA7_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/sdma6/
H A Dsdma6_4_2_2_sh_mask.h184 #define SDMA6_PUB_REG_TYPE0__SDMA6_CHICKEN_BITS__SHIFT 0x1d
244 #define SDMA6_PUB_REG_TYPE1__SDMA6_UTCL1_WATERMK__SHIFT 0x1d
309 #define SDMA6_PUB_REG_TYPE2__SDMA6_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d
379 #define SDMA6_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
403 #define SDMA6_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
703 #define SDMA6_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d
744 #define SDMA6_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d
800 #define SDMA6_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d
928 #define SDMA6_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d
1054 #define SDMA6_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_2_4_sh_mask.h384 #define SRBM_STATUS__BIF_BUSY__SHIFT 0x1d
474 #define SRBM_SOFT_RESET__SOFT_RESET_GRN__SHIFT 0x1d
604 #define SRBM_DEBUG_SNAPSHOT__VCE0_RDY__SHIFT 0x1d
636 #define SRBM_READ_ERROR__READ_REQUESTER_UVD__SHIFT 0x1d
884 #define SYS_GRBM_GFX_INDEX_DATA__SH_BROADCAST_WRITES__SHIFT 0x1d
928 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
950 #define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
1526 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
1548 #define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
2084 #define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT 0x1d
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_2_2_sh_mask.h184 #define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT 0x1d
244 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK__SHIFT 0x1d
309 #define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d
389 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
413 #define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
749 #define SDMA0_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d
790 #define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d
846 #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d
974 #define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d
1100 #define SDMA0_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d
[all...]
H A Dsdma0_4_2_sh_mask.h184 #define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT 0x1d
244 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK__SHIFT 0x1d
307 #define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d
383 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
407 #define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
743 #define SDMA0_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d
784 #define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d
840 #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d
968 #define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d
1093 #define SDMA0_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/sdma3/
H A Dsdma3_4_2_2_sh_mask.h184 #define SDMA3_PUB_REG_TYPE0__SDMA3_CHICKEN_BITS__SHIFT 0x1d
244 #define SDMA3_PUB_REG_TYPE1__SDMA3_UTCL1_WATERMK__SHIFT 0x1d
309 #define SDMA3_PUB_REG_TYPE2__SDMA3_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d
379 #define SDMA3_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
403 #define SDMA3_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
703 #define SDMA3_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d
744 #define SDMA3_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d
800 #define SDMA3_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d
928 #define SDMA3_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d
1054 #define SDMA3_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/sdma2/
H A Dsdma2_4_2_2_sh_mask.h184 #define SDMA2_PUB_REG_TYPE0__SDMA2_CHICKEN_BITS__SHIFT 0x1d
244 #define SDMA2_PUB_REG_TYPE1__SDMA2_UTCL1_WATERMK__SHIFT 0x1d
309 #define SDMA2_PUB_REG_TYPE2__SDMA2_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d
379 #define SDMA2_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
403 #define SDMA2_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
703 #define SDMA2_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d
744 #define SDMA2_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d
800 #define SDMA2_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d
928 #define SDMA2_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d
1054 #define SDMA2_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/sdma1/
H A Dsdma1_4_2_2_sh_mask.h184 #define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS__SHIFT 0x1d
244 #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WATERMK__SHIFT 0x1d
309 #define SDMA1_PUB_REG_TYPE2__SDMA1_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d
379 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
403 #define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
703 #define SDMA1_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d
744 #define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d
800 #define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d
928 #define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d
1054 #define SDMA1_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d
[all...]
H A Dsdma1_4_2_sh_mask.h185 #define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS__SHIFT 0x1d
246 #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WATERMK__SHIFT 0x1d
309 #define SDMA1_PUB_REG_TYPE2__SDMA1_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d
375 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
399 #define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
699 #define SDMA1_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d
740 #define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d
796 #define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d
924 #define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d
1049 #define SDMA1_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/sdma5/
H A Dsdma5_4_2_2_sh_mask.h184 #define SDMA5_PUB_REG_TYPE0__SDMA5_CHICKEN_BITS__SHIFT 0x1d
244 #define SDMA5_PUB_REG_TYPE1__SDMA5_UTCL1_WATERMK__SHIFT 0x1d
309 #define SDMA5_PUB_REG_TYPE2__SDMA5_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d
379 #define SDMA5_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
403 #define SDMA5_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
703 #define SDMA5_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d
744 #define SDMA5_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d
800 #define SDMA5_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d
928 #define SDMA5_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d
1054 #define SDMA5_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_2_2_sh_mask.h184 #define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT 0x1d
244 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK__SHIFT 0x1d
309 #define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d
389 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
413 #define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
749 #define SDMA0_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d
790 #define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d
846 #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d
974 #define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d
1100 #define SDMA0_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d
[all...]
H A Dsdma0_4_2_sh_mask.h184 #define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT 0x1d
244 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK__SHIFT 0x1d
307 #define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d
383 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
407 #define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
743 #define SDMA0_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d
784 #define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d
840 #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d
968 #define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d
1093 #define SDMA0_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_2_4_sh_mask.h384 #define SRBM_STATUS__BIF_BUSY__SHIFT 0x1d
474 #define SRBM_SOFT_RESET__SOFT_RESET_GRN__SHIFT 0x1d
604 #define SRBM_DEBUG_SNAPSHOT__VCE0_RDY__SHIFT 0x1d
636 #define SRBM_READ_ERROR__READ_REQUESTER_UVD__SHIFT 0x1d
884 #define SYS_GRBM_GFX_INDEX_DATA__SH_BROADCAST_WRITES__SHIFT 0x1d
928 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
950 #define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
1526 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
1548 #define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
2084 #define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT 0x1d
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/sdma5/
H A Dsdma5_4_2_2_sh_mask.h184 #define SDMA5_PUB_REG_TYPE0__SDMA5_CHICKEN_BITS__SHIFT 0x1d
244 #define SDMA5_PUB_REG_TYPE1__SDMA5_UTCL1_WATERMK__SHIFT 0x1d
309 #define SDMA5_PUB_REG_TYPE2__SDMA5_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d
379 #define SDMA5_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
403 #define SDMA5_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
703 #define SDMA5_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d
744 #define SDMA5_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d
800 #define SDMA5_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d
928 #define SDMA5_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d
1054 #define SDMA5_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/sdma4/
H A Dsdma4_4_2_2_sh_mask.h184 #define SDMA4_PUB_REG_TYPE0__SDMA4_CHICKEN_BITS__SHIFT 0x1d
244 #define SDMA4_PUB_REG_TYPE1__SDMA4_UTCL1_WATERMK__SHIFT 0x1d
309 #define SDMA4_PUB_REG_TYPE2__SDMA4_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d
379 #define SDMA4_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
403 #define SDMA4_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
703 #define SDMA4_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d
744 #define SDMA4_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d
800 #define SDMA4_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d
928 #define SDMA4_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d
1054 #define SDMA4_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/sdma7/
H A Dsdma7_4_2_2_sh_mask.h184 #define SDMA7_PUB_REG_TYPE0__SDMA7_CHICKEN_BITS__SHIFT 0x1d
244 #define SDMA7_PUB_REG_TYPE1__SDMA7_UTCL1_WATERMK__SHIFT 0x1d
309 #define SDMA7_PUB_REG_TYPE2__SDMA7_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d
379 #define SDMA7_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
403 #define SDMA7_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
703 #define SDMA7_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d
744 #define SDMA7_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d
800 #define SDMA7_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d
928 #define SDMA7_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d
1054 #define SDMA7_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/sdma6/
H A Dsdma6_4_2_2_sh_mask.h184 #define SDMA6_PUB_REG_TYPE0__SDMA6_CHICKEN_BITS__SHIFT 0x1d
244 #define SDMA6_PUB_REG_TYPE1__SDMA6_UTCL1_WATERMK__SHIFT 0x1d
309 #define SDMA6_PUB_REG_TYPE2__SDMA6_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d
379 #define SDMA6_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
403 #define SDMA6_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
703 #define SDMA6_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d
744 #define SDMA6_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d
800 #define SDMA6_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d
928 #define SDMA6_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d
1054 #define SDMA6_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/sdma3/
H A Dsdma3_4_2_2_sh_mask.h184 #define SDMA3_PUB_REG_TYPE0__SDMA3_CHICKEN_BITS__SHIFT 0x1d
244 #define SDMA3_PUB_REG_TYPE1__SDMA3_UTCL1_WATERMK__SHIFT 0x1d
309 #define SDMA3_PUB_REG_TYPE2__SDMA3_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d
379 #define SDMA3_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
403 #define SDMA3_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
703 #define SDMA3_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d
744 #define SDMA3_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d
800 #define SDMA3_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d
928 #define SDMA3_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d
1054 #define SDMA3_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/sdma2/
H A Dsdma2_4_2_2_sh_mask.h184 #define SDMA2_PUB_REG_TYPE0__SDMA2_CHICKEN_BITS__SHIFT 0x1d
244 #define SDMA2_PUB_REG_TYPE1__SDMA2_UTCL1_WATERMK__SHIFT 0x1d
309 #define SDMA2_PUB_REG_TYPE2__SDMA2_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d
379 #define SDMA2_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
403 #define SDMA2_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
703 #define SDMA2_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d
744 #define SDMA2_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d
800 #define SDMA2_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d
928 #define SDMA2_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d
1054 #define SDMA2_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/sdma1/
H A Dsdma1_4_2_2_sh_mask.h184 #define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS__SHIFT 0x1d
244 #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WATERMK__SHIFT 0x1d
309 #define SDMA1_PUB_REG_TYPE2__SDMA1_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d
379 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
403 #define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
703 #define SDMA1_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d
744 #define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d
800 #define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d
928 #define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d
1054 #define SDMA1_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d
[all...]
H A Dsdma1_4_2_sh_mask.h185 #define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS__SHIFT 0x1d
246 #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WATERMK__SHIFT 0x1d
309 #define SDMA1_PUB_REG_TYPE2__SDMA1_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d
375 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
399 #define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
699 #define SDMA1_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d
740 #define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d
796 #define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d
924 #define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d
1049 #define SDMA1_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d
[all...]
/third_party/node/deps/openssl/config/archs/linux64-mips64/asm/crypto/aes/
H A Daes-mips.S1607 .byte 0x12,0x09,0x09,0x1b, 0x1d,0x83,0x83,0x9e
1654 .byte 0x16,0x0b,0x0b,0x1d, 0xad,0xdb,0xdb,0x76
1686 .byte 0x3a,0x1d,0x1d,0x27, 0x27,0x9e,0x9e,0xb9
1766 .byte 0x3c,0x22,0xe0,0x43, 0x12,0x1b,0x17,0x1d
1779 .byte 0x1d,0x9e,0x2f,0x4b, 0xdc,0xb2,0x30,0xf3
1815 .byte 0xb3,0x67,0x1d,0x5a, 0x92,0xdb,0xd2,0x52
1827 .byte 0x16,0x1d,0xc3,0x72, 0xbc,0xe2,0x25,0x0c
1854 .byte 0x47, 0xf1, 0x1a, 0x71, 0x1d, 0x29, 0xc5, 0x89
1895 .byte 0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d,
[all...]

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