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/third_party/vixl/test/aarch32/traces/
H A Dassembler-cond-rd-rn-operand-rm-shift-amount-1to31-sbc-a32.h296 0x07, 0x1d, 0xc9, 0x70 // sbc vc r1 r9 r7 LSL 26
1484 0x01, 0x1d, 0xc0, 0xb0 // sbc lt r1 r0 r1 LSL 26
H A Dassembler-cond-rd-rn-operand-rm-shift-amount-1to31-sbc-t32.h989 0x6e, 0xeb, 0x3b, 0x1d // sbc al r13 r14 r11 ROR 4
1064 0x6b, 0xeb, 0x71, 0x1d // sbc al r13 r11 r1 ROR 5
H A Dassembler-cond-rd-rn-operand-rm-shift-amount-1to31-sbcs-a32.h296 0x07, 0x1d, 0xd9, 0x70 // sbcs vc r1 r9 r7 LSL 26
1484 0x01, 0x1d, 0xd0, 0xb0 // sbcs lt r1 r0 r1 LSL 26
H A Dassembler-cond-rd-rn-operand-rm-shift-amount-1to31-sbcs-t32.h989 0x7e, 0xeb, 0x3b, 0x1d // sbcs al r13 r14 r11 ROR 4
1064 0x7b, 0xeb, 0x71, 0x1d // sbcs al r13 r11 r1 ROR 5
H A Dassembler-cond-rd-rn-operand-rm-shift-amount-1to31-sub-a32.h296 0x07, 0x1d, 0x49, 0x70 // sub vc r1 r9 r7 LSL 26
1484 0x01, 0x1d, 0x40, 0xb0 // sub lt r1 r0 r1 LSL 26
H A Dassembler-cond-rd-rn-operand-rm-shift-amount-1to31-sub-t32.h989 0xae, 0xeb, 0x3b, 0x1d // sub al r13 r14 r11 ROR 4
1064 0xab, 0xeb, 0x71, 0x1d // sub al r13 r11 r1 ROR 5
H A Dassembler-cond-rd-rn-operand-rm-shift-amount-1to31-subs-a32.h296 0x07, 0x1d, 0x59, 0x70 // subs vc r1 r9 r7 LSL 26
1484 0x01, 0x1d, 0x50, 0xb0 // subs lt r1 r0 r1 LSL 26
H A Dassembler-cond-rd-rn-operand-rm-shift-amount-1to31-subs-t32.h989 0xbe, 0xeb, 0x3b, 0x1d // subs al r13 r14 r11 ROR 4
1064 0xbb, 0xeb, 0x71, 0x1d // subs al r13 r11 r1 ROR 5
H A Dassembler-cond-rd-rn-operand-rm-shift-amount-1to31-adc-a32.h296 0x07, 0x1d, 0xa9, 0x70 // adc vc r1 r9 r7 LSL 26
1484 0x01, 0x1d, 0xa0, 0xb0 // adc lt r1 r0 r1 LSL 26
H A Dassembler-cond-rd-rn-operand-rm-shift-amount-1to31-adc-t32.h989 0x4e, 0xeb, 0x3b, 0x1d // adc al r13 r14 r11 ROR 4
1064 0x4b, 0xeb, 0x71, 0x1d // adc al r13 r11 r1 ROR 5
H A Dassembler-cond-rd-rn-operand-rm-shift-amount-1to31-adcs-a32.h296 0x07, 0x1d, 0xb9, 0x70 // adcs vc r1 r9 r7 LSL 26
1484 0x01, 0x1d, 0xb0, 0xb0 // adcs lt r1 r0 r1 LSL 26
H A Dassembler-cond-rd-rn-operand-rm-shift-amount-1to31-adcs-t32.h989 0x5e, 0xeb, 0x3b, 0x1d // adcs al r13 r14 r11 ROR 4
1064 0x5b, 0xeb, 0x71, 0x1d // adcs al r13 r11 r1 ROR 5
H A Dassembler-cond-rd-rn-operand-rm-shift-amount-1to31-add-a32.h296 0x07, 0x1d, 0x89, 0x70 // add vc r1 r9 r7 LSL 26
1484 0x01, 0x1d, 0x80, 0xb0 // add lt r1 r0 r1 LSL 26
H A Dassembler-cond-rd-rn-operand-rm-shift-amount-1to31-add-t32.h989 0x0e, 0xeb, 0x3b, 0x1d // add al r13 r14 r11 ROR 4
1064 0x0b, 0xeb, 0x71, 0x1d // add al r13 r11 r1 ROR 5
H A Dassembler-cond-rd-rn-operand-rm-shift-amount-1to31-adds-a32.h296 0x07, 0x1d, 0x99, 0x70 // adds vc r1 r9 r7 LSL 26
1484 0x01, 0x1d, 0x90, 0xb0 // adds lt r1 r0 r1 LSL 26
H A Dassembler-cond-rd-rn-operand-rm-shift-amount-1to31-and-a32.h296 0x07, 0x1d, 0x09, 0x70 // and_ vc r1 r9 r7 LSL 26
1484 0x01, 0x1d, 0x00, 0xb0 // and_ lt r1 r0 r1 LSL 26
H A Dassembler-cond-rd-rn-operand-rm-shift-amount-1to31-and-t32.h989 0x0e, 0xea, 0x3b, 0x1d // and_ al r13 r14 r11 ROR 4
1064 0x0b, 0xea, 0x71, 0x1d // and_ al r13 r11 r1 ROR 5
H A Dassembler-cond-rd-rn-operand-rm-shift-amount-1to31-bic-a32.h296 0x07, 0x1d, 0xc9, 0x71 // bic vc r1 r9 r7 LSL 26
1484 0x01, 0x1d, 0xc0, 0xb1 // bic lt r1 r0 r1 LSL 26
H A Dassembler-cond-rd-rn-operand-rm-shift-amount-1to31-bic-t32.h989 0x2e, 0xea, 0x3b, 0x1d // bic al r13 r14 r11 ROR 4
1064 0x2b, 0xea, 0x71, 0x1d // bic al r13 r11 r1 ROR 5
H A Dassembler-cond-rd-rn-operand-rm-shift-amount-1to31-bics-a32.h296 0x07, 0x1d, 0xd9, 0x71 // bics vc r1 r9 r7 LSL 26
1484 0x01, 0x1d, 0xd0, 0xb1 // bics lt r1 r0 r1 LSL 26
H A Dassembler-cond-rd-rn-operand-rm-shift-amount-1to31-bics-t32.h989 0x3e, 0xea, 0x3b, 0x1d // bics al r13 r14 r11 ROR 4
1064 0x3b, 0xea, 0x71, 0x1d // bics al r13 r11 r1 ROR 5
H A Dassembler-cond-rd-rn-operand-rm-shift-amount-1to31-eor-a32.h296 0x07, 0x1d, 0x29, 0x70 // eor vc r1 r9 r7 LSL 26
1484 0x01, 0x1d, 0x20, 0xb0 // eor lt r1 r0 r1 LSL 26
H A Dassembler-cond-rd-rn-operand-rm-shift-amount-1to31-eor-t32.h989 0x8e, 0xea, 0x3b, 0x1d // eor al r13 r14 r11 ROR 4
1064 0x8b, 0xea, 0x71, 0x1d // eor al r13 r11 r1 ROR 5
H A Dassembler-cond-rd-operand-rn-shift-amount-1to32-cmp-t32.h407 0xb2, 0xeb, 0x1d, 0x2f // cmp al r2 r13 LSR 8
458 0xb2, 0xeb, 0x1d, 0x0f // cmp al r2 r13 LSR 32
H A Dassembler-cond-rd-operand-rn-shift-amount-1to32-mov-a32.h1106 0x2c, 0x1d, 0xa0, 0x91 // mov ls r1 r12 LSR 26
1421 0xad, 0x1d, 0xa0, 0x71 // mov vc r1 r13 LSR 27

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