Home
last modified time | relevance | path

Searched refs:x1d (Results 451 - 475 of 2581) sorted by relevance

1...<<11121314151617181920>>...104

/third_party/vixl/test/aarch32/traces/
H A Dassembler-cond-rd-rn-operand-rm-shift-amount-1to32-adcs-t32.h182 0x5e, 0xeb, 0x1d, 0x17 // adcs al r7 r14 r13 LSR 4
305 0x56, 0xeb, 0x9c, 0x1d // adcs al r13 r6 r12 LSR 6
338 0x5b, 0xeb, 0x1d, 0x5d // adcs al r13 r11 r13 LSR 20
458 0x57, 0xeb, 0x93, 0x1d // adcs al r13 r7 r3 LSR 6
515 0x50, 0xeb, 0xd1, 0x1d // adcs al r13 r0 r1 LSR 7
518 0x53, 0xeb, 0x1d, 0x43 // adcs al r3 r3 r13 LSR 16
614 0x5d, 0xeb, 0x1d, 0x49 // adcs al r9 r13 r13 LSR 16
728 0x56, 0xeb, 0x1d, 0x6c // adcs al r12 r6 r13 LSR 24
839 0x57, 0xeb, 0x1d, 0x49 // adcs al r9 r7 r13 LSR 16
947 0x56, 0xeb, 0xac, 0x1d // adc
[all...]
H A Dassembler-cond-rd-rn-operand-rm-shift-amount-1to32-add-t32.h182 0x0e, 0xeb, 0x1d, 0x17 // add al r7 r14 r13 LSR 4
305 0x06, 0xeb, 0x9c, 0x1d // add al r13 r6 r12 LSR 6
338 0x0b, 0xeb, 0x1d, 0x5d // add al r13 r11 r13 LSR 20
458 0x07, 0xeb, 0x93, 0x1d // add al r13 r7 r3 LSR 6
515 0x00, 0xeb, 0xd1, 0x1d // add al r13 r0 r1 LSR 7
518 0x03, 0xeb, 0x1d, 0x43 // add al r3 r3 r13 LSR 16
614 0x0d, 0xeb, 0x1d, 0x49 // add al r9 r13 r13 LSR 16
728 0x06, 0xeb, 0x1d, 0x6c // add al r12 r6 r13 LSR 24
839 0x07, 0xeb, 0x1d, 0x49 // add al r9 r7 r13 LSR 16
947 0x06, 0xeb, 0xac, 0x1d // ad
[all...]
H A Dassembler-cond-rd-rn-operand-rm-shift-amount-1to32-and-t32.h182 0x0e, 0xea, 0x1d, 0x17 // and_ al r7 r14 r13 LSR 4
305 0x06, 0xea, 0x9c, 0x1d // and_ al r13 r6 r12 LSR 6
338 0x0b, 0xea, 0x1d, 0x5d // and_ al r13 r11 r13 LSR 20
458 0x07, 0xea, 0x93, 0x1d // and_ al r13 r7 r3 LSR 6
515 0x00, 0xea, 0xd1, 0x1d // and_ al r13 r0 r1 LSR 7
518 0x03, 0xea, 0x1d, 0x43 // and_ al r3 r3 r13 LSR 16
614 0x0d, 0xea, 0x1d, 0x49 // and_ al r9 r13 r13 LSR 16
728 0x06, 0xea, 0x1d, 0x6c // and_ al r12 r6 r13 LSR 24
839 0x07, 0xea, 0x1d, 0x49 // and_ al r9 r7 r13 LSR 16
947 0x06, 0xea, 0xac, 0x1d // and
[all...]
H A Dassembler-cond-rd-rn-operand-rm-shift-amount-1to32-bic-t32.h182 0x2e, 0xea, 0x1d, 0x17 // bic al r7 r14 r13 LSR 4
305 0x26, 0xea, 0x9c, 0x1d // bic al r13 r6 r12 LSR 6
338 0x2b, 0xea, 0x1d, 0x5d // bic al r13 r11 r13 LSR 20
458 0x27, 0xea, 0x93, 0x1d // bic al r13 r7 r3 LSR 6
515 0x20, 0xea, 0xd1, 0x1d // bic al r13 r0 r1 LSR 7
518 0x23, 0xea, 0x1d, 0x43 // bic al r3 r3 r13 LSR 16
614 0x2d, 0xea, 0x1d, 0x49 // bic al r9 r13 r13 LSR 16
728 0x26, 0xea, 0x1d, 0x6c // bic al r12 r6 r13 LSR 24
839 0x27, 0xea, 0x1d, 0x49 // bic al r9 r7 r13 LSR 16
947 0x26, 0xea, 0xac, 0x1d // bi
[all...]
H A Dassembler-cond-rd-rn-operand-rm-shift-amount-1to32-bics-t32.h182 0x3e, 0xea, 0x1d, 0x17 // bics al r7 r14 r13 LSR 4
305 0x36, 0xea, 0x9c, 0x1d // bics al r13 r6 r12 LSR 6
338 0x3b, 0xea, 0x1d, 0x5d // bics al r13 r11 r13 LSR 20
458 0x37, 0xea, 0x93, 0x1d // bics al r13 r7 r3 LSR 6
515 0x30, 0xea, 0xd1, 0x1d // bics al r13 r0 r1 LSR 7
518 0x33, 0xea, 0x1d, 0x43 // bics al r3 r3 r13 LSR 16
614 0x3d, 0xea, 0x1d, 0x49 // bics al r9 r13 r13 LSR 16
728 0x36, 0xea, 0x1d, 0x6c // bics al r12 r6 r13 LSR 24
839 0x37, 0xea, 0x1d, 0x49 // bics al r9 r7 r13 LSR 16
947 0x36, 0xea, 0xac, 0x1d // bic
[all...]
H A Dassembler-cond-rd-rn-operand-rm-shift-amount-1to32-eor-t32.h182 0x8e, 0xea, 0x1d, 0x17 // eor al r7 r14 r13 LSR 4
305 0x86, 0xea, 0x9c, 0x1d // eor al r13 r6 r12 LSR 6
338 0x8b, 0xea, 0x1d, 0x5d // eor al r13 r11 r13 LSR 20
458 0x87, 0xea, 0x93, 0x1d // eor al r13 r7 r3 LSR 6
515 0x80, 0xea, 0xd1, 0x1d // eor al r13 r0 r1 LSR 7
518 0x83, 0xea, 0x1d, 0x43 // eor al r3 r3 r13 LSR 16
614 0x8d, 0xea, 0x1d, 0x49 // eor al r9 r13 r13 LSR 16
728 0x86, 0xea, 0x1d, 0x6c // eor al r12 r6 r13 LSR 24
839 0x87, 0xea, 0x1d, 0x49 // eor al r9 r7 r13 LSR 16
947 0x86, 0xea, 0xac, 0x1d // eo
[all...]
H A Dassembler-cond-rd-rn-operand-rm-shift-amount-1to32-eors-t32.h182 0x9e, 0xea, 0x1d, 0x17 // eors al r7 r14 r13 LSR 4
305 0x96, 0xea, 0x9c, 0x1d // eors al r13 r6 r12 LSR 6
338 0x9b, 0xea, 0x1d, 0x5d // eors al r13 r11 r13 LSR 20
458 0x97, 0xea, 0x93, 0x1d // eors al r13 r7 r3 LSR 6
515 0x90, 0xea, 0xd1, 0x1d // eors al r13 r0 r1 LSR 7
518 0x93, 0xea, 0x1d, 0x43 // eors al r3 r3 r13 LSR 16
614 0x9d, 0xea, 0x1d, 0x49 // eors al r9 r13 r13 LSR 16
728 0x96, 0xea, 0x1d, 0x6c // eors al r12 r6 r13 LSR 24
839 0x97, 0xea, 0x1d, 0x49 // eors al r9 r7 r13 LSR 16
947 0x96, 0xea, 0xac, 0x1d // eor
[all...]
H A Dassembler-cond-rd-rn-operand-rm-shift-amount-1to32-orn-t32.h182 0x6e, 0xea, 0x1d, 0x17 // orn al r7 r14 r13 LSR 4
305 0x66, 0xea, 0x9c, 0x1d // orn al r13 r6 r12 LSR 6
338 0x6b, 0xea, 0x1d, 0x5d // orn al r13 r11 r13 LSR 20
458 0x67, 0xea, 0x93, 0x1d // orn al r13 r7 r3 LSR 6
515 0x60, 0xea, 0xd1, 0x1d // orn al r13 r0 r1 LSR 7
518 0x63, 0xea, 0x1d, 0x43 // orn al r3 r3 r13 LSR 16
614 0x6d, 0xea, 0x1d, 0x49 // orn al r9 r13 r13 LSR 16
728 0x66, 0xea, 0x1d, 0x6c // orn al r12 r6 r13 LSR 24
839 0x67, 0xea, 0x1d, 0x49 // orn al r9 r7 r13 LSR 16
947 0x66, 0xea, 0xac, 0x1d // or
[all...]
H A Dassembler-cond-rd-rn-operand-rm-shift-amount-1to32-orns-t32.h182 0x7e, 0xea, 0x1d, 0x17 // orns al r7 r14 r13 LSR 4
305 0x76, 0xea, 0x9c, 0x1d // orns al r13 r6 r12 LSR 6
338 0x7b, 0xea, 0x1d, 0x5d // orns al r13 r11 r13 LSR 20
458 0x77, 0xea, 0x93, 0x1d // orns al r13 r7 r3 LSR 6
515 0x70, 0xea, 0xd1, 0x1d // orns al r13 r0 r1 LSR 7
518 0x73, 0xea, 0x1d, 0x43 // orns al r3 r3 r13 LSR 16
614 0x7d, 0xea, 0x1d, 0x49 // orns al r9 r13 r13 LSR 16
728 0x76, 0xea, 0x1d, 0x6c // orns al r12 r6 r13 LSR 24
839 0x77, 0xea, 0x1d, 0x49 // orns al r9 r7 r13 LSR 16
947 0x76, 0xea, 0xac, 0x1d // orn
[all...]
H A Dassembler-cond-rd-rn-operand-rm-shift-amount-1to32-orr-t32.h182 0x4e, 0xea, 0x1d, 0x17 // orr al r7 r14 r13 LSR 4
305 0x46, 0xea, 0x9c, 0x1d // orr al r13 r6 r12 LSR 6
338 0x4b, 0xea, 0x1d, 0x5d // orr al r13 r11 r13 LSR 20
458 0x47, 0xea, 0x93, 0x1d // orr al r13 r7 r3 LSR 6
515 0x40, 0xea, 0xd1, 0x1d // orr al r13 r0 r1 LSR 7
518 0x43, 0xea, 0x1d, 0x43 // orr al r3 r3 r13 LSR 16
614 0x4d, 0xea, 0x1d, 0x49 // orr al r9 r13 r13 LSR 16
728 0x46, 0xea, 0x1d, 0x6c // orr al r12 r6 r13 LSR 24
839 0x47, 0xea, 0x1d, 0x49 // orr al r9 r7 r13 LSR 16
947 0x46, 0xea, 0xac, 0x1d // or
[all...]
H A Dassembler-cond-rd-rn-operand-rm-shift-amount-1to32-orrs-t32.h182 0x5e, 0xea, 0x1d, 0x17 // orrs al r7 r14 r13 LSR 4
305 0x56, 0xea, 0x9c, 0x1d // orrs al r13 r6 r12 LSR 6
338 0x5b, 0xea, 0x1d, 0x5d // orrs al r13 r11 r13 LSR 20
458 0x57, 0xea, 0x93, 0x1d // orrs al r13 r7 r3 LSR 6
515 0x50, 0xea, 0xd1, 0x1d // orrs al r13 r0 r1 LSR 7
518 0x53, 0xea, 0x1d, 0x43 // orrs al r3 r3 r13 LSR 16
614 0x5d, 0xea, 0x1d, 0x49 // orrs al r9 r13 r13 LSR 16
728 0x56, 0xea, 0x1d, 0x6c // orrs al r12 r6 r13 LSR 24
839 0x57, 0xea, 0x1d, 0x49 // orrs al r9 r7 r13 LSR 16
947 0x56, 0xea, 0xac, 0x1d // orr
[all...]
H A Dassembler-cond-rd-rn-operand-rm-shift-amount-1to32-rsb-t32.h182 0xce, 0xeb, 0x1d, 0x17 // rsb al r7 r14 r13 LSR 4
305 0xc6, 0xeb, 0x9c, 0x1d // rsb al r13 r6 r12 LSR 6
338 0xcb, 0xeb, 0x1d, 0x5d // rsb al r13 r11 r13 LSR 20
458 0xc7, 0xeb, 0x93, 0x1d // rsb al r13 r7 r3 LSR 6
515 0xc0, 0xeb, 0xd1, 0x1d // rsb al r13 r0 r1 LSR 7
518 0xc3, 0xeb, 0x1d, 0x43 // rsb al r3 r3 r13 LSR 16
614 0xcd, 0xeb, 0x1d, 0x49 // rsb al r9 r13 r13 LSR 16
728 0xc6, 0xeb, 0x1d, 0x6c // rsb al r12 r6 r13 LSR 24
839 0xc7, 0xeb, 0x1d, 0x49 // rsb al r9 r7 r13 LSR 16
947 0xc6, 0xeb, 0xac, 0x1d // rs
[all...]
H A Dassembler-cond-rd-rn-operand-rm-shift-amount-1to32-rsbs-t32.h182 0xde, 0xeb, 0x1d, 0x17 // rsbs al r7 r14 r13 LSR 4
305 0xd6, 0xeb, 0x9c, 0x1d // rsbs al r13 r6 r12 LSR 6
338 0xdb, 0xeb, 0x1d, 0x5d // rsbs al r13 r11 r13 LSR 20
458 0xd7, 0xeb, 0x93, 0x1d // rsbs al r13 r7 r3 LSR 6
515 0xd0, 0xeb, 0xd1, 0x1d // rsbs al r13 r0 r1 LSR 7
518 0xd3, 0xeb, 0x1d, 0x43 // rsbs al r3 r3 r13 LSR 16
614 0xdd, 0xeb, 0x1d, 0x49 // rsbs al r9 r13 r13 LSR 16
728 0xd6, 0xeb, 0x1d, 0x6c // rsbs al r12 r6 r13 LSR 24
839 0xd7, 0xeb, 0x1d, 0x49 // rsbs al r9 r7 r13 LSR 16
947 0xd6, 0xeb, 0xac, 0x1d // rsb
[all...]
H A Dassembler-cond-rd-rn-operand-rm-shift-amount-1to32-sbc-t32.h182 0x6e, 0xeb, 0x1d, 0x17 // sbc al r7 r14 r13 LSR 4
305 0x66, 0xeb, 0x9c, 0x1d // sbc al r13 r6 r12 LSR 6
338 0x6b, 0xeb, 0x1d, 0x5d // sbc al r13 r11 r13 LSR 20
458 0x67, 0xeb, 0x93, 0x1d // sbc al r13 r7 r3 LSR 6
515 0x60, 0xeb, 0xd1, 0x1d // sbc al r13 r0 r1 LSR 7
518 0x63, 0xeb, 0x1d, 0x43 // sbc al r3 r3 r13 LSR 16
614 0x6d, 0xeb, 0x1d, 0x49 // sbc al r9 r13 r13 LSR 16
728 0x66, 0xeb, 0x1d, 0x6c // sbc al r12 r6 r13 LSR 24
839 0x67, 0xeb, 0x1d, 0x49 // sbc al r9 r7 r13 LSR 16
947 0x66, 0xeb, 0xac, 0x1d // sb
[all...]
H A Dassembler-cond-rd-rn-operand-rm-shift-amount-1to32-sbcs-t32.h182 0x7e, 0xeb, 0x1d, 0x17 // sbcs al r7 r14 r13 LSR 4
305 0x76, 0xeb, 0x9c, 0x1d // sbcs al r13 r6 r12 LSR 6
338 0x7b, 0xeb, 0x1d, 0x5d // sbcs al r13 r11 r13 LSR 20
458 0x77, 0xeb, 0x93, 0x1d // sbcs al r13 r7 r3 LSR 6
515 0x70, 0xeb, 0xd1, 0x1d // sbcs al r13 r0 r1 LSR 7
518 0x73, 0xeb, 0x1d, 0x43 // sbcs al r3 r3 r13 LSR 16
614 0x7d, 0xeb, 0x1d, 0x49 // sbcs al r9 r13 r13 LSR 16
728 0x76, 0xeb, 0x1d, 0x6c // sbcs al r12 r6 r13 LSR 24
839 0x77, 0xeb, 0x1d, 0x49 // sbcs al r9 r7 r13 LSR 16
947 0x76, 0xeb, 0xac, 0x1d // sbc
[all...]
H A Dassembler-cond-rd-rn-operand-rm-shift-amount-1to32-sub-t32.h182 0xae, 0xeb, 0x1d, 0x17 // sub al r7 r14 r13 LSR 4
305 0xa6, 0xeb, 0x9c, 0x1d // sub al r13 r6 r12 LSR 6
338 0xab, 0xeb, 0x1d, 0x5d // sub al r13 r11 r13 LSR 20
458 0xa7, 0xeb, 0x93, 0x1d // sub al r13 r7 r3 LSR 6
515 0xa0, 0xeb, 0xd1, 0x1d // sub al r13 r0 r1 LSR 7
518 0xa3, 0xeb, 0x1d, 0x43 // sub al r3 r3 r13 LSR 16
614 0xad, 0xeb, 0x1d, 0x49 // sub al r9 r13 r13 LSR 16
728 0xa6, 0xeb, 0x1d, 0x6c // sub al r12 r6 r13 LSR 24
839 0xa7, 0xeb, 0x1d, 0x49 // sub al r9 r7 r13 LSR 16
947 0xa6, 0xeb, 0xac, 0x1d // su
[all...]
H A Dassembler-cond-rd-rn-operand-rm-shift-amount-1to32-subs-t32.h182 0xbe, 0xeb, 0x1d, 0x17 // subs al r7 r14 r13 LSR 4
305 0xb6, 0xeb, 0x9c, 0x1d // subs al r13 r6 r12 LSR 6
338 0xbb, 0xeb, 0x1d, 0x5d // subs al r13 r11 r13 LSR 20
458 0xb7, 0xeb, 0x93, 0x1d // subs al r13 r7 r3 LSR 6
515 0xb0, 0xeb, 0xd1, 0x1d // subs al r13 r0 r1 LSR 7
518 0xb3, 0xeb, 0x1d, 0x43 // subs al r3 r3 r13 LSR 16
614 0xbd, 0xeb, 0x1d, 0x49 // subs al r9 r13 r13 LSR 16
728 0xb6, 0xeb, 0x1d, 0x6c // subs al r12 r6 r13 LSR 24
839 0xb7, 0xeb, 0x1d, 0x49 // subs al r9 r7 r13 LSR 16
947 0xb6, 0xeb, 0xac, 0x1d // sub
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_0_sh_mask.h184 #define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT 0x1d
244 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK__SHIFT 0x1d
309 #define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d
383 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
407 #define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
727 #define SDMA0_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d
768 #define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d
824 #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d
952 #define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d
1091 #define SDMA0_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d
[all...]
H A Dsdma0_4_1_sh_mask.h181 #define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT 0x1d
241 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK__SHIFT 0x1d
305 #define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d
382 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
406 #define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
726 #define SDMA0_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d
767 #define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d
823 #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d
951 #define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d
1083 #define SDMA0_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/sdma1/
H A Dsdma1_4_0_sh_mask.h184 #define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS__SHIFT 0x1d
244 #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WATERMK__SHIFT 0x1d
309 #define SDMA1_PUB_REG_TYPE2__SDMA1_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d
377 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
401 #define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
685 #define SDMA1_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d
726 #define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d
782 #define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d
910 #define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d
1049 #define SDMA1_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/sdma1/
H A Dsdma1_4_0_sh_mask.h184 #define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS__SHIFT 0x1d
244 #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WATERMK__SHIFT 0x1d
309 #define SDMA1_PUB_REG_TYPE2__SDMA1_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d
377 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
401 #define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
685 #define SDMA1_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d
726 #define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d
782 #define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d
910 #define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d
1049 #define SDMA1_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_sh_mask.h181 #define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT 0x1d
241 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK__SHIFT 0x1d
305 #define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d
382 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
406 #define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
726 #define SDMA0_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d
767 #define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d
823 #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d
951 #define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d
1083 #define SDMA0_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d
[all...]
H A Dsdma0_4_0_sh_mask.h184 #define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT 0x1d
244 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK__SHIFT 0x1d
309 #define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d
383 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
407 #define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
727 #define SDMA0_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d
768 #define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d
824 #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d
952 #define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d
1091 #define SDMA0_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d
[all...]
/third_party/openssl/test/
H A Dpkcs12_format_test.c52 0x31, 0x92, 0x1d, 0x8f, 0xa0, 0xfb, 0xe5, 0x4a, 0x08, 0x31, 0x78, 0x80, 0x9c, 0x23, 0xb4, 0xe9,
55 0x01, 0xa3, 0x3b, 0x30, 0x39, 0x30, 0x1f, 0x06, 0x03, 0x55, 0x1d, 0x23, 0x04, 0x18, 0x30, 0x16,
57 0x23, 0x0d, 0x96, 0x18, 0x30, 0x47, 0x30, 0x09, 0x06, 0x03, 0x55, 0x1d, 0x13, 0x04, 0x02, 0x30,
58 0x00, 0x30, 0x0b, 0x06, 0x03, 0x55, 0x1d, 0x0f, 0x04, 0x04, 0x03, 0x02, 0x04, 0xf0, 0x30, 0x0d,
91 0x01, 0xa3, 0x3b, 0x30, 0x39, 0x30, 0x1f, 0x06, 0x03, 0x55, 0x1d, 0x23, 0x04, 0x18, 0x30, 0x16,
93 0x23, 0x0d, 0x96, 0x18, 0x30, 0x47, 0x30, 0x09, 0x06, 0x03, 0x55, 0x1d, 0x13, 0x04, 0x02, 0x30,
94 0x00, 0x30, 0x0b, 0x06, 0x03, 0x55, 0x1d, 0x0f, 0x04, 0x04, 0x03, 0x02, 0x04, 0xf0, 0x30, 0x0d,
115 0x92, 0x1d, 0x8f, 0xa0, 0xfb, 0xe5, 0x4a, 0x08, 0x31, 0x78, 0x80, 0x9c, 0x23, 0xb4, 0xe9, 0x19,
172 0xc8, 0x33, 0xbe, 0x50, 0x37, 0x60, 0x9f, 0x3b, 0xb9, 0x59, 0x55, 0x22, 0x1f, 0xa5, 0x4b, 0x1d,
185 0x9e, 0xed, 0x10, 0xd0, 0xc5, 0x73, 0x1d,
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_4_1_sh_mask.h154 #define HW_DEBUG__HW_29_DEBUG__SHIFT 0x1d
620 #define BIF_SSA_MC_LOWER__SSA_MC_FB_STALL_EN__SHIFT 0x1d
2594 #define PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d
2612 #define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE__SHIFT 0x1d
3036 #define PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
3086 #define PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
3248 #define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
3348 #define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d
3794 #define PB0_HW_DEBUG__PB0_HW_29_DEBUG__SHIFT 0x1d
3840 #define PB0_STRAP_TX_REG0__STRAP_RX_TRK_MODE_1___SHIFT 0x1d
[all...]

Completed in 221 milliseconds

1...<<11121314151617181920>>...104