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/third_party/vixl/test/aarch32/traces/
H A Dassembler-cond-rd-rn-operand-rm-shift-amount-1to32-subs-t32.h182 0xbe, 0xeb, 0x1d, 0x17 // subs al r7 r14 r13 LSR 4
305 0xb6, 0xeb, 0x9c, 0x1d // subs al r13 r6 r12 LSR 6
338 0xbb, 0xeb, 0x1d, 0x5d // subs al r13 r11 r13 LSR 20
458 0xb7, 0xeb, 0x93, 0x1d // subs al r13 r7 r3 LSR 6
515 0xb0, 0xeb, 0xd1, 0x1d // subs al r13 r0 r1 LSR 7
518 0xb3, 0xeb, 0x1d, 0x43 // subs al r3 r3 r13 LSR 16
614 0xbd, 0xeb, 0x1d, 0x49 // subs al r9 r13 r13 LSR 16
728 0xb6, 0xeb, 0x1d, 0x6c // subs al r12 r6 r13 LSR 24
839 0xb7, 0xeb, 0x1d, 0x49 // subs al r9 r7 r13 LSR 16
947 0xb6, 0xeb, 0xac, 0x1d // sub
[all...]
/kernel/linux/linux-5.10/drivers/net/ethernet/chelsio/cxgb/
H A Dvsc7326_reg.h28 #define REG_GPIO_CTRL CRA(0x7,0xf,0x1d) /* GPIO Control */
231 TxBroadcast = 0x1d, // # frames broadcast
287 #define REG_ING_FFILT_BE_EN CRA(0x2, 0, 0x1d)
/kernel/linux/linux-5.10/drivers/video/fbdev/
H A Dcg3.c286 0x1c, 0x01, 0x1d, 0x05, 0x1e, 0xff, 0x1f, 0x01,
293 0x1c, 0x01, 0x1d, 0x09, 0x1e, 0xff, 0x1f, 0x01,
300 0x1c, 0x06, 0x1d, 0x0c, 0x1e, 0xff, 0x1f, 0x01,
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/hdp/
H A Dhdp_4_0_sh_mask.h72 #define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT 0x1d
114 #define HDP_MISC_CNTL__ADAPTIVE_CACHELINE_SIZE__SHIFT 0x1d
158 #define HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE__SHIFT 0x1d
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dgt215.c170 return read_clk(clk, 0x1d, false); in gt215_clk_read()
299 ret = gt215_clk_info(&clk->base, 0x1d, kHz, info); in calc_host()
429 prog_clk(clk, 0x1d, nv_clk_src_host); in prog_host()
/kernel/linux/linux-6.6/include/dt-bindings/memory/
H A Dtegra234-mc.h49 #define TEGRA234_SID_UFS_5 0x1d
129 #define TEGRA234_SID_XUSB_VF3 0x1d
220 #define TEGRA234_MEMORY_CLIENT_NVL7R 0x1d
/kernel/linux/linux-6.6/drivers/video/fbdev/
H A Dcg3.c287 0x1c, 0x01, 0x1d, 0x05, 0x1e, 0xff, 0x1f, 0x01,
294 0x1c, 0x01, 0x1d, 0x09, 0x1e, 0xff, 0x1f, 0x01,
301 0x1c, 0x06, 0x1d, 0x0c, 0x1e, 0xff, 0x1f, 0x01,
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/hdp/
H A Dhdp_4_0_sh_mask.h72 #define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT 0x1d
115 #define HDP_MISC_CNTL__ADAPTIVE_CACHELINE_SIZE__SHIFT 0x1d
160 #define HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE__SHIFT 0x1d
/kernel/linux/linux-6.6/drivers/net/ethernet/chelsio/cxgb/
H A Dvsc7326_reg.h28 #define REG_GPIO_CTRL CRA(0x7,0xf,0x1d) /* GPIO Control */
231 TxBroadcast = 0x1d, // # frames broadcast
287 #define REG_ING_FFILT_BE_EN CRA(0x2, 0, 0x1d)
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dgt215.c170 return read_clk(clk, 0x1d, false); in gt215_clk_read()
299 ret = gt215_clk_info(&clk->base, 0x1d, kHz, info); in calc_host()
429 prog_clk(clk, 0x1d, nv_clk_src_host); in prog_host()
/kernel/linux/linux-6.6/scripts/dtc/include-prefixes/dt-bindings/memory/
H A Dtegra234-mc.h49 #define TEGRA234_SID_UFS_5 0x1d
129 #define TEGRA234_SID_XUSB_VF3 0x1d
220 #define TEGRA234_MEMORY_CLIENT_NVL7R 0x1d
/third_party/ffmpeg/libavcodec/
H A Dindeo5data.h116 {0x0b, 0x11, 0x13, 0x14, 0x15, 0x16, 0x18, 0x1a, 0x1b, 0x1d, 0x20, 0x22,
153 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23,
158 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, 0x20
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_0_sh_mask.h184 #define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT 0x1d
244 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK__SHIFT 0x1d
309 #define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d
383 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
407 #define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
727 #define SDMA0_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d
768 #define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d
824 #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d
952 #define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d
1091 #define SDMA0_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d
[all...]
H A Dsdma0_4_1_sh_mask.h181 #define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT 0x1d
241 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK__SHIFT 0x1d
305 #define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d
382 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
406 #define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
726 #define SDMA0_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d
767 #define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d
823 #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d
951 #define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d
1083 #define SDMA0_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/sdma1/
H A Dsdma1_4_0_sh_mask.h184 #define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS__SHIFT 0x1d
244 #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WATERMK__SHIFT 0x1d
309 #define SDMA1_PUB_REG_TYPE2__SDMA1_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d
377 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
401 #define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
685 #define SDMA1_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d
726 #define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d
782 #define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d
910 #define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d
1049 #define SDMA1_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/sdma1/
H A Dsdma1_4_0_sh_mask.h184 #define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS__SHIFT 0x1d
244 #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WATERMK__SHIFT 0x1d
309 #define SDMA1_PUB_REG_TYPE2__SDMA1_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d
377 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
401 #define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
685 #define SDMA1_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d
726 #define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d
782 #define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d
910 #define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d
1049 #define SDMA1_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_sh_mask.h181 #define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT 0x1d
241 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK__SHIFT 0x1d
305 #define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d
382 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
406 #define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
726 #define SDMA0_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d
767 #define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d
823 #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d
951 #define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d
1083 #define SDMA0_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d
[all...]
H A Dsdma0_4_0_sh_mask.h184 #define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT 0x1d
244 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK__SHIFT 0x1d
309 #define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d
383 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
407 #define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
727 #define SDMA0_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d
768 #define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d
824 #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d
952 #define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d
1091 #define SDMA0_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d
[all...]
/third_party/openssl/test/
H A Dpkcs12_format_test.c52 0x31, 0x92, 0x1d, 0x8f, 0xa0, 0xfb, 0xe5, 0x4a, 0x08, 0x31, 0x78, 0x80, 0x9c, 0x23, 0xb4, 0xe9,
55 0x01, 0xa3, 0x3b, 0x30, 0x39, 0x30, 0x1f, 0x06, 0x03, 0x55, 0x1d, 0x23, 0x04, 0x18, 0x30, 0x16,
57 0x23, 0x0d, 0x96, 0x18, 0x30, 0x47, 0x30, 0x09, 0x06, 0x03, 0x55, 0x1d, 0x13, 0x04, 0x02, 0x30,
58 0x00, 0x30, 0x0b, 0x06, 0x03, 0x55, 0x1d, 0x0f, 0x04, 0x04, 0x03, 0x02, 0x04, 0xf0, 0x30, 0x0d,
91 0x01, 0xa3, 0x3b, 0x30, 0x39, 0x30, 0x1f, 0x06, 0x03, 0x55, 0x1d, 0x23, 0x04, 0x18, 0x30, 0x16,
93 0x23, 0x0d, 0x96, 0x18, 0x30, 0x47, 0x30, 0x09, 0x06, 0x03, 0x55, 0x1d, 0x13, 0x04, 0x02, 0x30,
94 0x00, 0x30, 0x0b, 0x06, 0x03, 0x55, 0x1d, 0x0f, 0x04, 0x04, 0x03, 0x02, 0x04, 0xf0, 0x30, 0x0d,
115 0x92, 0x1d, 0x8f, 0xa0, 0xfb, 0xe5, 0x4a, 0x08, 0x31, 0x78, 0x80, 0x9c, 0x23, 0xb4, 0xe9, 0x19,
172 0xc8, 0x33, 0xbe, 0x50, 0x37, 0x60, 0x9f, 0x3b, 0xb9, 0x59, 0x55, 0x22, 0x1f, 0xa5, 0x4b, 0x1d,
185 0x9e, 0xed, 0x10, 0xd0, 0xc5, 0x73, 0x1d,
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_4_1_sh_mask.h154 #define HW_DEBUG__HW_29_DEBUG__SHIFT 0x1d
620 #define BIF_SSA_MC_LOWER__SSA_MC_FB_STALL_EN__SHIFT 0x1d
2594 #define PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d
2612 #define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE__SHIFT 0x1d
3036 #define PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
3086 #define PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
3248 #define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
3348 #define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d
3794 #define PB0_HW_DEBUG__PB0_HW_29_DEBUG__SHIFT 0x1d
3840 #define PB0_STRAP_TX_REG0__STRAP_RX_TRK_MODE_1___SHIFT 0x1d
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/mmhub/
H A Dmmhub_9_3_0_sh_mask.h435 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
452 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
469 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
1137 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
1154 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
1171 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
1607 #define DAGB0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
1618 #define DAGB0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
1629 #define DAGB0_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
2111 #define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/mmhub/
H A Dmmhub_9_3_0_sh_mask.h435 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
452 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
469 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
1137 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
1154 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
1171 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
1607 #define DAGB0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
1618 #define DAGB0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
1629 #define DAGB0_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
2111 #define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_4_1_sh_mask.h154 #define HW_DEBUG__HW_29_DEBUG__SHIFT 0x1d
620 #define BIF_SSA_MC_LOWER__SSA_MC_FB_STALL_EN__SHIFT 0x1d
2594 #define PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d
2612 #define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE__SHIFT 0x1d
3036 #define PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
3086 #define PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
3248 #define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
3348 #define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d
3794 #define PB0_HW_DEBUG__PB0_HW_29_DEBUG__SHIFT 0x1d
3840 #define PB0_STRAP_TX_REG0__STRAP_RX_TRK_MODE_1___SHIFT 0x1d
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_8_1_sh_mask.h188 #define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR1__SHIFT 0x1d
460 #define MC_ARB_MISC2__ARB_DEBUG29__SHIFT 0x1d
762 #define MC_ARB_AGE_RD__DIVIDE_GROUP5__SHIFT 0x1d
810 #define MC_ARB_AGE_WR__DIVIDE_GROUP5__SHIFT 0x1d
1056 #define MC_ARB_GRUB_REALTIME_RD__SAMMSP__SHIFT 0x1d
1128 #define MC_ARB_GRUB_REALTIME_WR__VP8__SHIFT 0x1d
1200 #define MC_ARB_BUSY_STATUS__REM_RD1__SHIFT 0x1d
1290 #define MC_CITF_XTRA_ENABLE__TC2_REPAIR_ENABLE__SHIFT 0x1d
2116 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_WRITE__SHIFT 0x1d
4956 #define MC_XPB_INTF_CFG__XSP_SNOOP_VAL__SHIFT 0x1d
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_8_1_sh_mask.h188 #define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR1__SHIFT 0x1d
460 #define MC_ARB_MISC2__ARB_DEBUG29__SHIFT 0x1d
762 #define MC_ARB_AGE_RD__DIVIDE_GROUP5__SHIFT 0x1d
810 #define MC_ARB_AGE_WR__DIVIDE_GROUP5__SHIFT 0x1d
1056 #define MC_ARB_GRUB_REALTIME_RD__SAMMSP__SHIFT 0x1d
1128 #define MC_ARB_GRUB_REALTIME_WR__VP8__SHIFT 0x1d
1200 #define MC_ARB_BUSY_STATUS__REM_RD1__SHIFT 0x1d
1290 #define MC_CITF_XTRA_ENABLE__TC2_REPAIR_ENABLE__SHIFT 0x1d
2116 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_WRITE__SHIFT 0x1d
4956 #define MC_XPB_INTF_CFG__XSP_SNOOP_VAL__SHIFT 0x1d
[all...]

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