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/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
H A Drv770_smc.c199 0x0C, 0x14, 0x0C, 0x14,
200 0x0C, 0x14, 0x0C, 0x14,
201 0x0C, 0x14, 0x0C, 0x14,
202 0x0C, 0x14, 0x0C, 0x14,
203 0x0C, 0x14, 0x0C, 0x14,
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/radeon/
H A Drv770_smc.c190 0x0C, 0x14, 0x0C, 0x14,
191 0x0C, 0x14, 0x0C, 0x14,
192 0x0C, 0x14, 0x0C, 0x14,
193 0x0C, 0x14, 0x0C, 0x14,
194 0x0C, 0x14, 0x0C, 0x14,
[all...]
/third_party/node/deps/openssl/config/archs/aix64-gcc-as/asm/crypto/
H A Dppccpuid.s10 .byte 0,12,0x14,0,0,0,0,0
19 .byte 0,12,0x14,0,0,0,0,0
28 .byte 0,12,0x14,0,0,0,0,0
38 .byte 0,12,0x14,0,0,0,0,0
49 .byte 0,12,0x14,0,0,0,0,0
81 .byte 0,12,0x14,0,0,0,0,0
94 .byte 0,12,0x14,0,0,0,2,0
104 .byte 0,12,0x14,0,0,0,0,0
113 .byte 0,12,0x14,0,0,0,0,0
145 .byte 0,12,0x14,
[all...]
/third_party/node/deps/openssl/config/archs/aix64-gcc-as/asm_avx2/crypto/
H A Dppccpuid.s10 .byte 0,12,0x14,0,0,0,0,0
19 .byte 0,12,0x14,0,0,0,0,0
28 .byte 0,12,0x14,0,0,0,0,0
38 .byte 0,12,0x14,0,0,0,0,0
49 .byte 0,12,0x14,0,0,0,0,0
81 .byte 0,12,0x14,0,0,0,0,0
94 .byte 0,12,0x14,0,0,0,2,0
104 .byte 0,12,0x14,0,0,0,0,0
113 .byte 0,12,0x14,0,0,0,0,0
145 .byte 0,12,0x14,
[all...]
/third_party/node/deps/openssl/config/archs/linux-ppc64le/asm_avx2/crypto/
H A Dppccpuid.s14 .byte 0,12,0x14,0,0,0,0,0
26 .byte 0,12,0x14,0,0,0,0,0
38 .byte 0,12,0x14,0,0,0,0,0
51 .byte 0,12,0x14,0,0,0,0,0
65 .byte 0,12,0x14,0,0,0,0,0
100 .byte 0,12,0x14,0,0,0,0,0
116 .byte 0,12,0x14,0,0,0,2,0
129 .byte 0,12,0x14,0,0,0,0,0
141 .byte 0,12,0x14,0,0,0,0,0
176 .byte 0,12,0x14,
[all...]
/third_party/node/deps/openssl/config/archs/linux-ppc64le/asm/crypto/
H A Dppccpuid.s14 .byte 0,12,0x14,0,0,0,0,0
26 .byte 0,12,0x14,0,0,0,0,0
38 .byte 0,12,0x14,0,0,0,0,0
51 .byte 0,12,0x14,0,0,0,0,0
65 .byte 0,12,0x14,0,0,0,0,0
100 .byte 0,12,0x14,0,0,0,0,0
116 .byte 0,12,0x14,0,0,0,2,0
129 .byte 0,12,0x14,0,0,0,0,0
141 .byte 0,12,0x14,0,0,0,0,0
176 .byte 0,12,0x14,
[all...]
/third_party/backends/backend/
H A Dniash_xfer.c203 parusb_write_reg (iHandle, SPP_CONTROL, 0x14); in NiashWriteReg()
205 parusb_write_reg (iHandle, SPP_CONTROL, 0x14); in NiashWriteReg()
207 parusb_write_reg (iHandle, SPP_CONTROL, 0x14); in NiashWriteReg()
219 parusb_write_reg (iHandle, SPP_CONTROL, 0x14); in NiashReadReg()
223 parusb_write_reg (iHandle, SPP_CONTROL, 0x14); in NiashReadReg()
241 parusb_write_reg (iHandle, SPP_CONTROL, 0x14); in NiashWriteBulk()
243 parusb_write_reg (iHandle, SPP_CONTROL, 0x14); in NiashWriteBulk()
273 parusb_write_reg (iHandle, SPP_CONTROL, 0x14); in NiashReadBulk()
275 parusb_write_reg (iHandle, SPP_CONTROL, 0x14); in NiashReadBulk()
307 parusb_write_reg (iHandle, SPP_CONTROL, 0x14); in NiashWakeup()
[all...]
/third_party/mesa3d/src/nouveau/codegen/
H A Dnv50_ir_emit_gm107.cpp555 emitField(0x14, 24, pos - (codeSize + 8)); in emitBRA()
557 emitField(0x14, 32, pos); in emitBRA()
577 emitField(0x14, 24, insn->target.bb->binPos - (codeSize + 8)); in emitCAL()
584 emitField(0x14, 32, insn->target.bb->binPos); in emitCAL()
601 emitField(0x14, 24, insn->target.bb->binPos - (codeSize + 8)); in emitPCNT()
623 emitField(0x14, 24, insn->target.bb->binPos - (codeSize + 8)); in emitPBK()
645 emitField(0x14, 24, insn->target.bb->binPos - (codeSize + 8)); in emitPRET()
667 emitField(0x14, 24, insn->target.bb->binPos - (codeSize + 8)); in emitSSY()
738 emitGPR (0x14, insn->src(0)); in emitMOV()
742 emitCBUF(0x22, -1, 0x14, 1 in emitMOV()
[all...]
/third_party/ffmpeg/libavcodec/
H A Dmpeg12data.c73 { 0x16, 14 }, { 0x15, 14 }, { 0x14, 14 }, { 0x13, 14 },
75 { 0x17, 15 }, { 0x16, 15 }, { 0x15, 15 }, { 0x14, 15 },
82 { 0xb, 10 }, { 0x14, 12 }, { 0x14, 13 }, { 0x7, 5 },
85 { 0x12, 13 }, { 0x5, 6 }, { 0x1e, 12 }, { 0x14, 16 },
106 {0x16,14}, {0x15,14}, {0x14,14}, {0x13,14},
108 {0x17,15}, {0x16,15}, {0x15,15}, {0x14,15},
115 {0xfc, 8}, {0x0c,10}, {0x14,13}, {0x07, 5},
118 {0x12,13}, {0x06, 7}, {0x1e,12}, {0x14,16},
201 {0x14, 1
[all...]
H A Dulti_cb.h74 0x00, 0x07, 0x0D, 0x14,
75 0x00, 0x0A, 0x0F, 0x14,
76 0x00, 0x05, 0x0F, 0x14,
77 0x00, 0x05, 0x0A, 0x14,
78 0x00, 0x14, 0x14, 0x14,
79 0x00, 0x00, 0x14, 0x14,
80 0x00, 0x00, 0x00, 0x14,
[all...]
H A Dh263data.c102 { 0x6, 3 }, { 0x14, 6 }, { 0x1e, 8 }, { 0xf, 10 },
109 { 0x16, 7 }, { 0x55, 12 }, { 0x15, 7 }, { 0x14, 7 },
118 { 0x14, 8 }, { 0x13, 8 }, { 0x18, 9 }, { 0x17, 9 },
119 { 0x16, 9 }, { 0x15, 9 }, { 0x14, 9 }, { 0x13, 9 },
174 { 0x53, 12 }, { 0xf, 4 }, { 0x14, 6 }, { 0x14, 7 },
186 { 0xe, 6 }, { 0x14, 9 }, { 0x24, 11 }, { 0xd, 6 },
189 { 0x14, 8 }, { 0x5b, 12 }, { 0x15, 8 }, { 0x1a, 8 },
/kernel/linux/linux-6.6/drivers/net/ethernet/realtek/
H A Dr8169_phy_config.c48 __phy_modify(phydev, 0x14, mask, val); in r8168g_phy_param()
89 phy_modify_paged(phydev, 0xa42, 0x14, 0x0000, 0x0080); in rtl8168h_config_eee_phy()
97 phy_modify_paged(phydev, 0xa6d, 0x14, 0x0010, 0x0000); in rtl8125a_config_eee_phy()
103 phy_modify_paged(phydev, 0xa6d, 0x14, 0x0010, 0x0000); in rtl8125b_config_eee_phy()
104 phy_modify_paged(phydev, 0xa42, 0x14, 0x0080, 0x0000); in rtl8125b_config_eee_phy()
216 { 0x14, 0xfb54 }, in rtl8169scd_hw_phy_config()
307 phy_set_bits(phydev, 0x14, BIT(5)); in rtl8168cp_2_hw_phy_config()
337 phy_set_bits(phydev, 0x14, BIT(5)); in rtl8168c_1_hw_phy_config()
365 phy_set_bits(phydev, 0x14, BIT(5)); in rtl8168c_2_hw_phy_config()
387 phy_set_bits(phydev, 0x14, BI in rtl8168c_3_hw_phy_config()
[all...]
/third_party/ffmpeg/libavcodec/aarch64/
H A Dmdct_neon.S34 lsl x12, x12, x14 // n = 1 << nbits
35 lsr x14, x12, #2 // n4 = n >> 2
47 subs x14, x14, #2
78 lsl x12, x12, x14 // n = 1 << nbits
79 lsr x14, x12, #3 // n8 = n >> 3
81 add x4, x4, x14, lsl #3
82 add x6, x20, x14, lsl #3
94 subs x14, x14, #
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/hdp/
H A Dhdp_4_0_sh_mask.h217 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x14
229 #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x14
343 #define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x14
352 #define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x14
361 #define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x14
370 #define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x14
379 #define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x14
388 #define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x14
397 #define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT 0x14
452 #define HDP_XDP_P2P_BAR0__VALID__SHIFT 0x14
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/hdp/
H A Dhdp_4_0_sh_mask.h219 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x14
231 #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x14
345 #define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x14
354 #define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x14
363 #define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x14
372 #define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x14
381 #define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x14
390 #define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x14
399 #define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT 0x14
454 #define HDP_XDP_P2P_BAR0__VALID__SHIFT 0x14
[all...]
H A Dhdp_5_2_1_sh_mask.h124 #define HDP_MISC_CNTL__ATOMIC_NACK_ENABLE__SHIFT 0x14
155 #define HDP_MEM_POWER_CTRL__RC_MEM_IDLE_HYSTERESIS__SHIFT 0x14
251 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x14
263 #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x14
377 #define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x14
386 #define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x14
395 #define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x14
404 #define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x14
413 #define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x14
422 #define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x14
[all...]
H A Dhdp_4_4_2_sh_mask.h126 #define HDP_MISC_CNTL__SRAM_ECC_ENABLE__SHIFT 0x14
161 #define HDP_MEM_POWER_CTRL__RC_MEM_IDLE_HYSTERESIS__SHIFT 0x14
268 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x14
280 #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x14
394 #define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x14
403 #define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x14
412 #define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x14
421 #define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x14
430 #define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x14
439 #define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x14
[all...]
H A Dhdp_6_0_0_sh_mask.h105 #define HDP_MISC_CNTL__ATOMIC_NACK_ENABLE__SHIFT 0x14
133 #define HDP_MEM_POWER_CTRL__RC_MEM_IDLE_HYSTERESIS__SHIFT 0x14
229 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x14
241 #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x14
355 #define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x14
364 #define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x14
373 #define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x14
382 #define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x14
391 #define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x14
400 #define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x14
[all...]
/kernel/linux/linux-5.10/arch/x86/kernel/
H A Dsignal_compat.c74 BUILD_BUG_ON(offsetof(siginfo_t, si_uid) != 0x14); in signal_compat_build_tests()
83 BUILD_BUG_ON(offsetof(siginfo_t, si_overrun) != 0x14); in signal_compat_build_tests()
87 BUILD_BUG_ON(offsetof(compat_siginfo_t, si_value) != 0x14); in signal_compat_build_tests()
94 BUILD_BUG_ON(offsetof(siginfo_t, si_uid) != 0x14); in signal_compat_build_tests()
98 BUILD_BUG_ON(offsetof(compat_siginfo_t, si_value) != 0x14); in signal_compat_build_tests()
105 BUILD_BUG_ON(offsetof(siginfo_t, si_uid) != 0x14); in signal_compat_build_tests()
111 BUILD_BUG_ON(offsetof(compat_siginfo_t, si_status) != 0x14); in signal_compat_build_tests()
135 BUILD_BUG_ON(offsetof(compat_siginfo_t, si_lower) != 0x14); in signal_compat_build_tests()
139 BUILD_BUG_ON(offsetof(compat_siginfo_t, si_pkey) != 0x14); in signal_compat_build_tests()
159 BUILD_BUG_ON(offsetof(compat_siginfo_t, si_arch) != 0x14); in signal_compat_build_tests()
[all...]
/kernel/linux/linux-6.6/arch/arm/mach-omap1/
H A Dhardware.h125 #define OMAP_IH1_SIR_FIQ (OMAP_IH1_BASE + 0x14)
133 #define OMAP_IH2_SIR_FIQ (OMAP_IH2_BASE + 0x14)
141 #define OMAP_IH2_0_SIR_FIQ (OMAP_IH2_0_BASE + 0x14)
149 #define OMAP_IH2_1_SIR_FIQ (OMAP_IH2_1_BASE + 0x14)
157 #define OMAP_IH2_2_SIR_FIQ (OMAP_IH2_2_BASE + 0x14)
165 #define OMAP_IH2_3_SIR_FIQ (OMAP_IH2_3_BASE + 0x14)
173 #define IRQ_SIR_FIQ_REG_OFFSET 0x14
205 #define MPUI_DSP_STATUS (MPUI_BASE + 0x14)
/kernel/linux/linux-5.10/include/linux/regulator/
H A Dpca9450.h70 PCA9450_REG_BUCK2OUT_DVS0 = 0x14,
155 #define BUCK1OUT_DVS0_DEFAULT 0x14
159 #define BUCK1OUT_DVS1_DEFAULT 0x14
163 #define BUCK2OUT_DVS0_DEFAULT 0x14
167 #define BUCK2OUT_DVS1_DEFAULT 0x14
171 #define BUCK3OUT_DVS0_DEFAULT 0x14
175 #define BUCK3OUT_DVS1_DEFAULT 0x14
187 #define BUCK6OUT_DEFAULT 0x14
/kernel/linux/linux-6.6/include/linux/regulator/
H A Dpca9450.h70 PCA9450_REG_BUCK2OUT_DVS0 = 0x14,
155 #define BUCK1OUT_DVS0_DEFAULT 0x14
159 #define BUCK1OUT_DVS1_DEFAULT 0x14
163 #define BUCK2OUT_DVS0_DEFAULT 0x14
167 #define BUCK2OUT_DVS1_DEFAULT 0x14
171 #define BUCK3OUT_DVS0_DEFAULT 0x14
175 #define BUCK3OUT_DVS1_DEFAULT 0x14
187 #define BUCK6OUT_DEFAULT 0x14
/kernel/linux/linux-5.10/drivers/hid/
H A Dhid-waltop.c62 0x14, /* Logical Minimum (0), */
71 0x14, /* Logical Minimum (0), */
113 0x14, /* Logical Minimum (0), */
122 0x14, /* Logical Minimum (0), */
164 0x14, /* Logical Minimum (0), */
173 0x14, /* Logical Minimum (0), */
217 0x14, /* Logical Minimum (0), */
226 0x14, /* Logical Minimum (0), */
237 0x46, 0x82, 0x14, /* Physical Maximum (5250), */
269 0x14, /* Logica
[all...]
/kernel/linux/linux-6.6/drivers/hid/
H A Dhid-waltop.c62 0x14, /* Logical Minimum (0), */
71 0x14, /* Logical Minimum (0), */
113 0x14, /* Logical Minimum (0), */
122 0x14, /* Logical Minimum (0), */
164 0x14, /* Logical Minimum (0), */
173 0x14, /* Logical Minimum (0), */
217 0x14, /* Logical Minimum (0), */
226 0x14, /* Logical Minimum (0), */
237 0x46, 0x82, 0x14, /* Physical Maximum (5250), */
269 0x14, /* Logica
[all...]
/kernel/linux/linux-5.10/drivers/clk/bcm/
H A Dclk-ns2.c74 .mdiv = REG_VAL(0x14, 0, 8),
80 .mdiv = REG_VAL(0x14, 8, 8),
86 .mdiv = REG_VAL(0x14, 16, 8),
92 .mdiv = REG_VAL(0x14, 24, 8),
136 .mdiv = REG_VAL(0x14, 0, 8),
142 .mdiv = REG_VAL(0x14, 8, 8),
148 .mdiv = REG_VAL(0x14, 16, 8),
154 .mdiv = REG_VAL(0x14, 24, 8),
186 .mdiv = REG_VAL(0x14, 0, 8),
192 .mdiv = REG_VAL(0x14,
[all...]

Completed in 23 milliseconds

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