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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_3_1_sh_mask.h147 #define UVD_CGC_GATE__UDEC_RE_MASK 0x1000
187 #define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x1000
229 #define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x1000
291 #define UVD_CGC_UDEC_STATUS__MP_SCLK_MASK 0x1000
353 #define UVD_LMI_CTRL__MASK_MC_URGENT_MASK 0x1000
401 #define UVD_LMI_STATUS__ADP_MC_READ_CLEAN_MASK 0x1000
589 #define UVD_SOFT_RESET__IDCT_SOFT_RESET_MASK 0x1000
703 #define UVD_CGC_MEM_CTRL__MIF_LS_EN_MASK 0x1000
727 #define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE_MASK 0x1000
/kernel/linux/linux-5.10/drivers/net/ethernet/qlogic/
H A Dqla3xxx.h225 ISP_CONTROL_LINK_DN_1 = 0x1000,
250 ISP_SERIAL_PORT_IF_SCE = 0x1000,
320 EXT_HW_CONFIG_DCS_18MA = 0x1000,
360 PORT_CONTROL_FI = 0x1000,
376 PORT_STATUS_REV_ID_1 = 0x1000,
705 PETBI_CTRL_AUTO_NEG = 0x1000,
727 PHY_GIG_ENABLE_MAN = 0x1000, /* Enable Master/Slave Manual Config*/
758 PHY_CTRL_AUTO_NEG = 0x1000,
827 #define PORT_CONFIG_HALF_DUPLEX_ENABLED 0x1000
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/
H A Dnouveau_reg.h612 #define NV50_PCONNECTOR__ESIZE 0x1000
679 #define NV50_PBUS__ESIZE 0x1000
688 #define NV50_PFB__ESIZE 0x1000
692 #define NV50_PEXTDEV__ESIZE 0x1000
853 #define NV50_PDISPLAY_USER(i) ((i) * 0x1000 + 0x00640000)
854 #define NV50_PDISPLAY_USER_PUT(i) ((i) * 0x1000 + 0x00640000)
855 #define NV50_PDISPLAY_USER_GET(i) ((i) * 0x1000 + 0x00640004)
858 #define NV50_PDISPLAY_CURSOR_USER_POS_CTRL(i) ((i) * 0x1000 + 0x00647080)
859 #define NV50_PDISPLAY_CURSOR_USER_POS(i) ((i) * 0x1000 + 0x00647084)
/kernel/linux/linux-6.6/drivers/net/ethernet/qlogic/
H A Dqla3xxx.h225 ISP_CONTROL_LINK_DN_1 = 0x1000,
250 ISP_SERIAL_PORT_IF_SCE = 0x1000,
320 EXT_HW_CONFIG_DCS_18MA = 0x1000,
360 PORT_CONTROL_FI = 0x1000,
376 PORT_STATUS_REV_ID_1 = 0x1000,
705 PETBI_CTRL_AUTO_NEG = 0x1000,
727 PHY_GIG_ENABLE_MAN = 0x1000, /* Enable Master/Slave Manual Config*/
758 PHY_CTRL_AUTO_NEG = 0x1000,
827 #define PORT_CONFIG_HALF_DUPLEX_ENABLED 0x1000
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/
H A Dnouveau_reg.h612 #define NV50_PCONNECTOR__ESIZE 0x1000
679 #define NV50_PBUS__ESIZE 0x1000
688 #define NV50_PFB__ESIZE 0x1000
692 #define NV50_PEXTDEV__ESIZE 0x1000
853 #define NV50_PDISPLAY_USER(i) ((i) * 0x1000 + 0x00640000)
854 #define NV50_PDISPLAY_USER_PUT(i) ((i) * 0x1000 + 0x00640000)
855 #define NV50_PDISPLAY_USER_GET(i) ((i) * 0x1000 + 0x00640004)
858 #define NV50_PDISPLAY_CURSOR_USER_POS_CTRL(i) ((i) * 0x1000 + 0x00647080)
859 #define NV50_PDISPLAY_CURSOR_USER_POS(i) ((i) * 0x1000 + 0x00647084)
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_3_1_sh_mask.h147 #define UVD_CGC_GATE__UDEC_RE_MASK 0x1000
187 #define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x1000
229 #define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x1000
291 #define UVD_CGC_UDEC_STATUS__MP_SCLK_MASK 0x1000
353 #define UVD_LMI_CTRL__MASK_MC_URGENT_MASK 0x1000
401 #define UVD_LMI_STATUS__ADP_MC_READ_CLEAN_MASK 0x1000
589 #define UVD_SOFT_RESET__IDCT_SOFT_RESET_MASK 0x1000
703 #define UVD_CGC_MEM_CTRL__MIF_LS_EN_MASK 0x1000
727 #define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE_MASK 0x1000
H A Duvd_4_2_sh_mask.h147 #define UVD_CGC_GATE__UDEC_RE_MASK 0x1000
187 #define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x1000
229 #define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x1000
291 #define UVD_CGC_UDEC_STATUS__MP_SCLK_MASK 0x1000
357 #define UVD_LMI_CTRL__MASK_MC_URGENT_MASK 0x1000
405 #define UVD_LMI_STATUS__ADP_MC_READ_CLEAN_MASK 0x1000
595 #define UVD_SOFT_RESET__IDCT_SOFT_RESET_MASK 0x1000
709 #define UVD_CGC_MEM_CTRL__MIF_LS_EN_MASK 0x1000
733 #define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE_MASK 0x1000
/kernel/linux/linux-5.10/arch/xtensa/lib/
H A Dpci-auto.c159 pciauto_upper_iospc &= ~(0x1000 - 1); in pciauto_prescan_setup_bridge()
200 pciauto_upper_iospc &= ~(0x1000 - 1); in pciauto_postscan_setup_bridge()
202 pciauto_upper_iospc -= 0x1000; in pciauto_postscan_setup_bridge()
/kernel/linux/linux-5.10/arch/powerpc/include/asm/
H A Dcell-regs.h124 u8 pad_0x0cb0_0x1000 [0x1000 - 0x0cb0]; /* 0x0cb0 */
214 u8 pad_0x0530_0x1000[0x1000 - 0x0530]; /* 0x0530 */
301 u8 pad_0x0240_0x1000[0x1000 - 0x0240]; /* 0x0240 */
/kernel/linux/linux-5.10/arch/powerpc/platforms/83xx/
H A Dusb.c31 immap = ioremap(get_immrbase(), 0x1000); in mpc834x_usb_cfg()
118 immap = ioremap(get_immrbase(), 0x1000); in mpc831x_usb_cfg()
233 immap = ioremap(get_immrbase(), 0x1000); in mpc837x_usb_cfg()
/kernel/linux/linux-6.6/arch/powerpc/include/asm/
H A Dcell-regs.h124 u8 pad_0x0cb0_0x1000 [0x1000 - 0x0cb0]; /* 0x0cb0 */
214 u8 pad_0x0530_0x1000[0x1000 - 0x0530]; /* 0x0530 */
301 u8 pad_0x0240_0x1000[0x1000 - 0x0240]; /* 0x0240 */
/kernel/linux/linux-6.6/arch/powerpc/kernel/
H A Dudbg_16550.c307 udbg_uart_early_addr = early_ioremap(CONFIG_PPC_EARLY_DEBUG_16550_PHYSADDR, 0x1000); in udbg_init_debug_16550()
318 addr = ioremap(CONFIG_PPC_EARLY_DEBUG_16550_PHYSADDR, 0x1000); in udbg_init_debug_16550_ioremap()
323 early_iounmap(udbg_uart_early_addr, 0x1000); in udbg_init_debug_16550_ioremap()
/kernel/linux/linux-5.10/drivers/tty/serial/
H A Dicom.h112 #define ICOM_IRAM_OFFSET 0x1000
135 #define INT_RCV_COMPLETED 0x1000
168 #define XMIT_BUFF_SZ 0x1000
/kernel/linux/linux-5.10/include/net/
H A Dieee80211_radiotap.h232 IEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE3_KNOWN = 0x1000,
253 IEEE80211_RADIOTAP_HE_DATA3_DATA_DCM = 0x1000,
319 IEEE80211_RADIOTAP_HE_MU_FLAGS1_CH1_CTR_26T_RU_KNOWN = 0x1000,
/kernel/linux/linux-5.10/sound/soc/intel/skylake/
H A Dskl-sst-dsp.h60 #define SKL_ADSP_W0_STAT_SZ 0x1000
62 #define SKL_ADSP_W0_UP_SZ 0x1000
64 #define SKL_ADSP_W1_SZ 0x1000
/kernel/linux/linux-6.6/arch/xtensa/lib/
H A Dpci-auto.c159 pciauto_upper_iospc &= ~(0x1000 - 1); in pciauto_prescan_setup_bridge()
200 pciauto_upper_iospc &= ~(0x1000 - 1); in pciauto_postscan_setup_bridge()
202 pciauto_upper_iospc -= 0x1000; in pciauto_postscan_setup_bridge()
/kernel/linux/linux-6.6/sound/soc/intel/skylake/
H A Dskl-sst-dsp.h60 #define SKL_ADSP_W0_STAT_SZ 0x1000
62 #define SKL_ADSP_W0_UP_SZ 0x1000
64 #define SKL_ADSP_W1_SZ 0x1000
/foundation/ability/ability_runtime/test/unittest/app_spawn_client_test/
H A Dapp_spawn_client_test.cpp235 startMsg.flags = 0x1000; in HWTEST_F()
283 startMsg.flags = 0x1000; in HWTEST_F()
331 startMsg.flags = 0x1000; in HWTEST_F()
379 startMsg.flags = 0x1000; in HWTEST_F()
434 startMsg.flags = 0x1000; in HWTEST_F()
483 startMsg.flags = 0x1000; in HWTEST_F()
533 startMsg.flags = 0x1000; in HWTEST_F()
583 startMsg.flags = 0x1000; in HWTEST_F()
633 startMsg.flags = 0x1000; in HWTEST_F()
679 startMsg.flags = 0x1000; in HWTEST_F()
[all...]
/kernel/linux/linux-5.10/drivers/mtd/chips/
H A Djedec_probe.c1532 ERASEINFO(0x1000,256),
1533 ERASEINFO(0x1000,256)
1545 ERASEINFO(0x1000,256),
1546 ERASEINFO(0x1000,256)
1559 ERASEINFO(0x1000,256),
1560 ERASEINFO(0x1000,256)
1573 ERASEINFO(0x1000,256),
1574 ERASEINFO(0x1000,256)
1586 ERASEINFO(0x1000,256),
1587 ERASEINFO(0x1000,25
[all...]
/kernel/linux/linux-6.6/drivers/mtd/chips/
H A Djedec_probe.c1533 ERASEINFO(0x1000,256),
1534 ERASEINFO(0x1000,256)
1546 ERASEINFO(0x1000,256),
1547 ERASEINFO(0x1000,256)
1560 ERASEINFO(0x1000,256),
1561 ERASEINFO(0x1000,256)
1574 ERASEINFO(0x1000,256),
1575 ERASEINFO(0x1000,256)
1587 ERASEINFO(0x1000,256),
1588 ERASEINFO(0x1000,25
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_8_0_sh_mask.h269 #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK 0x1000
407 #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_SCL_GATE_DISABLE_MASK 0x1000
501 #define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK 0x1000
513 #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x1000
617 #define CRTC_CONTROL__CRTC_START_POINT_CNTL_MASK 0x1000
879 #define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS_MASK 0x1000
891 #define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS_MASK 0x1000
903 #define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS_MASK 0x1000
981 #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_MASK 0x1000
1051 #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x1000
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_8_0_sh_mask.h269 #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK 0x1000
407 #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_SCL_GATE_DISABLE_MASK 0x1000
501 #define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK 0x1000
513 #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x1000
617 #define CRTC_CONTROL__CRTC_START_POINT_CNTL_MASK 0x1000
879 #define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS_MASK 0x1000
891 #define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS_MASK 0x1000
903 #define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS_MASK 0x1000
981 #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_MASK 0x1000
1051 #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x1000
[all...]
/kernel/linux/linux-5.10/arch/arm/mach-pxa/
H A Dregs-u2d.h156 #define U2DMACSR0 (0x1000) /* U2DMA Control/Status Register - Channel 0 */
157 #define U2DMACSR(x) (0x1000 + ((x) << 2)) /* U2DMA Control/Status Register - Channel x */
/kernel/linux/linux-5.10/arch/powerpc/xmon/
H A Dppc.h117 #define PPC_OPCODE_POWER4 0x1000
377 #define PPC_OPERAND_NEGATIVE (0x1000)
/kernel/linux/linux-5.10/arch/arm/mm/
H A Dpv-fixup-asm.S30 add r7, r2, #0x1000
41 add r7, r2, #0x1000

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