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/kernel/linux/linux-6.6/tools/perf/tests/
H A Dmem2node.c54 .memory_bsize = 0x100, in test__mem2node()
68 T("failed: mem2node__node", 1 == mem2node__node(&map, 0x100)); in test__mem2node()
/kernel/linux/linux-5.10/arch/arm/mach-mvebu/
H A Dpmsu.c44 #define PMSU_BASE_OFFSET 0x100
48 #define PMSU_CONTROL_AND_CONFIG(cpu) ((cpu * 0x100) + 0x104)
53 #define PMSU_CPU_POWER_DOWN_CONTROL(cpu) ((cpu * 0x100) + 0x108)
57 #define PMSU_STATUS_AND_MASK(cpu) ((cpu * 0x100) + 0x10c)
66 #define PMSU_EVENT_STATUS_AND_MASK(cpu) ((cpu * 0x100) + 0x120)
70 #define PMSU_BOOT_ADDR_REDIRECT_OFFSET(cpu) ((cpu * 0x100) + 0x124)
/kernel/linux/linux-5.10/drivers/clk/sunxi-ng/
H A Dccu-suniv-f1c100s.c247 0x100, BIT(0), 0);
249 0x100, BIT(1), 0);
251 "pll-ddr", 0x100, BIT(2), 0);
253 0x100, BIT(3), 0);
255 0x100, BIT(24), 0);
257 0x100, BIT(26), 0);
/kernel/linux/linux-6.6/arch/arm64/include/asm/
H A Dfpsimdmacros.h109 _check_num (\offset), -0x100, 0xff
121 _check_num (\offset), -0x100, 0xff
133 _check_num (\offset), -0x100, 0xff
145 _check_num (\offset), -0x100, 0xff
202 _check_num (\offset), -0x100, 0xff
216 _check_num (\offset), -0x100, 0xff
/kernel/linux/linux-6.6/arch/arm/mach-mvebu/
H A Dpmsu.c41 #define PMSU_BASE_OFFSET 0x100
45 #define PMSU_CONTROL_AND_CONFIG(cpu) ((cpu * 0x100) + 0x104)
50 #define PMSU_CPU_POWER_DOWN_CONTROL(cpu) ((cpu * 0x100) + 0x108)
54 #define PMSU_STATUS_AND_MASK(cpu) ((cpu * 0x100) + 0x10c)
63 #define PMSU_EVENT_STATUS_AND_MASK(cpu) ((cpu * 0x100) + 0x120)
67 #define PMSU_BOOT_ADDR_REDIRECT_OFFSET(cpu) ((cpu * 0x100) + 0x124)
/kernel/linux/linux-5.10/drivers/misc/habanalabs/include/gaudi/asic_reg/
H A Dmme0_qm_masks.h148 #define MME0_QM_GLBL_STS1_CP_FENCE0_OVF_ERR_MASK 0x100
178 #define MME0_QM_GLBL_STS1_4_CP_FENCE0_OVF_ERR_MASK 0x100
210 #define MME0_QM_GLBL_MSG_EN_CP_FENCE0_OVF_ERR_MASK 0x100
240 #define MME0_QM_GLBL_MSG_EN_4_CP_FENCE0_OVF_ERR_MASK 0x100
576 #define MME0_QM_ARB_CFG_0_EN_MASK 0x100
712 #define MME0_QM_CGM_STS_AGENT_IDLE_MASK 0x100
H A Ddma0_qm_masks.h148 #define DMA0_QM_GLBL_STS1_CP_FENCE0_OVF_ERR_MASK 0x100
178 #define DMA0_QM_GLBL_STS1_4_CP_FENCE0_OVF_ERR_MASK 0x100
210 #define DMA0_QM_GLBL_MSG_EN_CP_FENCE0_OVF_ERR_MASK 0x100
240 #define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE0_OVF_ERR_MASK 0x100
576 #define DMA0_QM_ARB_CFG_0_EN_MASK 0x100
712 #define DMA0_QM_CGM_STS_AGENT_IDLE_MASK 0x100
H A Dtpc0_qm_masks.h148 #define TPC0_QM_GLBL_STS1_CP_FENCE0_OVF_ERR_MASK 0x100
178 #define TPC0_QM_GLBL_STS1_4_CP_FENCE0_OVF_ERR_MASK 0x100
210 #define TPC0_QM_GLBL_MSG_EN_CP_FENCE0_OVF_ERR_MASK 0x100
240 #define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE0_OVF_ERR_MASK 0x100
576 #define TPC0_QM_ARB_CFG_0_EN_MASK 0x100
712 #define TPC0_QM_CGM_STS_AGENT_IDLE_MASK 0x100
/kernel/linux/linux-5.10/sound/soc/codecs/
H A Dwm8776.c176 master = 0x100; in wm8776_set_fmt()
257 master = 0x100; in wm8776_hw_params()
420 snd_soc_component_update_bits(component, WM8776_HPRVOL, 0x100, 0x100); in wm8776_probe()
421 snd_soc_component_update_bits(component, WM8776_DACRVOL, 0x100, 0x100); in wm8776_probe()
/kernel/linux/linux-6.6/drivers/clk/sunxi-ng/
H A Dccu-suniv-f1c100s.c255 0x100, BIT(0), 0);
257 0x100, BIT(1), 0);
259 "pll-ddr", 0x100, BIT(2), 0);
261 0x100, BIT(3), 0);
263 0x100, BIT(24), 0);
265 0x100, BIT(26), 0);
/kernel/linux/linux-6.6/drivers/accel/habanalabs/include/gaudi/asic_reg/
H A Ddma0_qm_masks.h148 #define DMA0_QM_GLBL_STS1_CP_FENCE0_OVF_ERR_MASK 0x100
178 #define DMA0_QM_GLBL_STS1_4_CP_FENCE0_OVF_ERR_MASK 0x100
210 #define DMA0_QM_GLBL_MSG_EN_CP_FENCE0_OVF_ERR_MASK 0x100
240 #define DMA0_QM_GLBL_MSG_EN_4_CP_FENCE0_OVF_ERR_MASK 0x100
576 #define DMA0_QM_ARB_CFG_0_EN_MASK 0x100
712 #define DMA0_QM_CGM_STS_AGENT_IDLE_MASK 0x100
H A Dmme0_qm_masks.h148 #define MME0_QM_GLBL_STS1_CP_FENCE0_OVF_ERR_MASK 0x100
178 #define MME0_QM_GLBL_STS1_4_CP_FENCE0_OVF_ERR_MASK 0x100
210 #define MME0_QM_GLBL_MSG_EN_CP_FENCE0_OVF_ERR_MASK 0x100
240 #define MME0_QM_GLBL_MSG_EN_4_CP_FENCE0_OVF_ERR_MASK 0x100
576 #define MME0_QM_ARB_CFG_0_EN_MASK 0x100
712 #define MME0_QM_CGM_STS_AGENT_IDLE_MASK 0x100
H A Dtpc0_qm_masks.h148 #define TPC0_QM_GLBL_STS1_CP_FENCE0_OVF_ERR_MASK 0x100
178 #define TPC0_QM_GLBL_STS1_4_CP_FENCE0_OVF_ERR_MASK 0x100
210 #define TPC0_QM_GLBL_MSG_EN_CP_FENCE0_OVF_ERR_MASK 0x100
240 #define TPC0_QM_GLBL_MSG_EN_4_CP_FENCE0_OVF_ERR_MASK 0x100
576 #define TPC0_QM_ARB_CFG_0_EN_MASK 0x100
712 #define TPC0_QM_CGM_STS_AGENT_IDLE_MASK 0x100
H A Dnic0_qm0_masks.h148 #define NIC0_QM0_GLBL_STS1_CP_FENCE0_OVF_ERR_MASK 0x100
178 #define NIC0_QM0_GLBL_STS1_4_CP_FENCE0_OVF_ERR_MASK 0x100
210 #define NIC0_QM0_GLBL_MSG_EN_CP_FENCE0_OVF_ERR_MASK 0x100
240 #define NIC0_QM0_GLBL_MSG_EN_4_CP_FENCE0_OVF_ERR_MASK 0x100
576 #define NIC0_QM0_ARB_CFG_0_EN_MASK 0x100
712 #define NIC0_QM0_CGM_STS_AGENT_IDLE_MASK 0x100
/kernel/linux/linux-6.6/sound/soc/codecs/
H A Dwm8776.c176 master = 0x100; in wm8776_set_fmt()
257 master = 0x100; in wm8776_hw_params()
420 snd_soc_component_update_bits(component, WM8776_HPRVOL, 0x100, 0x100); in wm8776_probe()
421 snd_soc_component_update_bits(component, WM8776_DACRVOL, 0x100, 0x100); in wm8776_probe()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_5_1_sh_mask.h53 #define BUS_CNTL__BIF_ERR_RTR_BKPRESSURE_EN_MASK 0x100
111 #define HW_DEBUG__HW_08_DEBUG_MASK 0x100
185 #define INTERRUPT_CNTL__GEN_IH_INT_EN_MASK 0x100
243 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK 0x100
267 #define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN3_MASK 0x100
291 #define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN3_MASK 0x100
323 #define BIF_FEATURES_CONTROL_MISC__IGNORE_BE_CHECK_GASKET_COMB_DIS_MASK 0x100
373 #define BIF_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK 0x100
413 #define GPU_HDP_FLUSH_REQ__CP8_MASK 0x100
437 #define GPU_HDP_FLUSH_DONE__CP8_MASK 0x100
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_5_1_sh_mask.h53 #define BUS_CNTL__BIF_ERR_RTR_BKPRESSURE_EN_MASK 0x100
111 #define HW_DEBUG__HW_08_DEBUG_MASK 0x100
185 #define INTERRUPT_CNTL__GEN_IH_INT_EN_MASK 0x100
243 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK 0x100
267 #define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN3_MASK 0x100
291 #define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN3_MASK 0x100
323 #define BIF_FEATURES_CONTROL_MISC__IGNORE_BE_CHECK_GASKET_COMB_DIS_MASK 0x100
373 #define BIF_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK 0x100
413 #define GPU_HDP_FLUSH_REQ__CP8_MASK 0x100
437 #define GPU_HDP_FLUSH_DONE__CP8_MASK 0x100
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_5_0_sh_mask.h151 #define UVD_CGC_GATE__MPRD_MASK 0x100
195 #define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x100
307 #define UVD_CGC_UDEC_STATUS__IT_VCLK_MASK 0x100
341 #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x100
383 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x100
429 #define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK 0x100
577 #define UVD_VCPU_CNTL__ABORT_REQ_MASK 0x100
619 #define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x100
739 #define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x100
769 #define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK_MASK 0x100
[all...]
H A Duvd_6_0_sh_mask.h153 #define UVD_CGC_GATE__MPRD_MASK 0x100
197 #define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x100
309 #define UVD_CGC_UDEC_STATUS__IT_VCLK_MASK 0x100
343 #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x100
385 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x100
431 #define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK 0x100
579 #define UVD_VCPU_CNTL__ABORT_REQ_MASK 0x100
621 #define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x100
741 #define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x100
767 #define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK_MASK 0x100
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_6_0_sh_mask.h153 #define UVD_CGC_GATE__MPRD_MASK 0x100
197 #define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x100
309 #define UVD_CGC_UDEC_STATUS__IT_VCLK_MASK 0x100
343 #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x100
385 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x100
431 #define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK 0x100
579 #define UVD_VCPU_CNTL__ABORT_REQ_MASK 0x100
621 #define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x100
741 #define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x100
767 #define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK_MASK 0x100
[all...]
H A Duvd_5_0_sh_mask.h151 #define UVD_CGC_GATE__MPRD_MASK 0x100
195 #define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x100
307 #define UVD_CGC_UDEC_STATUS__IT_VCLK_MASK 0x100
341 #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x100
383 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x100
429 #define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK 0x100
577 #define UVD_VCPU_CNTL__ABORT_REQ_MASK 0x100
619 #define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x100
739 #define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x100
769 #define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK_MASK 0x100
[all...]
/kernel/linux/linux-5.10/arch/alpha/include/asm/
H A Dcore_cia.h205 #define CIA_IOC_PCI_Wn_BASE(N) (IDENT_ADDR + 0x8760000400UL + (N)*0x100)
206 #define CIA_IOC_PCI_Wn_MASK(N) (IDENT_ADDR + 0x8760000440UL + (N)*0x100)
207 #define CIA_IOC_PCI_Tn_BASE(N) (IDENT_ADDR + 0x8760000480UL + (N)*0x100)
221 (IDENT_ADDR + 0x8760001000UL + (n)*0x100 + (m)*0x40)
/kernel/linux/linux-5.10/arch/arm64/include/asm/
H A Dfpsimdmacros.h100 _check_num (\offset), -0x100, 0xff
112 _check_num (\offset), -0x100, 0xff
124 _check_num (\offset), -0x100, 0xff
136 _check_num (\offset), -0x100, 0xff
/kernel/linux/linux-5.10/arch/sh/kernel/cpu/sh2a/
H A Dsetup-sh7206.c140 DEFINE_RES_MEM(0xfffe8000, 0x100),
160 DEFINE_RES_MEM(0xfffe8800, 0x100),
180 DEFINE_RES_MEM(0xfffe9000, 0x100),
200 DEFINE_RES_MEM(0xfffe9800, 0x100),
/kernel/linux/linux-5.10/arch/arm/mach-integrator/
H A Dhardware.h88 #define INTEGRATOR_HDR_SPDBASE_OFFSET 0x100
198 #define INTEGRATOR_SC_OSC_PCI_25MHz 0x100
200 #define INTEGRATOR_SC_OSC_PCI_MASK 0x100
335 #define INTEGRATOR_TIMER1_BASE (INTEGRATOR_CT_BASE + 0x100)

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