/third_party/vixl/test/aarch32/traces/ |
H A D | assembler-cond-rd-rn-operand-rm-shift-amount-1to32-orn-t32.h | 452 0x64, 0xea, 0xa5, 0x0d // orn al r13 r4 r5 ASR 2 809 0x6d, 0xea, 0xa5, 0x0d // orn al r13 r13 r5 ASR 2 860 0x68, 0xea, 0x2e, 0x0d // orn al r13 r8 r14 ASR 32
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H A D | assembler-cond-rd-rn-operand-rm-shift-amount-1to32-orns-t32.h | 452 0x74, 0xea, 0xa5, 0x0d // orns al r13 r4 r5 ASR 2 809 0x7d, 0xea, 0xa5, 0x0d // orns al r13 r13 r5 ASR 2 860 0x78, 0xea, 0x2e, 0x0d // orns al r13 r8 r14 ASR 32
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H A D | assembler-cond-rd-rn-operand-rm-shift-amount-1to32-orr-a32.h | 890 0xa8, 0x0d, 0x80, 0x81 // orr hi r0 r0 r8 LSR 27 1256 0xa1, 0x0d, 0x81, 0x21 // orr cs r0 r1 r1 LSR 27 1490 0x2e, 0x0d, 0x80, 0x21 // orr cs r0 r0 r14 LSR 26
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H A D | assembler-cond-rd-rn-operand-rm-shift-amount-1to32-orr-t32.h | 452 0x44, 0xea, 0xa5, 0x0d // orr al r13 r4 r5 ASR 2 809 0x4d, 0xea, 0xa5, 0x0d // orr al r13 r13 r5 ASR 2 860 0x48, 0xea, 0x2e, 0x0d // orr al r13 r8 r14 ASR 32
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H A D | assembler-cond-rd-rn-operand-rm-shift-amount-1to32-orrs-a32.h | 890 0xa8, 0x0d, 0x90, 0x81 // orrs hi r0 r0 r8 LSR 27 1256 0xa1, 0x0d, 0x91, 0x21 // orrs cs r0 r1 r1 LSR 27 1490 0x2e, 0x0d, 0x90, 0x21 // orrs cs r0 r0 r14 LSR 26
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H A D | assembler-cond-rd-rn-operand-rm-shift-amount-1to32-orrs-t32.h | 452 0x54, 0xea, 0xa5, 0x0d // orrs al r13 r4 r5 ASR 2 809 0x5d, 0xea, 0xa5, 0x0d // orrs al r13 r13 r5 ASR 2 860 0x58, 0xea, 0x2e, 0x0d // orrs al r13 r8 r14 ASR 32
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H A D | assembler-cond-rd-rn-operand-rm-shift-amount-1to32-rsb-a32.h | 890 0xa8, 0x0d, 0x60, 0x80 // rsb hi r0 r0 r8 LSR 27 1256 0xa1, 0x0d, 0x61, 0x20 // rsb cs r0 r1 r1 LSR 27 1490 0x2e, 0x0d, 0x60, 0x20 // rsb cs r0 r0 r14 LSR 26
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H A D | assembler-cond-rd-rn-operand-rm-shift-amount-1to32-rsb-t32.h | 452 0xc4, 0xeb, 0xa5, 0x0d // rsb al r13 r4 r5 ASR 2 809 0xcd, 0xeb, 0xa5, 0x0d // rsb al r13 r13 r5 ASR 2 860 0xc8, 0xeb, 0x2e, 0x0d // rsb al r13 r8 r14 ASR 32
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H A D | assembler-cond-rd-rn-operand-rm-shift-amount-1to32-rsbs-a32.h | 890 0xa8, 0x0d, 0x70, 0x80 // rsbs hi r0 r0 r8 LSR 27 1256 0xa1, 0x0d, 0x71, 0x20 // rsbs cs r0 r1 r1 LSR 27 1490 0x2e, 0x0d, 0x70, 0x20 // rsbs cs r0 r0 r14 LSR 26
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H A D | assembler-cond-rd-rn-operand-rm-shift-amount-1to32-rsbs-t32.h | 452 0xd4, 0xeb, 0xa5, 0x0d // rsbs al r13 r4 r5 ASR 2 809 0xdd, 0xeb, 0xa5, 0x0d // rsbs al r13 r13 r5 ASR 2 860 0xd8, 0xeb, 0x2e, 0x0d // rsbs al r13 r8 r14 ASR 32
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H A D | assembler-cond-rd-rn-operand-rm-shift-amount-1to32-rsc-a32.h | 890 0xa8, 0x0d, 0xe0, 0x80 // rsc hi r0 r0 r8 LSR 27 1256 0xa1, 0x0d, 0xe1, 0x20 // rsc cs r0 r1 r1 LSR 27 1490 0x2e, 0x0d, 0xe0, 0x20 // rsc cs r0 r0 r14 LSR 26
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H A D | assembler-cond-rd-rn-operand-rm-shift-amount-1to32-rscs-a32.h | 890 0xa8, 0x0d, 0xf0, 0x80 // rscs hi r0 r0 r8 LSR 27 1256 0xa1, 0x0d, 0xf1, 0x20 // rscs cs r0 r1 r1 LSR 27 1490 0x2e, 0x0d, 0xf0, 0x20 // rscs cs r0 r0 r14 LSR 26
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H A D | assembler-cond-rd-rn-operand-rm-shift-amount-1to32-sbc-a32.h | 890 0xa8, 0x0d, 0xc0, 0x80 // sbc hi r0 r0 r8 LSR 27 1256 0xa1, 0x0d, 0xc1, 0x20 // sbc cs r0 r1 r1 LSR 27 1490 0x2e, 0x0d, 0xc0, 0x20 // sbc cs r0 r0 r14 LSR 26
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H A D | assembler-cond-rd-rn-operand-rm-shift-amount-1to32-sbc-t32.h | 452 0x64, 0xeb, 0xa5, 0x0d // sbc al r13 r4 r5 ASR 2 809 0x6d, 0xeb, 0xa5, 0x0d // sbc al r13 r13 r5 ASR 2 860 0x68, 0xeb, 0x2e, 0x0d // sbc al r13 r8 r14 ASR 32
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H A D | assembler-cond-rd-rn-operand-rm-shift-amount-1to32-sbcs-a32.h | 890 0xa8, 0x0d, 0xd0, 0x80 // sbcs hi r0 r0 r8 LSR 27 1256 0xa1, 0x0d, 0xd1, 0x20 // sbcs cs r0 r1 r1 LSR 27 1490 0x2e, 0x0d, 0xd0, 0x20 // sbcs cs r0 r0 r14 LSR 26
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H A D | assembler-cond-rd-rn-operand-rm-shift-amount-1to32-sbcs-t32.h | 452 0x74, 0xeb, 0xa5, 0x0d // sbcs al r13 r4 r5 ASR 2 809 0x7d, 0xeb, 0xa5, 0x0d // sbcs al r13 r13 r5 ASR 2 860 0x78, 0xeb, 0x2e, 0x0d // sbcs al r13 r8 r14 ASR 32
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H A D | assembler-cond-rd-rn-operand-rm-shift-amount-1to32-sub-a32.h | 890 0xa8, 0x0d, 0x40, 0x80 // sub hi r0 r0 r8 LSR 27 1256 0xa1, 0x0d, 0x41, 0x20 // sub cs r0 r1 r1 LSR 27 1490 0x2e, 0x0d, 0x40, 0x20 // sub cs r0 r0 r14 LSR 26
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H A D | assembler-cond-rd-rn-operand-rm-shift-amount-1to32-sub-t32.h | 452 0xa4, 0xeb, 0xa5, 0x0d // sub al r13 r4 r5 ASR 2 809 0xad, 0xeb, 0xa5, 0x0d // sub al r13 r13 r5 ASR 2 860 0xa8, 0xeb, 0x2e, 0x0d // sub al r13 r8 r14 ASR 32
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H A D | assembler-cond-rd-rn-operand-rm-shift-amount-1to32-subs-a32.h | 890 0xa8, 0x0d, 0x50, 0x80 // subs hi r0 r0 r8 LSR 27 1256 0xa1, 0x0d, 0x51, 0x20 // subs cs r0 r1 r1 LSR 27 1490 0x2e, 0x0d, 0x50, 0x20 // subs cs r0 r0 r14 LSR 26
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H A D | assembler-cond-rd-rn-operand-rm-shift-amount-1to32-subs-t32.h | 452 0xb4, 0xeb, 0xa5, 0x0d // subs al r13 r4 r5 ASR 2 809 0xbd, 0xeb, 0xa5, 0x0d // subs al r13 r13 r5 ASR 2 860 0xb8, 0xeb, 0x2e, 0x0d // subs al r13 r8 r14 ASR 32
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H A D | assembler-cond-rd-rn-operand-rm-asr-a32.h | 161 0x5c, 0x0d, 0xa0, 0xe1 // asr al r0 r12 r13 260 0x52, 0x0d, 0xa0, 0x21 // asr cs r0 r2 r13 1322 0x5d, 0x0d, 0xa0, 0x01 // asr eq r0 r13 r13
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H A D | assembler-cond-rd-rn-operand-rm-asrs-a32.h | 161 0x5c, 0x0d, 0xb0, 0xe1 // asrs al r0 r12 r13 260 0x52, 0x0d, 0xb0, 0x21 // asrs cs r0 r2 r13 1322 0x5d, 0x0d, 0xb0, 0x01 // asrs eq r0 r13 r13
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H A D | assembler-cond-rd-rn-operand-rm-lsl-a32.h | 161 0x1c, 0x0d, 0xa0, 0xe1 // lsl al r0 r12 r13 260 0x12, 0x0d, 0xa0, 0x21 // lsl cs r0 r2 r13 1322 0x1d, 0x0d, 0xa0, 0x01 // lsl eq r0 r13 r13
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H A D | assembler-cond-rd-rn-operand-rm-lsls-a32.h | 161 0x1c, 0x0d, 0xb0, 0xe1 // lsls al r0 r12 r13 260 0x12, 0x0d, 0xb0, 0x21 // lsls cs r0 r2 r13 1322 0x1d, 0x0d, 0xb0, 0x01 // lsls eq r0 r13 r13
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H A D | assembler-cond-rd-rn-operand-rm-lsr-a32.h | 161 0x3c, 0x0d, 0xa0, 0xe1 // lsr al r0 r12 r13 260 0x32, 0x0d, 0xa0, 0x21 // lsr cs r0 r2 r13 1322 0x3d, 0x0d, 0xa0, 0x01 // lsr eq r0 r13 r13
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