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/third_party/node/deps/v8/src/wasm/baseline/riscv64/
H A Dliftoff-assembler-riscv64.h708 __ sub(temp, result_reg, value.gp()); in AtomicBinop()
1172 I32_BINOP(sub, subw)
1188 I32_BINOP_I(sub, Sub32)
1286 I64_BINOP(sub, sub)
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1767 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); in DecodeCopMemInstruction()
1878 Op = ARM_AM::sub; in DecodeAddrMode2IdxInstruction()
1965 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); in DecodeSORegMemOperand()
2581 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); in DecodeAddrMode5Operand()
2601 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm))); in DecodeAddrMode5FP16Operand()
/third_party/toybox/toys/pending/
H A Dbc.c1322 static BcStatus bc_num_a(BcNum *a, BcNum *b, BcNum *c, size_t sub) { in bc_num_a() argument
1333 if (sub && c->len) c->neg = !c->neg; in bc_num_a()
1391 static BcStatus bc_num_s(BcNum *a, BcNum *b, BcNum *c, size_t sub) { in bc_num_s() argument
1404 if (sub && c->len) c->neg = !c->neg; in bc_num_s()
1433 if (sub) neg = !neg; in bc_num_s()
/third_party/vixl/src/aarch64/
H A Dassembler-aarch64.h677 void sub(const Register& rd, const Register& rn, const Operand& operand);
2503 void sub(const VRegister& vd, const VRegister& vn, const VRegister& vm);
2517 // Unsigned halving sub.
2520 // Signed halving sub.
2592 // Signed long multiply-sub by scalar element.
2598 // Signed long multiply-sub by scalar element (second part).
2604 // Unsigned long multiply-sub by scalar element.
2610 // Unsigned long multiply-sub by scalar element (second part).
2664 // Signed saturating doubling long multiply-sub by element.
2670 // Signed saturating doubling long multiply-sub b
[all...]
/third_party/vk-gl-cts/modules/gles31/functional/
H A Des31fTessellationTests.cpp184 const int sub = intPow(base, exp/2);
186 return sub*sub;
188 return sub*sub*base;
/third_party/vixl/test/aarch64/
H A Dtest-disasm-sve-aarch64.cc2204 COMPARE(sub(z9.VnB(), z7.VnB(), z25.VnB()), "sub z9.b, z7.b, z25.b"); in TEST()
2205 COMPARE(sub(z8.VnH(), z8.VnH(), z26.VnH()), "sub z8.h, z8.h, z26.h"); in TEST()
2206 COMPARE(sub(z7.VnS(), z9.VnS(), z27.VnS()), "sub z7.s, z9.s, z27.s"); in TEST()
2207 COMPARE(sub(z6.VnD(), z10.VnD(), z28.VnD()), "sub z6.d, z10.d, z28.d"); in TEST()
2315 COMPARE(sub(z28.VnB(), p2.Merging(), z28.VnB(), z0.VnB()), in TEST()
2316 "sub z2 in TEST()
[all...]
/third_party/mesa3d/src/amd/compiler/
H A Daco_register_allocation.cpp362 std::array<uint32_t, 4>& sub = in fill_subdword() local
365 sub[j] = val; in fill_subdword()
367 if (sub == std::array<uint32_t, 4>{0, 0, 0, 0}) { in fill_subdword()
1101 * also use the correct stride for sub-dword operands */ in get_regs_for_copies()
1463 /* This function assumes RegisterDemand/live_var_analysis rounds up sub-dword in compact_relocate_vars()
1725 // TODO: improve p_create_vector for sub-dword vectors in get_reg_create_vector()
2935 /* kill definitions and late-kill operands and ensure that sub-dword operands can actually in register_allocation()
/third_party/node/deps/openssl/config/archs/darwin64-x86_64-cc/asm/crypto/bn/
H A Dx86_64-mont5.s395 jmp L$sub
397 L$sub: sbbq (%rcx,%r14,8),%rax
402 jnz L$sub
/third_party/node/deps/v8/src/compiler/backend/ppc/
H A Dcode-generator-ppc.cc258 // Overflow checked for add/sub only. in FlagsConditionToCondition()
415 __ sub(i.OutputRegister(), i.InputRegister(0), scratch, LeaveOE, \
1399 __ sub(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1), in AssembleArchInstruction()
2125 ATOMIC_BINOP_CASE(Sub, sub) in AssembleArchInstruction()
/third_party/node/deps/v8/src/codegen/ia32/
H A Dassembler-ia32.cc1296 void Assembler::sub(Operand dst, const Immediate& x) { in sub() function in v8::internal::Assembler
1301 void Assembler::sub(Register dst, Operand src) { in sub() function in v8::internal::Assembler
1307 void Assembler::sub(Operand dst, Register src) { in sub() function in v8::internal::Assembler
/third_party/node/deps/v8/src/wasm/baseline/mips64/
H A Dliftoff-assembler-mips64.h1157 I32_BINOP(sub, subu)
1173 I32_BINOP_I(sub, Subu)
1275 I64_BINOP(sub, dsubu)
/third_party/node/deps/openssl/config/archs/darwin64-x86_64-cc/asm_avx2/crypto/bn/
H A Dx86_64-mont5.s395 jmp L$sub
397 L$sub: sbbq (%rcx,%r14,8),%rax
402 jnz L$sub
/third_party/python/Lib/test/
H A Dtest_zipfile.py3544 sub = root / "b"
3545 assert sub.name == "b"
3546 assert sub.parent
H A Dtest_xml_etree.py2792 sub = MyElement('bar')
2793 sub.text = 'subtext'
2794 e.append(sub)
3079 doc = ET.XML("<root>a&amp;<sub>b&amp;</sub>c&amp;</root>")
/third_party/ffmpeg/libavcodec/x86/
H A Dvp9intrapred.asm1732 sub stride4q, strideq
1791 sub stride8q, strideq
/third_party/mesa3d/src/gallium/drivers/vc4/
H A Dvc4_program.c601 struct qinst *sub = qir_FSUB_dest(c, result, in ntq_ffloor() local
603 sub->cond = QPU_COND_NS; in ntq_ffloor()
/third_party/node/deps/v8/src/wasm/baseline/mips/
H A Dliftoff-assembler-mips.h966 I32_BINOP(sub, subu)
982 I32_BINOP_I(sub, Subu)
/third_party/python/Lib/
H A Dturtle.py3941 newdocstr = parexp.sub(":", newdocstr)
3953 newdocstr = parexp.sub(":", newdocstr)
/third_party/python/Lib/tkinter/
H A D__init__.py77 value = _magic_re.sub(r'\\\1', value)
79 value = _space_re.sub(r'\\\1', value)
/third_party/vixl/src/aarch32/
H A Ddisasm-aarch32.cc3164 void Disassembler::sub(Condition cond, in sub() function in vixl::aarch32::Disassembler
3178 void Disassembler::sub(Condition cond, Register rd, const Operand& operand) { in sub() function in vixl::aarch32::Disassembler
7030 sub(CurrentCond(), in DecodeT32()
7072 sub(CurrentCond(), Narrow, Register(rd), Register(rn), imm); in DecodeT32()
7229 sub(CurrentCond(), Register(rd), imm); in DecodeT32()
7232 sub(CurrentCond(), Narrow, Register(rd), Register(rd), imm); in DecodeT32()
8040 sub(CurrentCond(), Narrow, sp, sp, imm); in DecodeT32()
8886 sub(CurrentCond(), Wide, Register(rd), sp, imm); in DecodeT32()
8889 sub(CurrentCond(), Best, Register(rd), sp, imm); in DecodeT32()
8913 sub(CurrentCon in DecodeT32()
[all...]
/third_party/icu/icu4c/source/i18n/
H A DdecNumber.cpp1788 uByte sub; /* add or subtract */ in uprv_decNumberNextToward() local
1797 sub=0; /* add, please */ in uprv_decNumberNextToward()
1806 sub=DECNEG; /* subtract, please */ in uprv_decNumberNextToward()
1811 decAddOp(res, lhs, &dtiny, &workset, sub, &status); /* + or - */ in uprv_decNumberNextToward()
/third_party/node/deps/icu-small/source/i18n/
H A DdecNumber.cpp1788 uByte sub; /* add or subtract */ in uprv_decNumberNextToward() local
1797 sub=0; /* add, please */ in uprv_decNumberNextToward()
1806 sub=DECNEG; /* subtract, please */ in uprv_decNumberNextToward()
1811 decAddOp(res, lhs, &dtiny, &workset, sub, &status); /* + or - */ in uprv_decNumberNextToward()
/third_party/node/deps/v8/src/codegen/arm64/
H A Dassembler-arm64.cc853 void Assembler::sub(const Register& rd, const Register& rn, in sub() function in v8::internal::Assembler
870 sub(rd, zr, operand); in neg()
3060 V(sub, NEON_SUB, vd.IsVector() || vd.Is1D()) \
3647 // add/sub wsp, <Wn>, <Wm> [, LSL #0-3 ] in AddSub()
3648 // add/sub <Wd>, wsp, <Wm> [, LSL #0-3 ] in AddSub()
3649 // add/sub wsp, wsp, <Wm> [, LSL #0-3 ] in AddSub()
3652 // extended register mode, and emit an add/sub extended instruction. in AddSub()
4676 // sub sp, sp, #0 in PatchSubSp()
4681 sub(sp, sp, immediate); in PatchSubSp()
/third_party/node/deps/v8/src/codegen/riscv64/
H A Dmacro-assembler-riscv64.cc458 sub(rd, rs, rt.rm()); in Sub64()
495 sub(rd, rs, scratch); in Sub64()
3140 // with the slt instructions. We could use sub or add instead but we would miss
4099 sub(scratch2, left, right_reg); in SubOverflow64()
4105 sub(dst, left, right_reg); in SubOverflow64()
/third_party/skia/third_party/externals/icu/source/i18n/
H A DdecNumber.cpp1788 uByte sub; /* add or subtract */ in uprv_decNumberNextToward() local
1797 sub=0; /* add, please */ in uprv_decNumberNextToward()
1806 sub=DECNEG; /* subtract, please */ in uprv_decNumberNextToward()
1811 decAddOp(res, lhs, &dtiny, &workset, sub, &status); /* + or - */ in uprv_decNumberNextToward()

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