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/third_party/mesa3d/src/compiler/nir/
H A Dnir_lower_amul.c80 nir_instr *parent = src->ssa->parent_instr; in lower_large_src()
H A Dnir_opt_large_constants.c365 nir_ssa_def_rewrite_uses(&intrin->dest.ssa, in nir_opt_large_constants()
H A Dnir_opt_access.c176 gather_buffer_access(state, ssbo ? instr->src[0].ssa : NULL, in gather_intrinsic()
H A Dnir_lower_idiv.c262 if (alu->dest.dest.ssa.bit_size > 32) in inst_is_idiv()
H A Dnir_lower_alu.c219 nir_ssa_def_rewrite_uses(&instr->dest.dest.ssa, lowered); in lower_alu_instr()
/third_party/mesa3d/src/gallium/drivers/asahi/
H A Dagx_blit.c53 nir_store_var(&b, out, &tex->dest.ssa, 0xFF); in agx_build_reload_shader()
/third_party/mesa3d/src/gallium/drivers/etnaviv/
H A Detnaviv_compiler_nir_liveness.c48 unsigned *live_map; /* to map ssa/reg index into defs array */
76 nir_instr *instr = src->ssa->parent_instr; in set_src_live()
161 /* We now know how many unique ssa definitions we have and we can go in etna_live_defs()
/third_party/mesa3d/src/amd/vulkan/
H A Dradv_meta_decompress.c63 &b, 4, 32, &nir_build_deref_var(&b, input_img)->dest.ssa, global_id, nir_ssa_undef(&b, 1, 32), in build_expand_depth_stencil_compute_shader()
73 nir_image_deref_store(&b, &nir_build_deref_var(&b, output_img)->dest.ssa, global_id, in build_expand_depth_stencil_compute_shader()
H A Dradv_pipeline.c2811 nir_ssa_def_rewrite_uses(&intr->dest.ssa, nir_imm_zero(&b, 1, 32)); in radv_lower_viewport_to_zero()
3951 if (alu->dest.dest.ssa.num_components > 1) in lower_bit_size_callback()
3954 if (alu->dest.dest.ssa.bit_size & (8 | 16)) { in lower_bit_size_callback()
3955 unsigned bit_size = alu->dest.dest.ssa.bit_size; in lower_bit_size_callback()
4019 const unsigned bit_size = alu->dest.dest.ssa.bit_size; in opt_vectorize_callback()
4060 if (src->ssa->num_components == 1) in non_uniform_access_callback()
4209 unsigned num_components = intrin->dest.ssa.num_components; in radv_lower_vs_input()
4218 unsigned mask = nir_ssa_def_components_read(&intrin->dest.ssa) << component; in radv_lower_vs_input()
4231 intrin->dest.ssa.num_components = intrin->num_components; in radv_lower_vs_input()
4242 channels[i] = nir_channel(&b, &intrin->dest.ssa, swizzl in radv_lower_vs_input()
[all...]
H A Dradv_meta_fast_clear.c62 &b, 4, 32, &nir_build_deref_var(&b, input_img)->dest.ssa, img_coord, nir_ssa_undef(&b, 1, 32), in build_dcc_decompress_compute_shader()
72 nir_image_deref_store(&b, &nir_build_deref_var(&b, output_img)->dest.ssa, img_coord, in build_dcc_decompress_compute_shader()
/third_party/mesa3d/src/panfrost/util/
H A Dpan_lower_framebuffer.c544 unpacked = nir_resize_vector(b, unpacked, intr->dest.ssa.num_components); in pan_lower_fb_load()
550 nir_ssa_def_rewrite_uses_after(&intr->dest.ssa, unpacked, &intr->instr); in pan_lower_fb_load()
/kernel/linux/linux-6.6/tools/testing/selftests/sgx/
H A Dmain.c1233 void *addr, *tcs, *stack_end, *ssa; in TEST_F() local
1301 ssa = (void *)self->encl.encl_base + total_size + 2 * PAGE_SIZE; in TEST_F()
1328 eaccept_op.epc_addr = (unsigned long)ssa; in TEST_F()
1363 init_tcs_page_op.ssa = (unsigned long)total_size + 2 * PAGE_SIZE; in TEST_F()
1482 eaccept_op.epc_addr = (unsigned long)ssa; in TEST_F()
/third_party/mesa3d/src/freedreno/ir3/
H A Dir3_compiler_nir.c373 dst_sz = alu->dest.dest.ssa.num_components; in emit_alu()
528 (list_length(&alu->src[0].src.ssa->uses) == 1)) { in emit_alu()
1540 intr->dest.ssa.num_components > 1) { in emit_intrinsic_load_ssbo()
1550 unsigned num_components = intr->dest.ssa.num_components; in emit_intrinsic_load_ssbo()
1552 emit_sam(ctx, OPC_ISAM, info, utype_for_size(intr->dest.ssa.bit_size), in emit_intrinsic_load_ssbo()
1885 ctx->so->fragcoord_compmask |= nir_ssa_def_components_read(&intr->dest.ssa); in get_frag_coord()
2561 unsigned components = intr->dest.ssa.num_components; in emit_intrinsic()
3203 sam->prefetch.input_offset = ir3_nir_coord_offset(tex->src[idx].src.ssa); in emit_tex()
3388 compile_assert(ctx, nphi->dest.ssa.num_components == 1); in emit_phi()
3428 if (nsrc->src.ssa in read_phi_src()
[all...]
H A Dir3_nir.c211 return nir_ishl(b, &intr->dest.ssa, nir_imm_int(b, ssbo_size_to_bytes_shift)); in ir3_nir_lower_ssbo_size_instr()
594 nir_ssa_def_rewrite_uses(&intrin->dest.ssa, zero); in ir3_nir_lower_view_layer_id()
/third_party/mesa3d/src/intel/compiler/
H A Dbrw_fs_nir.cpp506 !instr->src[0].src.ssa->parent_instr) in optimize_extract_to_float()
509 if (instr->src[0].src.ssa->parent_instr->type != nir_instr_type_alu) in optimize_extract_to_float()
513 nir_instr_as_alu(instr->src[0].src.ssa->parent_instr); in optimize_extract_to_float()
2074 brw_reg_type_from_bit_size(src.ssa->bit_size, BRW_REGISTER_TYPE_D);
2075 reg = bld.vgrf(reg_type, src.ssa->num_components);
2077 reg = nir_ssa_values[src.ssa->index];
2123 brw_reg_type_from_bit_size(dest.ssa.bit_size,
2124 dest.ssa.bit_size == 8 ?
2127 nir_ssa_values[dest.ssa.index] =
2128 bld.vgrf(reg_type, dest.ssa
[all...]
H A Dbrw_nir_lower_rt_intrinsics.c332 nir_ssa_def_rewrite_uses(&intrin->dest.ssa, in lower_rt_intrinsics_impl()
/third_party/mesa3d/src/intel/vulkan/
H A Danv_nir_lower_multiview.c241 nir_ssa_def_rewrite_uses(&load->dest.ssa, value); in anv_nir_lower_multiview()
/third_party/mesa3d/src/gallium/drivers/lima/ir/gp/
H A Dgpir.h417 /* lookup for vector ssa */
419 int ssa; member
/third_party/mesa3d/src/panfrost/midgard/
H A Dmidgard_compile.c105 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
119 i.src[0] = ssa; \
123 i.dest = ssa; \
237 nir_ssa_def *addr = intr->src[0].ssa; in midgard_nir_lower_global_load_instr()
260 load = &shared_load->dest.ssa; in midgard_nir_lower_global_load_instr()
271 nir_ssa_def_rewrite_uses(&intr->dest.ssa, nir_vec(b, comps, ncomps)); in midgard_nir_lower_global_load_instr()
601 BITSET_SET(ctx->already_emitted, (*dest)->ssa.index); in mir_accept_dest_mod()
734 if (dest->is_ssa && BITSET_TEST(ctx->already_emitted, dest->ssa.index)) in emit_alu()
3163 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa in midgard_compile_shader_nir()
/third_party/mesa3d/src/gallium/drivers/r600/sfn/
H A Dsfn_shader.cpp860 bool uses_retval = !instr->dest.is_ssa || !list_is_empty(&instr->dest.ssa.uses); in emit_atomic_local_shared()
1117 << intr->dest.ssa.index << " const["<< i << "]: "<< intr->const_index[i] << "\n"; in load_uniform()
1236 << instr->dest.ssa.index << " const["<< i << "]: "<< instr->const_index[i] << "\n"; in load_ubo()
/third_party/mesa3d/src/gallium/drivers/d3d12/
H A Dd3d12_blit.cpp670 nir_ssa_def *tex_deref = &nir_build_deref_var(&b, sampler)->dest.ssa; in get_stencil_resolve_fs()
698 nir_channel(&b, nir_i2f32(&b, &txs->dest.ssa), 1), in get_stencil_resolve_fs()
721 nir_store_var(&b, stencil_out, nir_channel(&b, &tex->dest.ssa, 1), 0x1); in get_stencil_resolve_fs()
/third_party/mesa3d/src/panfrost/bifrost/
H A Dbifrost_compile.c4358 nir_invalidate_divergence_ssa(nir_ssa_def *ssa, UNUSED void *data) in nir_invalidate_divergence_ssa() argument
4360 ssa->divergent = false; in nir_invalidate_divergence_ssa()
4399 nir_ssa_def *in = intr->src[0].ssa; in bifrost_nir_lower_blend_components()
4591 nir_ssa_def *cast = nir_convert_to_bit_size(b, intr->src[0].ssa, type, 16); in bifrost_nir_lower_i8_fragout_impl()
4612 nir_load_output(b, intr->num_components, 16, intr->src[0].ssa, in bifrost_nir_lower_i8_fragin_impl()
4619 nir_ssa_def_rewrite_uses(&intr->dest.ssa, cast); in bifrost_nir_lower_i8_fragin_impl()
4672 nir_ssa_def *value = intr->src[0].ssa; in bifrost_nir_lower_store_component()
4681 nir_ssa_def *prev_ssa = prev->src[0].ssa; in bifrost_nir_lower_store_component()
4803 nir_ssa_scalar x = nir_ssa_scalar_resolved(src.ssa, 0); in bi_gather_texcoords()
4804 nir_ssa_scalar y = nir_ssa_scalar_resolved(src.ssa, in bi_gather_texcoords()
[all...]
/kernel/linux/linux-5.10/drivers/net/ethernet/freescale/fman/
H A Dfman_port.c333 u32 ssa; /* Soft Sequence Attachment */ member
730 iowrite32be(0x00000000, &regs->pmda[i].ssa); in init_hwp()
735 iowrite32be(HWP_HXS_SH_PAD_REM, &regs->pmda[HWP_HXS_TCP_OFFSET].ssa); in init_hwp()
736 iowrite32be(HWP_HXS_SH_PAD_REM, &regs->pmda[HWP_HXS_UDP_OFFSET].ssa); in init_hwp()
/kernel/linux/linux-6.6/drivers/net/ethernet/freescale/fman/
H A Dfman_port.c307 u32 ssa; /* Soft Sequence Attachment */ member
704 iowrite32be(0x00000000, &regs->pmda[i].ssa); in init_hwp()
709 iowrite32be(HWP_HXS_SH_PAD_REM, &regs->pmda[HWP_HXS_TCP_OFFSET].ssa); in init_hwp()
710 iowrite32be(HWP_HXS_SH_PAD_REM, &regs->pmda[HWP_HXS_UDP_OFFSET].ssa); in init_hwp()
/third_party/mesa3d/src/broadcom/vulkan/
H A Dv3dv_pipeline.c659 nir_ssa_def_rewrite_uses(&instr->dest.ssa, in lower_vulkan_resource_index()
680 nir_deref_instr *deref = nir_instr_as_deref(src->src.ssa->parent_instr); in lower_tex_src_to_offset()
684 nir_instr_as_deref(deref->parent.ssa->parent_instr); in lower_tex_src_to_offset()
821 nir_instr_as_deref(deref->parent.ssa->parent_instr); in lower_image_deref()
901 nir_ssa_def_rewrite_uses(&instr->dest.ssa, instr->src[0].ssa); in lower_intrinsic()

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