/third_party/mesa3d/src/compiler/spirv/ |
H A D | spirv_to_nir.c | 285 return val->ssa; in vtn_ssa_value() 289 struct vtn_ssa_value *ssa = in vtn_ssa_value() local 291 ssa->def = vtn_pointer_to_ssa(b, val->pointer); in vtn_ssa_value() 292 return ssa; in vtn_ssa_value() 301 struct vtn_ssa_value *ssa) in vtn_push_ssa_value() 306 vtn_fail_if(ssa->type != glsl_get_bare_type(type->type), in vtn_push_ssa_value() 311 val = vtn_push_pointer(b, value_id, vtn_pointer_from_ssa(b, ssa->def, type)); in vtn_push_ssa_value() 316 val->ssa = ssa; in vtn_push_ssa_value() 325 struct vtn_ssa_value *ssa in vtn_get_nir_ssa() local 300 vtn_push_ssa_value(struct vtn_builder *b, uint32_t value_id, struct vtn_ssa_value *ssa) vtn_push_ssa_value() argument 341 struct vtn_ssa_value *ssa = vtn_create_ssa_value(b, type->type); vtn_push_nir_ssa() local 4054 struct vtn_ssa_value *ssa = vtn_create_ssa_value(b, type->type); vtn_handle_composite() local 5716 struct vtn_ssa_value *ssa = vtn_create_ssa_value(b, value.glsl_type); ray_query_load_intrinsic_create() local [all...] |
/third_party/mesa3d/src/freedreno/ir3/ |
H A D | ir3_context.c | 196 value = ir3_get_dst_ssa(ctx, &dst->ssa, n); in ir3_get_dst() 201 /* NOTE: in non-ssa case, we don't really need to store last_dst in ir3_get_dst() 216 entry = _mesa_hash_table_search(ctx->def_ht, src->ssa); in ir3_get_src() 264 ir3_set_dst_type(ssa(dst->srcs[0]), true); in ir3_put_dst() 265 ir3_fixup_src_type(ssa(dst->srcs[0])); in ir3_put_dst() 374 dst[i] = ssa(src->srcs[i + base]); in ir3_split_dest() 544 * length 1 to ssa. in ir3_declare_array()
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H A D | ir3_nir_analyze_ubo_ranges.c | 247 *srcp = alu->src[1].src.ssa; in handle_partial_const() 249 *srcp = alu->src[0].src.ssa; in handle_partial_const() 335 nir_load_uniform(b, instr->num_components, instr->dest.ssa.bit_size, in lower_ubo_load_to_uniform() 338 nir_ssa_def_rewrite_uses(&instr->dest.ssa, uniform); in lower_ubo_load_to_uniform()
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H A D | ir3_nir_lower_load_barycentric_at_sample.c | 44 nir_ssa_def *pos = load_sample_pos(b, intr->src[0].ssa); in lower_load_barycentric_at_sample()
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H A D | ir3_a6xx.c | 55 ldib->cat6.type = intr->dest.ssa.bit_size == 16 ? TYPE_U16 : TYPE_U32; in emit_intrinsic_load_ssbo() 83 stib->cat6.type = intr->src[0].ssa->bit_size == 16 ? TYPE_U16 : TYPE_U32; in emit_intrinsic_store_ssbo() 395 load->cat6.type = type_uint_size(intr->dest.ssa.bit_size); in emit_intrinsic_load_global_ir3() 435 stg->cat6.type = type_uint_size(intr->src[0].ssa->bit_size); in emit_intrinsic_store_global_ir3()
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/third_party/mesa3d/src/amd/vulkan/ |
H A D | radv_meta_resolve_cs.c | 102 nir_image_deref_store(&b, &nir_build_deref_var(&b, output_img)->dest.ssa, img_coord, in build_resolve_compute_shader() 155 nir_ssa_def *input_img_deref = &nir_build_deref_var(&b, input_img)->dest.ssa; in build_depth_stencil_resolve_compute_shader() 175 nir_ssa_def *outval = &tex->dest.ssa; in build_depth_stencil_resolve_compute_shader() 198 outval = nir_fadd(&b, outval, &tex_add->dest.ssa); in build_depth_stencil_resolve_compute_shader() 202 outval = nir_fmin(&b, outval, &tex_add->dest.ssa); in build_depth_stencil_resolve_compute_shader() 204 outval = nir_umin(&b, outval, &tex_add->dest.ssa); in build_depth_stencil_resolve_compute_shader() 208 outval = nir_fmax(&b, outval, &tex_add->dest.ssa); in build_depth_stencil_resolve_compute_shader() 210 outval = nir_umax(&b, outval, &tex_add->dest.ssa); in build_depth_stencil_resolve_compute_shader() 223 nir_image_deref_store(&b, &nir_build_deref_var(&b, output_img)->dest.ssa, coord, in build_depth_stencil_resolve_compute_shader()
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H A D | radv_meta_fmask_copy.c | 61 nir_ssa_def *input_img_deref = &nir_build_deref_var(&b, input_img)->dest.ssa; in build_fmask_copy_compute_shader() 80 nir_ssa_def *frag_mask = &frag_mask_fetch->dest.ssa; in build_fmask_copy_compute_shader() 116 nir_ssa_def *outval = &frag_fetch->dest.ssa; in build_fmask_copy_compute_shader() 117 nir_image_deref_store(&b, &nir_build_deref_var(&b, output_img)->dest.ssa, dst_coord, in build_fmask_copy_compute_shader()
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/third_party/mesa3d/src/compiler/nir/ |
H A D | nir_lower_blend.c | 387 nir_ssa_def *src = nir_pad_vector(b, store->src[1].ssa, 4); in nir_lower_blend_store() 417 store->dest.ssa.num_components = num_components; in nir_lower_blend_store() 468 nir_ssa_def *val = nir_resize_vector(b, &intrin->dest.ssa, in nir_lower_blend_instr() 471 nir_ssa_def_rewrite_uses_after(&intrin->dest.ssa, val, in nir_lower_blend_instr()
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H A D | nir_schedule.c | 166 return _mesa_hash_table_search_data(scoreboard->remaining_uses, src->ssa); in nir_schedule_scoreboard_get_src() 183 return nir_schedule_def_pressure(src->ssa); in nir_schedule_src_pressure() 192 return nir_schedule_def_pressure(&dest->ssa); in nir_schedule_dest_pressure() 881 src->ssa->parent_instr->type != nir_instr_type_load_const) { in nir_schedule_mark_src_scheduled() 882 nir_foreach_use(other_src, src->ssa) { in nir_schedule_mark_src_scheduled() 904 src->is_ssa ? (void *)src->ssa : (void *)src->reg.reg, in nir_schedule_mark_src_scheduled()
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H A D | nir_lower_multiview.c | 327 nir_ssa_def_rewrite_uses(&intrin->dest.ssa, view_index); in nir_lower_multiview() 337 nir_src_for_ssa(&pos_deref->dest.ssa)); in nir_lower_multiview()
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H A D | nir_lower_poly_line_smooth.c | 65 intr->src[0].ssa); in lower_polylinesmooth()
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H A D | nir_opt_fragdepth.c | 82 if (ssa_def_is_source_depth(intrin->src[1].ssa)) { in nir_opt_fragdepth()
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H A D | nir_lower_patch_vertices.c | 94 nir_ssa_def_rewrite_uses(&intr->dest.ssa, in nir_lower_patch_vertices()
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H A D | nir_opt_gcm.c | 172 nir_instr *src_instr = src->ssa->parent_instr; in is_src_scalarizable() 435 gcm_schedule_early_instr(src->ssa->parent_instr, void_state); in gcm_schedule_early_src() 445 &state->instr_infos[src->ssa->parent_instr->index]; in gcm_schedule_early_src() 648 if (phi_src->src.ssa == def) in gcm_schedule_late_def()
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/third_party/mesa3d/src/gallium/drivers/r600/sfn/ |
H A D | sfn_nir_vectorize_vs_inputs.c | 152 intr->dest.ssa.bit_size, NULL); in r600_create_new_load() 158 new_intr->src[0] = nir_src_for_ssa(&deref->dest.ssa); in r600_create_new_load() 168 nir_ssa_def *load = nir_swizzle(b, &new_intr->dest.ssa, channels, old_num_comps); in r600_create_new_load() 169 nir_ssa_def_rewrite_uses(&intr->dest.ssa, load); in r600_create_new_load()
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/third_party/mesa3d/src/panfrost/midgard/ |
H A D | compiler.h | 460 nir_ssa_index(nir_ssa_def *ssa) in nir_ssa_index() argument 462 return (ssa->index << 1) | 0; in nir_ssa_index() 469 return nir_ssa_index(src->ssa); in nir_src_index() 480 return (dst->ssa.index << 1) | 0; in nir_dest_index()
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/third_party/mesa3d/src/panfrost/util/ |
H A D | pan_lower_helper_invocation.c | 46 nir_ssa_def_rewrite_uses(&intr->dest.ssa, eq); in pan_lower_helper_invocation_instr()
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H A D | pan_lower_sample_position.c | 61 nir_ssa_def_rewrite_uses(&intr->dest.ssa, decoded); in pan_lower_sample_pos_impl()
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/third_party/mesa3d/src/broadcom/compiler/ |
H A D | v3d_nir_lower_load_store_bitsize.c | 159 dest_components[component] = &new_intr->dest.ssa; in lower_load_bitsize() 165 nir_ssa_def_rewrite_uses(&intr->dest.ssa, new_dst); in lower_load_bitsize()
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H A D | v3d_nir_lower_io.c | 112 nir_src_for_ssa(nir_ishl(b, intr->src[0].ssa, in v3d_nir_lower_uniform() 358 nir_ssa_def *result = &intr->dest.ssa; in v3d_nir_lower_fragment_input() 375 if (result != &intr->dest.ssa) { in v3d_nir_lower_fragment_input() 376 nir_ssa_def_rewrite_uses_after(&intr->dest.ssa, in v3d_nir_lower_fragment_input()
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/third_party/mesa3d/src/intel/vulkan/ |
H A D | anv_nir_compute_push_layout.c | 171 nir_imul_imm(b, intrin->src[0].ssa, sizeof(uint64_t)), in anv_nir_compute_push_layout() 175 nir_ssa_def_rewrite_uses(&intrin->dest.ssa, pc_load); in anv_nir_compute_push_layout()
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/third_party/mesa3d/src/gallium/drivers/etnaviv/ |
H A D | etnaviv_compiler_nir_ra.c | 133 * (some ssa values do not represent an allocated register) in etna_ra_assign() 169 if (dest->ssa.num_components == 2) in etna_ra_assign() 171 if (dest->ssa.num_components == 3) in etna_ra_assign()
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/third_party/mesa3d/src/compiler/nir/tests/ |
H A D | dce_tests.cpp | 98 nir_store_var(&bld, var, &phi->dest.ssa, 0x1); in TEST_F()
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/third_party/mesa3d/src/imagination/rogue/nir/ |
H A D | rogue_nir_pfo.c | 37 nir_ssa_def *new_output_src_ssa = nir_pack_unorm_4x8(b, output_src->ssa); in insert_pfo()
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/third_party/mesa3d/src/gallium/auxiliary/gallivm/ |
H A D | lp_bld_nir.c | 153 static LLVMValueRef get_ssa_src(struct lp_build_nir_context *bld_base, nir_ssa_def *ssa) in get_ssa_src() argument 155 return bld_base->ssa_defs[ssa->index]; in get_ssa_src() 180 return get_ssa_src(bld_base, src.ssa); in get_src() 194 assign_ssa_dest(struct lp_build_nir_context *bld_base, const nir_ssa_def *ssa, in assign_ssa_dest() argument 197 if ((ssa->num_components == 1 || is_aos(bld_base))) { in assign_ssa_dest() 198 assign_ssa(bld_base, ssa->index, vals[0]); in assign_ssa_dest() 200 assign_ssa(bld_base, ssa->index, in assign_ssa_dest() 202 vals, ssa->num_components)); in assign_ssa_dest() 228 assign_ssa_dest(bld_base, &dest->ssa, vals); in assign_dest() 240 assign_ssa_dest(bld_base, &dest->dest.ssa, val in assign_alu_dest() [all...] |