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/third_party/mesa3d/src/intel/compiler/
H A Dbrw_fs.h541 struct brw_reg src1);
H A Dbrw_lower_logical_sends.cpp2405 const fs_reg src1 = is_int_div ? inst->src[0] : inst->src[1]; in lower_math_logical_send() local
2411 bld.MOV(fs_reg(MRF, inst->base_mrf + 1, src1.type), src1); in lower_math_logical_send() local
/third_party/mesa3d/src/gallium/drivers/llvmpipe/
H A Dlp_state_fs_linear.c93 const uint32_t *src1; member
/third_party/wpa_supplicant/wpa_supplicant-2.9_standard/src/utils/
H A Dcommon.h537 const u8 *src1, size_t src1_len,
/third_party/ffmpeg/libavcodec/
H A Dhevcdec.c1584 uint8_t *src1 = ref1->data[0] + y_off1 * src1stride + (int)((unsigned)x_off1 << s->ps.sps->pixel_shift); in luma_mc_bi() local
1610 s->vdsp.emulated_edge_mc(lc->edge_emu_buffer2, src1 - offset, in luma_mc_bi()
1616 src1 = lc->edge_emu_buffer2 + buf_offset; in luma_mc_bi()
1623 s->hevcdsp.put_hevc_qpel_bi[idx][!!my1][!!mx1](dst, dststride, src1, src1stride, lc->tmp, in luma_mc_bi()
1626 s->hevcdsp.put_hevc_qpel_bi_w[idx][!!my1][!!mx1](dst, dststride, src1, src1stride, lc->tmp, in luma_mc_bi()
1724 uint8_t *src1 = ref0->data[cidx+1]; in chroma_mc_bi() local
1751 src1 += y_off0 * src1stride + (int)((unsigned)x_off0 << s->ps.sps->pixel_shift); in chroma_mc_bi()
1762 s->vdsp.emulated_edge_mc(lc->edge_emu_buffer, src1 - offset1, in chroma_mc_bi()
1769 src1 = lc->edge_emu_buffer + buf_offset1; in chroma_mc_bi()
1792 s->hevcdsp.put_hevc_epel[idx][!!my0][!!mx0](lc->tmp, src1, src1strid in chroma_mc_bi()
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H A Dmjpegdec.c2762 uint8_t *src1 = &((uint8_t *)s->picture_ptr->data[p])[i * s->upscale_v[p] / (s->upscale_v[p] + 1) * s->linesize[p]]; in ff_mjpeg_receive_frame() local
2764 if (s->upscale_v[p] != 2 && (src1 == src2 || i == h - 1)) { in ff_mjpeg_receive_frame()
2765 memcpy(dst, src1, w); in ff_mjpeg_receive_frame()
2768 dst[index] = (src1[index] + src2[index]) >> 1; in ff_mjpeg_receive_frame()
H A Datrac3.c120 void (*vector_fmul)(float *dst, const float *src0, const float *src1,
/third_party/node/deps/v8/src/compiler/backend/arm64/
H A Dinstruction-selector-arm64.cc4116 InstructionOperand* src0, InstructionOperand* src1) { in ArrangeShuffleTable()
4119 *src0 = *src1 = g->UseRegister(input0); in ArrangeShuffleTable()
4123 *src1 = g->UseFixed(input1, fp_fixed2); in ArrangeShuffleTable()
4177 InstructionOperand src0, src1; in VisitI8x16Shuffle() local
4178 ArrangeShuffleTable(&g, input0, input1, &src0, &src1); in VisitI8x16Shuffle()
4179 Emit(kArm64I8x16Shuffle, g.DefineAsRegister(node), src0, src1, in VisitI8x16Shuffle()
4115 ArrangeShuffleTable(Arm64OperandGenerator* g, Node* input0, Node* input1, InstructionOperand* src0, InstructionOperand* src1) ArrangeShuffleTable() argument
/third_party/mesa3d/src/compiler/glsl/
H A Dglsl_to_nir.cpp93 nir_alu_instr *emit(nir_op op, unsigned dest_size, nir_ssa_def *src1);
94 nir_alu_instr *emit(nir_op op, unsigned dest_size, nir_ssa_def *src1,
96 nir_alu_instr *emit(nir_op op, unsigned dest_size, nir_ssa_def *src1,
/third_party/mesa3d/src/nouveau/codegen/
H A Dnv50_ir_from_nir.cpp2858 Value *src1;
2860 src1 = loadImm(getSSA(8), 0.0);
2862 src1 = zero;
2865 mkCmp(OP_SET, cc, TYPE_U32, newDefs[0], sTypes[0], getSrc(&insn->src[0]), src1);
/third_party/mesa3d/src/gallium/drivers/svga/
H A Dsvga_tgsi_vgpu10.c6490 const struct tgsi_full_src_register *src1, in emit_instruction_opn()
6498 emit_src_register(emit, src1); in emit_instruction_opn()
6521 const struct tgsi_full_src_register *src1, in emit_instruction_op2()
6524 emit_instruction_opn(emit, opcode, dst, src1, src2, NULL, FALSE, FALSE); in emit_instruction_op2()
6531 const struct tgsi_full_src_register *src1, in emit_instruction_op3()
6535 emit_instruction_opn(emit, opcode, dst, src1, src2, src3, FALSE, FALSE); in emit_instruction_op3()
7054 /* dst.x = (src0.x < 0) ? src1.x : src2.x in emit_cmp()
7055 * dst.y = (src0.y < 0) ? src1.y : src2.y in emit_cmp()
7056 * dst.z = (src0.z < 0) ? src1.z : src2.z in emit_cmp()
7057 * dst.w = (src0.w < 0) ? src1 in emit_cmp()
6487 emit_instruction_opn(struct svga_shader_emitter_v10 *emit, unsigned opcode, const struct tgsi_full_dst_register *dst, const struct tgsi_full_src_register *src1, const struct tgsi_full_src_register *src2, const struct tgsi_full_src_register *src3, boolean saturate, bool precise) emit_instruction_opn() argument
6518 emit_instruction_op2(struct svga_shader_emitter_v10 *emit, VGPU10_OPCODE_TYPE opcode, const struct tgsi_full_dst_register *dst, const struct tgsi_full_src_register *src1, const struct tgsi_full_src_register *src2) emit_instruction_op2() argument
6528 emit_instruction_op3(struct svga_shader_emitter_v10 *emit, VGPU10_OPCODE_TYPE opcode, const struct tgsi_full_dst_register *dst, const struct tgsi_full_src_register *src1, const struct tgsi_full_src_register *src2, const struct tgsi_full_src_register *src3) emit_instruction_op3() argument
8205 emit_comparison(struct svga_shader_emitter_v10 *emit, SVGA3dCmpFunc func, const struct tgsi_full_dst_register *dst, const struct tgsi_full_src_register *src0, const struct tgsi_full_src_register *src1) emit_comparison() argument
9400 struct tgsi_full_src_register src1 = check_double_src(emit, &inst->Src[1]); emit_dmad() local
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/third_party/mesa3d/src/amd/vulkan/
H A Dradv_pipeline.c4390 nir_ssa_def *src1 = values[i * 2 + 1]; in radv_lower_fs_output() local
4395 src1 = nir_imm_zero(&b, 1, input_16_bit ? 16 : 32); in radv_lower_fs_output()
4399 values[i] = nir_pack_32_2x16_split(&b, src0, src1); in radv_lower_fs_output()
4401 values[i] = nir_pack_half_2x16_split(&b, src0, src1); in radv_lower_fs_output()
4404 values[i] = nir_pack_unorm_2x16(&b, nir_vec2(&b, src0, src1)); in radv_lower_fs_output()
4406 values[i] = nir_pack_snorm_2x16(&b, nir_vec2(&b, src0, src1)); in radv_lower_fs_output()
4408 values[i] = nir_pack_uint_2x16(&b, nir_vec2(&b, src0, src1)); in radv_lower_fs_output()
4410 values[i] = nir_pack_sint_2x16(&b, nir_vec2(&b, src0, src1)); in radv_lower_fs_output()
/third_party/ltp/tools/sparse/sparse-src/
H A Dflow.c247 pseudo = def->src1; in try_to_simplify_bb()
/third_party/mesa3d/src/panfrost/lib/
H A Dpan_blend.c696 options.src1 = s_src[1]; in pan_blend_create_shader()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
H A DSIFixSGPRCopies.cpp703 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src1);
740 // Move src1 to be in M0
/third_party/node/deps/v8/src/wasm/baseline/
H A Dliftoff-compiler.cc3447 LiftoffRegister src1 = __ PopToRegister(LiftoffRegList{src3, src2});
3448 // Reusing src1 and src2 will complicate codegen for select for some
3449 // backend, so we allow only reusing src3 (the mask), and pin src1 and src2.
3452 LiftoffRegList{src1, src2})
3454 CallEmitFn(fn, dst, src1, src2, src3);
3461 CheckS128Nan(dst, LiftoffRegList{src1, src2, src3, dst},
4049 LiftoffRegister src1 = (src1_rc == src2_rc || pin_src2)
4055 ? __ GetUnusedRegister(result_rc, {src1}, LiftoffRegList{src2})
4056 : __ GetUnusedRegister(result_rc, {src1}, {});
4057 fn(dst, src1, src
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/third_party/ffmpeg/libavcodec/mips/
H A Dh264dsp_mmi.c1228 MMI_LDC1(%[ftmp1], %[src1], 0x00) in ff_h264_biweight_pixels16_8_mmi()
1253 [src0]"r"(src), [src1]"r"(src+8), in ff_h264_biweight_pixels16_8_mmi()
H A Dhevc_idct_msa.c437 int16_t *src1 = (coeffs + 2 * buf_pitch); in hevc_idct_8x32_column_msa() local
514 LD_SH8(src1, 4 * buf_pitch, in0, in1, in2, in3, in4, in5, in6, in7); in hevc_idct_8x32_column_msa()
H A Dqpeldsp_msa.c5773 uint64_t src0, src1; in copy_8x8_msa() local
5779 src1 = LD(src); in copy_8x8_msa()
5784 SD(src1, dst); in copy_8x8_msa()
5792 v16u8 src0, src1, src2, src3, src4, src5, src6, src7; in copy_16x16_msa() local
5795 LD_UB8(src, src_stride, src0, src1, src2, src3, src4, src5, src6, src7); in copy_16x16_msa()
5800 ST_UB8(src0, src1, src2, src3, src4, src5, src6, src7, dst, dst_stride); in copy_16x16_msa()
5812 v16u8 src0, src1, src2, src3; in avg_width8_msa() local
5816 LD_UB4(src, src_stride, src0, src1, src2, src3); in avg_width8_msa()
5820 AVER_UB4_UB(src0, dst0, src1, dst1, src2, dst2, src3, dst3, in avg_width8_msa()
5837 v16u8 src0, src1, src in avg_width16_msa() local
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/third_party/mesa3d/src/gallium/drivers/r600/sfn/
H A Dsfn_nir_lower_64bit.cpp567 auto src1 = nir_channels(b, src.ssa, 3); in split_store_output() local
570 nir_instr_rewrite_src(&store1->instr, &src, nir_src_for_ssa(src1)); in split_store_output()
/third_party/skia/src/core/
H A DSkGeometry.cpp905 const SkScalar src1[] = { 0, 0 };
917 { TEST_COLLAPS_ENTRY(src1), 1 },
/third_party/skia/third_party/externals/swiftshader/src/Shader/
H A DVertexPipeline.cpp937 Float4 VertexPipeline::power(Float4 &src0, Float4 &src1) in power() argument
945 dst *= src1; in power()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUInstPrinter.cpp615 AMDGPU::OpName::src1)) in printOperand()
676 AMDGPU::OpName::src1)) in printOperandAndIntInputMods()
877 // If compr is set, print as src0, src0, src1, src1 in printExpSrcN()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp2836 const int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1); in validateConstantBusLimitations()
2903 const int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1); in validateEarlyClobberLimitations()
3264 const int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1); in validateLdsDirect()
3269 // lds_direct cannot be specified as either src1 or src2. in validateLdsDirect()
3345 const int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1); in validateSOPLiteral()
3402 const int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1); in validateVOP3Literal()
6206 AMDGPU::OpName::src1,
6376 AMDGPU::OpName::src1,
6894 // Note that src0 and src1 occupy 2 slots each because of modifiers.
/third_party/ffmpeg/libswscale/ppc/
H A Dswscale_vsx.c1785 int dstWidth, const uint8_t *src1, in hcscale_fast_vsx()
1848 HCSCALE(src1, dst1); in hcscale_fast_vsx()
1854 dst1[i] = src1[srcW-1]*128; in hcscale_fast_vsx()
1784 hcscale_fast_vsx(SwsContext *c, int16_t *dst1, int16_t *dst2, int dstWidth, const uint8_t *src1, const uint8_t *src2, int srcW, int xInc) hcscale_fast_vsx() argument

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