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/third_party/ffmpeg/libswscale/
H A Drgb2rgb.c88 void (*interleaveBytes)(const uint8_t *src1, const uint8_t *src2, uint8_t *dst,
94 void (*vu9_to_vu12)(const uint8_t *src1, const uint8_t *src2,
99 void (*yvu9_to_yuy2)(const uint8_t *src1, const uint8_t *src2,
/third_party/mesa3d/src/gallium/drivers/vc4/
H A Dvc4_qir.h526 struct qreg src0, struct qreg src1);
715 qir_SEL(struct vc4_compile *c, uint8_t cond, struct qreg src0, struct qreg src1) in qir_SEL() argument
718 qir_MOV_dest(c, t, src1); in qir_SEL()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
H A DGCNDPPCombine.cpp15 // $res = VALU $dpp_value [, src1]
19 // $res = VALU_DPP $combined_old, $vgpr_to_be_read_from_other_lane, [src1,]
32 // -> $combined_old = src1,
230 if (auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1)) { in createDPPInst()
232 LLVM_DEBUG(dbgs() << " failed: src1 is illegal\n"); in createDPPInst()
323 auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1); in createDPPInst()
325 LLVM_DEBUG(dbgs() << " failed: no src1 or it isn't a register\n"); in createDPPInst()
334 LLVM_DEBUG(dbgs() << " failed: src1 isn't a VGPR32 register\n"); in createDPPInst()
517 Use == TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1)) { in combineDPPMov()
H A DSIFoldOperands.cpp204 else if (OpNo == AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1)) in updateOperand()
818 UseMI->RemoveOperand(2); // Remove exec read (or src1 for readlane) in foldOperand()
837 UseMI->RemoveOperand(2); // Remove exec read (or src1 for readlane) in foldOperand()
999 int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1); in tryConstantFoldOp()
1109 const MachineOperand *Src1 = TII->getNamedOperand(*MI, AMDGPU::OpName::src1); in tryFoldInst()
1121 MI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1)); in tryFoldInst()
1275 const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in isClamp()
1391 const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in isOMod()
1420 const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in isOMod()
/third_party/ffmpeg/libavcodec/
H A Ddcadsp.h85 void (*assemble_freq_bands)(int32_t *dst, int32_t *src0, int32_t *src1,
H A Dopusenc.c200 float *src1 = b->overlap; in celt_frame_mdct() local
203 s->dsp->vector_fmul(win, src1, ff_celt_window, 128); in celt_frame_mdct()
206 src1 = src2; in celt_frame_mdct()
/third_party/ffmpeg/libavfilter/x86/
H A Dscene_sad.asm31 cglobal scene_sad, 6, 7, 2, src1, stride1, src2, stride2, width, end, x
/third_party/mbedtls/library/
H A Dconstant_time_internal.h476 * memcpy(dest, src1, len);
482 * It will always read len bytes from src1.
488 * \param src1 Secret. Pointer to copy from (if \p condition == MBEDTLS_CT_TRUE).
492 * This may be equal to \p dest, but may not overlap it in other ways. It may overlap with \p src1.
497 const unsigned char *src1,
/third_party/mesa3d/src/gallium/drivers/zink/nir_to_spirv/
H A Dnir_to_spirv.c127 SpvId src0, SpvId src1);
131 SpvId src0, SpvId src1, SpvId src2);
1704 emit_atomic(struct ntv_context *ctx, SpvId op, SpvId type, SpvId src0, SpvId src1, SpvId src2) in emit_atomic() argument
1714 src2, src1); in emit_atomic()
1717 emit_uint_const(ctx, 32, 0), src1); in emit_atomic()
1722 SpvId src0, SpvId src1) in emit_binop()
1724 return spirv_builder_emit_binop(&ctx->builder, op, type, src0, src1); in emit_binop()
1729 SpvId src0, SpvId src1, SpvId src2) in emit_triop()
1731 return spirv_builder_emit_triop(&ctx->builder, op, type, src0, src1, src2); in emit_triop()
1745 SpvId src0, SpvId src1) in emit_builtin_binop()
1721 emit_binop(struct ntv_context *ctx, SpvOp op, SpvId type, SpvId src0, SpvId src1) emit_binop() argument
1728 emit_triop(struct ntv_context *ctx, SpvOp op, SpvId type, SpvId src0, SpvId src1, SpvId src2) emit_triop() argument
1744 emit_builtin_binop(struct ntv_context *ctx, enum GLSLstd450 op, SpvId type, SpvId src0, SpvId src1) emit_builtin_binop() argument
1753 emit_builtin_triop(struct ntv_context *ctx, enum GLSLstd450 op, SpvId type, SpvId src0, SpvId src1, SpvId src2) emit_builtin_triop() argument
2623 SpvId src1 = 0; emit_interpolate() local
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/third_party/mesa3d/src/amd/llvm/
H A Dac_nir_to_llvm.c151 LLVMValueRef src0, LLVMValueRef src1) in emit_int_cmp()
154 src1 = ac_to_integer(ctx, src1); in emit_int_cmp()
155 return LLVMBuildICmp(ctx->builder, pred, src0, src1, ""); in emit_int_cmp()
159 LLVMValueRef src0, LLVMValueRef src1) in emit_float_cmp()
162 src1 = ac_to_float(ctx, src1); in emit_float_cmp()
163 return LLVMBuildFCmp(ctx->builder, pred, src0, src1, ""); in emit_float_cmp()
209 LLVMValueRef src1) in emit_intrin_2f_param()
214 ac_to_float(ctx, src1), in emit_intrin_2f_param()
150 emit_int_cmp(struct ac_llvm_context *ctx, LLVMIntPredicate pred, LLVMValueRef src0, LLVMValueRef src1) emit_int_cmp() argument
158 emit_float_cmp(struct ac_llvm_context *ctx, LLVMRealPredicate pred, LLVMValueRef src0, LLVMValueRef src1) emit_float_cmp() argument
207 emit_intrin_2f_param(struct ac_llvm_context *ctx, const char *intrin, LLVMTypeRef result_type, LLVMValueRef src0, LLVMValueRef src1) emit_intrin_2f_param() argument
223 emit_intrin_3f_param(struct ac_llvm_context *ctx, const char *intrin, LLVMTypeRef result_type, LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2) emit_intrin_3f_param() argument
240 emit_bcsel(struct ac_llvm_context *ctx, LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2) emit_bcsel() argument
263 emit_uint_carry(struct ac_llvm_context *ctx, const char *intrin, LLVMValueRef src0, LLVMValueRef src1) emit_uint_carry() argument
374 emit_umul_high(struct ac_llvm_context *ctx, LLVMValueRef src0, LLVMValueRef src1) emit_umul_high() argument
387 emit_imul_high(struct ac_llvm_context *ctx, LLVMValueRef src0, LLVMValueRef src1) emit_imul_high() argument
3185 LLVMValueRef src1 = get_src(ctx, instr->src[src_idx + 1]); visit_var_atomic() local
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/base/telephony/ril_adapter/services/vendor/src/
H A Dat_data.c441 static int32_t IsStrEqual(const char *src1, const char *src2) in IsStrEqual() argument
444 if (IsStrEmpty(src1) && IsStrEmpty(src2)) { in IsStrEqual()
446 } else if (!IsStrEmpty(src1) && !IsStrEmpty(src2)) { in IsStrEqual()
447 if (strcasecmp(src1, src2) == 0) { in IsStrEqual()
450 TELEPHONY_LOGE("IsStrEqual src1=%{public}s, src2=%{public}s", src1, src2); in IsStrEqual()
453 TELEPHONY_LOGE("IsStrEqual src1 or src2 is empty!"); in IsStrEqual()
/third_party/mesa3d/src/gallium/drivers/etnaviv/
H A Detnaviv_compiler_nir.c516 nir_src *coord = NULL, *src1 = NULL, *src2 = NULL; in emit_tex() local
526 assert(!src1); in emit_tex()
527 src1 = &tex->src[i].src; in emit_tex()
541 src1 ? get_src(c, src1) : SRC_DISABLE, in emit_tex()
/third_party/vixl/src/aarch64/
H A Dmacro-assembler-aarch64.cc2196 const CPURegister& src1, in Emit()
2200 VIXL_ASSERT(AreSameSizeAndType(src0, src1, src2, src3)); in Emit()
2203 int count = 1 + src1.IsValid() + src2.IsValid() + src3.IsValid(); in Emit()
2207 PushHelper(count, size, src0, src1, src2, src3); in Emit()
2251 const CPURegister& src1 = registers.PopLowestIndex(); in Emit() local
2252 if (src1.IsValid()) { in Emit()
2253 Stp(src0, src1, MemOperand(StackPointer(), offset)); in Emit()
2323 const CPURegister& src1, in Emit()
2332 VIXL_ASSERT(AreSameSizeAndType(src0, src1, src2, src3)); in Emit()
2339 VIXL_ASSERT(src1 in Emit()
2195 Push(const CPURegister& src0, const CPURegister& src1, const CPURegister& src2, const CPURegister& src3) Emit() argument
2320 PushHelper(int count, int size, const CPURegister& src0, const CPURegister& src1, const CPURegister& src2, const CPURegister& src3) Emit() argument
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/third_party/node/deps/v8/src/codegen/riscv64/
H A Dmacro-assembler-riscv64.cc102 Condition cond, Register src1, in LoadRoot()
105 BranchShort(&skip, NegateCondition(cond), src1, src2); in LoadRoot()
3650 void TurboAssembler::MovToFloatParameters(DoubleRegister src1, in MovToFloatParameters() argument
3654 DCHECK(src1 != fparg2); in MovToFloatParameters()
3656 Move(fa0, src1); in MovToFloatParameters()
3658 Move(fa0, src1); in MovToFloatParameters()
4709 void TurboAssembler::FloatMinMaxHelper(FPURegister dst, FPURegister src1, in FloatMinMaxHelper() argument
4714 if (src1 == src2 && dst != src1) { in FloatMinMaxHelper()
4716 fmv_s(dst, src1); in FloatMinMaxHelper()
101 LoadRoot(Register destination, RootIndex index, Condition cond, Register src1, const Operand& src2) LoadRoot() argument
4764 Float32Max(FPURegister dst, FPURegister src1, FPURegister src2) Float32Max() argument
4770 Float32Min(FPURegister dst, FPURegister src1, FPURegister src2) Float32Min() argument
4776 Float64Max(FPURegister dst, FPURegister src1, FPURegister src2) Float64Max() argument
4782 Float64Min(FPURegister dst, FPURegister src1, FPURegister src2) Float64Min() argument
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/third_party/mesa3d/src/microsoft/compiler/
H A Ddxil_nir_lower_vs_vertex_conversion.c52 (*shift_right_func)(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1);
/third_party/ltp/tools/sparse/sparse-src/
H A Dir.c139 err += check_user(insn, insn->src1); in validate_insn()
/third_party/node/deps/v8/src/wasm/baseline/mips/
H A Dliftoff-assembler-mips.h1228 Register src1 = src.high_gp() == dst.low_gp() ? src.high_gp() : src.low_gp(); in emit_i64_popcnt() local
1230 TurboAssembler::Popcnt(dst.low_gp(), src1); in emit_i64_popcnt()
1869 LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) { \
1871 MSARegister src1_msa = MSARegister::from_code(src1.liftoff_code()); \
1897 LiftoffRegister src1, in emit_i16x8_q15mulr_sat_s()
2078 LiftoffRegister src1, in emit_s128_select()
2853 LiftoffRegister src1, in emit_i8x16_replace_lane()
2860 LiftoffRegister src1, in emit_i16x8_replace_lane()
2867 LiftoffRegister src1, in emit_i32x4_replace_lane()
2874 LiftoffRegister src1, in emit_i64x2_replace_lane()
1896 emit_i16x8_q15mulr_sat_s(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i16x8_q15mulr_sat_s() argument
2077 emit_s128_select(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, LiftoffRegister mask) emit_s128_select() argument
2852 emit_i8x16_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_i8x16_replace_lane() argument
2859 emit_i16x8_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_i16x8_replace_lane() argument
2866 emit_i32x4_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_i32x4_replace_lane() argument
2873 emit_i64x2_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_i64x2_replace_lane() argument
2880 emit_f32x4_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_f32x4_replace_lane() argument
2887 emit_f64x2_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_f64x2_replace_lane() argument
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/third_party/ffmpeg/libavresample/
H A Ddither.c115 int *src1 = src0 + len; in dither_int_to_float_triangular_c() local
119 r += src1[i] * LFG_SCALE; in dither_int_to_float_triangular_c()
/third_party/ffmpeg/libswscale/tests/
H A Dswscale.c58 static uint64_t getSSD(const uint8_t *src1, const uint8_t *src2, in getSSD() argument
66 int d = src1[x + y * stride1] - src2[x + y * stride2]; in getSSD()
/third_party/mesa3d/src/intel/compiler/
H A Dbrw_ir_fs.h343 const fs_reg &src0, const fs_reg &src1);
345 const fs_reg &src0, const fs_reg &src1, const fs_reg &src2);
/third_party/mesa3d/src/gallium/drivers/llvmpipe/
H A Dlp_state_fs_linear_llvm.c215 LLVMValueRef src1 = lp_build_zero(gallivm, fs_type); in llvm_fragment_body() local
224 src1, /* src1 */ in llvm_fragment_body()
/third_party/mesa3d/src/panfrost/midgard/
H A Dmidgard.h316 unsigned src1 : 13; member
337 unsigned src1 : 6; member
/third_party/mesa3d/src/gallium/frontends/nine/
H A Dnine_shader.c828 struct ureg_src src1, INT idx) in TEX_if_fetch4()
831 struct ureg_src src_tg4[3] = {src0, ureg_imm1f(tx->ureg, 0.f), src1}; in TEX_if_fetch4()
873 struct ureg_src src1, INT idx) in TEX_with_ps1x_projection()
884 ureg_TEX(tx->ureg, dst, target, src0, src1); in TEX_with_ps1x_projection()
886 ureg_TXP(tx->ureg, dst, target, src0, src1); in TEX_with_ps1x_projection()
890 ureg_TEX(tx->ureg, dst, target, ureg_src(tmp), src1); in TEX_with_ps1x_projection()
1659 struct ureg_src src1 = tx_src_param(tx, &tx->insn.src[1]); in DECL_SPECIAL() local
1661 ureg_ADD(ureg, dst, src0, ureg_negate(src1)); in DECL_SPECIAL()
1680 struct ureg_src src1 = tx_src_param(tx, &tx->insn.src[1]); in DECL_SPECIAL() local
1685 ureg_swizzle(src1, TGSI_SWIZZLE_ in DECL_SPECIAL()
826 TEX_if_fetch4(struct shader_translator *tx, struct ureg_dst dst, unsigned target, struct ureg_src src0, struct ureg_src src1, INT idx) TEX_if_fetch4() argument
871 TEX_with_ps1x_projection(struct shader_translator *tx, struct ureg_dst dst, unsigned target, struct ureg_src src0, struct ureg_src src1, INT idx) TEX_with_ps1x_projection() argument
2906 struct ureg_src src1 = tx_src_param(tx, &tx->insn.src[1]); DECL_SPECIAL() local
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/third_party/mesa3d/src/gallium/auxiliary/nir/
H A Dnir_to_tgsi.c135 struct ureg_src src0, struct ureg_src src1, in ntt_insn()
141 .src = { src0, src1, src2, src3 }, in ntt_insn()
181 struct ureg_src src1) \
183 ntt_insn(c, TGSI_OPCODE_##op, dst, src0, src1, ureg_src_undef(), ureg_src_undef()); \
190 struct ureg_src src1, \
193 ntt_insn(c, TGSI_OPCODE_##op, dst, src0, src1, src2, ureg_src_undef()); \
200 struct ureg_src src1, \
204 ntt_insn(c, TGSI_OPCODE_##op, dst, src0, src1, src2, src3); \
1298 struct ureg_src src1) in ntt_emit_scalar()
1304 src1 in ntt_emit_scalar()
133 ntt_insn(struct ntt_compile *c, enum tgsi_opcode opcode, struct ureg_dst dst, struct ureg_src src0, struct ureg_src src1, struct ureg_src src2, struct ureg_src src3) ntt_insn() argument
1295 ntt_emit_scalar(struct ntt_compile *c, unsigned tgsi_op, struct ureg_dst dst, struct ureg_src src0, struct ureg_src src1) ntt_emit_scalar() argument
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/third_party/ffmpeg/libavutil/arm/
H A Dfloat_dsp_vfp.S27 @ void ff_vector_fmul_vfp(float *dst, const float *src0, const float *src1, int len)
75 @ const float *src1, const float *win, int len)
279 @ const float *src1, int len)

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