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/third_party/ffmpeg/libavcodec/x86/
H A Dqpeldsp_init.c35 const uint8_t *src1, const uint8_t *src2,
38 const uint8_t *src1, const uint8_t *src2,
41 const uint8_t *src1, const uint8_t *src2,
44 const uint8_t *src1, const uint8_t *src2,
47 const uint8_t *src1, const uint8_t *src2,
50 const uint8_t *src1, const uint8_t *src2,
H A Dexrdsp.asm39 cglobal reorder_pixels, 3,4,3, dst, src1, size, src2
44 neg sizeq ; size = offset for dst, src1, src2
H A Daacpsdsp_init.c32 float *src1, int n);
/third_party/ffmpeg/libavresample/x86/
H A Daudio_mix.asm33 cglobal mix_2_to_1_fltp_flt, 3,4,6, src, matrix, len, src1
69 cglobal mix_2_to_1_s16p_flt, 3,4,6, src, matrix, len, src1
113 cglobal mix_2_to_1_s16p_q8, 3,4,6, src, matrix, len, src1
154 cglobal mix_1_to_2_fltp_flt, 3,5,4, src0, matrix0, len, src1, matrix1
188 cglobal mix_1_to_2_s16p_flt, 3,5,6, src0, matrix0, len, src1, matrix1
276 cglobal mix_%1_to_%2_%3_flt, 3,in_channels+2,needed_mmregs+matrix_elements_mm, needed_stack_size, src0, src1, len, src2, src3, src4, src5, src6, src7
/third_party/pcre2/pcre2/src/sljit/
H A DsljitLir.h1158 sljit_s32 src1, sljit_sw src1w,
1165 sljit_s32 src1, sljit_sw src1w,
1178 src_dst |= ((src1 >> 1) >> (src2 ^ value_mask))
1184 src_dst |= ((src1 << 1) << (src2 ^ value_mask))
1193 src1 / src1w contains the bits which shifted into src_dst
1197 src1 are set to the same register
1208 sljit_s32 src1, sljit_sw src1w,
1306 sljit_s32 src1, sljit_sw src1w,
1445 sljit_s32 src1, sljit_sw src1w,
1458 sljit_s32 src1, sljit_s
[all...]
/third_party/ffmpeg/libavcodec/arm/
H A Daacpsdsp_init_arm.c29 float *src1, int n);
H A Dvp9mc_neon.S209 @ Extract a vector from src1-src2 and src4-src5 (src1-src3 and src4-src6
212 .macro extmla dst1, dst2, dst3, dst4, dst1d, dst3d, src1, src2, src3, src4, src5, src6, offset, size
213 vext.8 q14, \src1, \src2, #(2*\offset)
232 .macro extmulqadd dst1, dst2, dst3, dst4, dst1d, dst3d, src1, src2, src3, src4, src5, src6, offset, size
233 vext.8 q14, \src1, \src2, #(2*\offset)
493 @ Evaluate the filter twice in parallel, from the inputs src1-src9 into dst1-dst2
494 @ (src1-src8 into dst1, src2-src9 into dst2), adding idx2 separately
498 .macro convolve dst1, dst2, src1, src2, src3, src4, src5, src6, src7, src8, src9, idx1, idx2, tmp1, tmp2
501 vmul.s16 \tmp1, \src1, d
[all...]
/third_party/ffmpeg/libavfilter/
H A Dframerate.h25 #define BLEND_FUNC_PARAMS const uint8_t *src1, ptrdiff_t src1_linesize, \
/third_party/mesa3d/src/nouveau/codegen/
H A Dnv50_ir_peephole.cpp416 ImmediateValue src0, src1, src2; in visit() local
420 i->src(1).getImmediate(src1) && in visit()
422 expr(i, src0, src1, src2); in visit()
425 i->src(0).getImmediate(src0) && i->src(1).getImmediate(src1)) { in visit()
426 expr(i, src0, src1); in visit()
432 if (i->srcExists(1) && i->src(1).getImmediate(src1)) { in visit()
433 if (opnd(i, src1, 1)) in visit()
756 ImmediateValue src0, src1 = *i->getSrc(0)->asImm(); in expr() local
770 expr(i, src0, src1); in expr()
772 opnd(i, src1, in expr()
1849 Value *src1 = sub->getSrc(1); handleABS() local
1877 Value *src1 = add->getSrc(1); handleADD() local
1897 Value *src1 = add->getSrc(1); tryADDToMADOrSAD() local
1963 Value *src1 = minmax->getSrc(1); handleMINMAX() local
2026 Value *src1 = logop->getSrc(1); handleLOGOP() local
2444 Value *src1 = add->getSrc(1); handleADD() local
2458 Value *src1 = add->getSrc(1); tryADDToSHLADD() local
[all...]
/third_party/node/deps/v8/src/codegen/ppc/
H A Dmacro-assembler-ppc.cc2274 void TurboAssembler::MovToFloatParameters(DoubleRegister src1, in CallRecordWriteStub() argument
2277 DCHECK(src1 != d2); in CallRecordWriteStub()
2279 Move(d1, src1); in CallRecordWriteStub()
2281 Move(d1, src1); in CallRecordWriteStub()
2997 void TurboAssembler::CmpS64(Register src1, Register src2, CRegister cr) { in CallRecordWriteStub() argument
2998 cmp(src1, src2, cr); in CallRecordWriteStub()
3001 void TurboAssembler::CmpS64(Register src1, const Operand& src2, in CallRecordWriteStub() argument
3005 cmpi(src1, src2, cr); in CallRecordWriteStub()
3008 CmpS64(src1, scratch, cr); in CallRecordWriteStub()
3012 void TurboAssembler::CmpU64(Register src1, cons in CallRecordWriteStub() argument
3023 CmpU64(Register src1, Register src2, CRegister cr) CallRecordWriteStub() argument
3027 CmpS32(Register src1, const Operand& src2, Register scratch, CRegister cr) CallRecordWriteStub() argument
3038 CmpS32(Register src1, Register src2, CRegister cr) CallRecordWriteStub() argument
3042 CmpU32(Register src1, const Operand& src2, Register scratch, CRegister cr) CallRecordWriteStub() argument
3053 CmpU32(Register src1, Register src2, CRegister cr) CallRecordWriteStub() argument
3106 CmpSmiLiteral(Register src1, Smi smi, Register scratch, CRegister cr) CallRecordWriteStub() argument
3116 CmplSmiLiteral(Register src1, Smi smi, Register scratch, CRegister cr) CallRecordWriteStub() argument
[all...]
/foundation/graphic/graphic_2d/rosen/test/render_service/render_service_base/unittest/render/
H A Drs_foreground_effect_filter_test.cpp120 Drawing::Rect src1; in HWTEST_F() local
122 ForegroundEffectParam param(src1, dst2); in HWTEST_F()
/third_party/ffmpeg/libavcodec/mips/
H A Daacpsdsp_mips.c245 static void ps_mul_pair_single_mips(float (*dst)[2], float (*src0)[2], float *src1, in ps_mul_pair_single_mips() argument
252 p_s1 = &src1[0]; in ps_mul_pair_single_mips()
/third_party/mesa3d/src/gallium/drivers/r600/sfn/
H A Dsfn_instrfactory.cpp150 auto src1 = m_value_factory.literal((literal->value[i].u64 >> 32) & 0xffffffff); in load_const() local
151 shader.emit_instruction(new AluInstr(op1_mov, dest1, src1, AluInstr::last_write)); in load_const()
/third_party/node/deps/openssl/openssl/crypto/perlasm/
H A Dx86asm.pl151 my ($dst,$src1,$src2,$rxb)=@_;
155 $rxb&=~(0x01<<5) if($src1>=8);
/third_party/openssl/crypto/perlasm/
H A Dx86asm.pl151 my ($dst,$src1,$src2,$rxb)=@_;
155 $rxb&=~(0x01<<5) if($src1>=8);
/third_party/ffmpeg/libavcodec/
H A Dme_cmp.c665 static int dct_sad8x8_c(MpegEncContext *s, uint8_t *src1, in dct_sad8x8_c() argument
672 s->pdsp.diff_pixels_unaligned(temp, src1, src2, stride); in dct_sad8x8_c()
706 static int dct264_sad8x8_c(MpegEncContext *s, uint8_t *src1, in dct264_sad8x8_c() argument
712 s->pdsp.diff_pixels_unaligned(dct[0], src1, src2, stride); in dct264_sad8x8_c()
731 static int dct_max8x8_c(MpegEncContext *s, uint8_t *src1, in dct_max8x8_c() argument
739 s->pdsp.diff_pixels_unaligned(temp, src1, src2, stride); in dct_max8x8_c()
748 static int quant_psnr8x8_c(MpegEncContext *s, uint8_t *src1, in quant_psnr8x8_c() argument
758 s->pdsp.diff_pixels_unaligned(temp, src1, src2, stride); in quant_psnr8x8_c()
773 static int rd8x8_c(MpegEncContext *s, uint8_t *src1, uint8_t *src2, in rd8x8_c() argument
786 copy_block8(lsrc1, src1, in rd8x8_c()
850 bit8x8_c(MpegEncContext *s, uint8_t *src1, uint8_t *src2, ptrdiff_t stride, int h) bit8x8_c() argument
[all...]
H A Daacpsdsp.h34 void (*mul_pair_single)(INTFLOAT (*dst)[2], INTFLOAT (*src0)[2], INTFLOAT *src1,
H A Dsbrdsp.h35 void (*qmf_deint_bfly)(INTFLOAT *v, const INTFLOAT *src0, const INTFLOAT *src1);
H A Drv34dsp.h34 uint8_t *src1/*align width (8 or 16)*/,
/third_party/node/deps/v8/src/codegen/arm64/
H A Dmacro-assembler-arm64-inl.h1137 void TurboAssembler::Push(const CPURegister& src0, const CPURegister& src1, in Push() argument
1139 DCHECK(AreSameSizeAndType(src0, src1, src2, src3)); in Push()
1140 DCHECK_IMPLIES((lr_mode == kSignLR), ((src0 == lr) || (src1 == lr) || in Push()
1142 DCHECK_IMPLIES((lr_mode == kDontStoreLR), ((src0 != lr) && (src1 != lr) && in Push()
1151 int count = 1 + src1.is_valid() + src2.is_valid() + src3.is_valid(); in Push()
1155 PushHelper(count, size, src0, src1, src2, src3); in Push()
1159 void TurboAssembler::Push(const Register& src0, const VRegister& src1) { in Push() argument
1160 DCHECK_IMPLIES((lr_mode == kSignLR), ((src0 == lr) || (src1 == lr))); in Push()
1161 DCHECK_IMPLIES((lr_mode == kDontStoreLR), ((src0 != lr) && (src1 != lr))); in Push()
1168 int size = src0.SizeInBytes() + src1 in Push()
[all...]
/third_party/vk-gl-cts/framework/referencerenderer/
H A DrrFragmentOperations.cpp367 const Vec4& src1 = m_sampleRegister[regSampleNdx].clampedBlendSrc1Color; \ in executeBlendFactorComputeRGB()
370 DE_UNREF(src1); \ in executeBlendFactorComputeRGB()
395 case BLENDFUNC_SRC1_COLOR: SAMPLE_REGISTER_BLEND_FACTOR(FACTOR_NAME, src1.swizzle(0,1,2)) break; \ in executeBlendFactorComputeRGB()
396 case BLENDFUNC_ONE_MINUS_SRC1_COLOR: SAMPLE_REGISTER_BLEND_FACTOR(FACTOR_NAME, Vec3(1.0f) - src1.swizzle(0,1,2)) break; \ in executeBlendFactorComputeRGB()
397 case BLENDFUNC_SRC1_ALPHA: SAMPLE_REGISTER_BLEND_FACTOR(FACTOR_NAME, Vec3(src1.w())) break; \ in executeBlendFactorComputeRGB()
398 case BLENDFUNC_ONE_MINUS_SRC1_ALPHA: SAMPLE_REGISTER_BLEND_FACTOR(FACTOR_NAME, Vec3(1.0f - src1.w())) break; \ in executeBlendFactorComputeRGB()
418 const Vec4& src1 = m_sampleRegister[regSampleNdx].clampedBlendSrc1Color; \ in executeBlendFactorComputeA()
421 DE_UNREF(src1); \ in executeBlendFactorComputeA()
446 case BLENDFUNC_SRC1_COLOR: SAMPLE_REGISTER_BLEND_FACTOR(FACTOR_NAME, src1.w()) break; \ in executeBlendFactorComputeA()
447 case BLENDFUNC_ONE_MINUS_SRC1_COLOR: SAMPLE_REGISTER_BLEND_FACTOR(FACTOR_NAME, 1.0f - src1 in executeBlendFactorComputeA()
[all...]
/third_party/node/deps/v8/src/compiler/backend/arm64/
H A Dcode-generator-arm64.cc2252 src1 = i.InputSimd128Register(0).Format(f); in AssembleArchInstruction() local
2253 if (dst != src1) { in AssembleArchInstruction()
2254 __ Mov(dst, src1); in AssembleArchInstruction()
2345 src1 = i.InputSimd128Register(0).Format(f); in AssembleArchInstruction() local
2348 if (dst != src1) { in AssembleArchInstruction()
2349 __ Mov(dst, src1); in AssembleArchInstruction()
2367 VRegister src1 = i.InputSimd128Register(0); in AssembleArchInstruction() local
2386 // `src1` and `src2` are split up into 32-bit components: in AssembleArchInstruction()
2387 // src1 = |d|c|b|a| in AssembleArchInstruction()
2390 // src1 * src in AssembleArchInstruction()
2515 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
2536 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
2577 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
2595 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
[all...]
/third_party/node/deps/v8/src/wasm/baseline/ppc/
H A Dliftoff-assembler-ppc.h1788 LiftoffRegister src1, in emit_f64x2_replace_lane()
1900 LiftoffRegister src1, in emit_f32x4_replace_lane()
1997 LiftoffRegister src1, in emit_i64x2_replace_lane()
2061 LiftoffRegister src1, in emit_i64x2_extmul_low_i32x4_s()
2067 LiftoffRegister src1, in emit_i64x2_extmul_low_i32x4_u()
2073 LiftoffRegister src1, in emit_i64x2_extmul_high_i32x4_s()
2104 LiftoffRegister src1, in emit_i64x2_extmul_high_i32x4_u()
2121 LiftoffRegister src1, in emit_i32x4_replace_lane()
2230 LiftoffRegister src1, in emit_i32x4_extmul_low_i16x8_s()
2236 LiftoffRegister src1, in emit_i32x4_extmul_low_i16x8_u()
1787 emit_f64x2_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_f64x2_replace_lane() argument
1899 emit_f32x4_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_f32x4_replace_lane() argument
1996 emit_i64x2_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_i64x2_replace_lane() argument
2060 emit_i64x2_extmul_low_i32x4_s(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i64x2_extmul_low_i32x4_s() argument
2066 emit_i64x2_extmul_low_i32x4_u(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i64x2_extmul_low_i32x4_u() argument
2072 emit_i64x2_extmul_high_i32x4_s(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i64x2_extmul_high_i32x4_s() argument
2103 emit_i64x2_extmul_high_i32x4_u(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i64x2_extmul_high_i32x4_u() argument
2120 emit_i32x4_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_i32x4_replace_lane() argument
2229 emit_i32x4_extmul_low_i16x8_s(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i32x4_extmul_low_i16x8_s() argument
2235 emit_i32x4_extmul_low_i16x8_u(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i32x4_extmul_low_i16x8_u() argument
2241 emit_i32x4_extmul_high_i16x8_s(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i32x4_extmul_high_i16x8_s() argument
2247 emit_i32x4_extmul_high_i16x8_u(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i32x4_extmul_high_i16x8_u() argument
2374 emit_i16x8_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_i16x8_replace_lane() argument
2397 emit_i16x8_extmul_low_i8x16_s(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i16x8_extmul_low_i8x16_s() argument
2403 emit_i16x8_extmul_low_i8x16_u(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i16x8_extmul_low_i8x16_u() argument
2409 emit_i16x8_extmul_high_i8x16_s(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i16x8_extmul_high_i8x16_s() argument
2415 emit_i16x8_q15mulr_sat_s(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i16x8_q15mulr_sat_s() argument
2421 emit_i16x8_extmul_high_i8x16_u(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2) emit_i16x8_extmul_high_i8x16_u() argument
2451 emit_i8x16_replace_lane(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, uint8_t imm_lane_idx) emit_i8x16_replace_lane() argument
2725 emit_s128_select(LiftoffRegister dst, LiftoffRegister src1, LiftoffRegister src2, LiftoffRegister mask) emit_s128_select() argument
[all...]
/third_party/mesa3d/src/freedreno/afuc/
H A Dasm.h42 int src1; member
/third_party/mesa3d/src/gallium/drivers/llvmpipe/
H A Dlp_bld_blend.h65 LLVMValueRef src1,

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