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/third_party/ffmpeg/libavfilter/
H A Dcolorspace.c55 const double src1[3][3], const double src2[3][3]) in ff_matrix_mul_3x3()
61 dst[m][n] = src2[m][0] * src1[0][n] + in ff_matrix_mul_3x3()
62 src2[m][1] * src1[1][n] + in ff_matrix_mul_3x3()
63 src2[m][2] * src1[2][n]; in ff_matrix_mul_3x3()
54 ff_matrix_mul_3x3(double dst[3][3], const double src1[3][3], const double src2[3][3]) ff_matrix_mul_3x3() argument
H A Dvf_framerate.c99 AVFrame *src1 = td->copy_src1; in filter_slice() local
105 for (plane = 0; plane < 4 && src1->data[plane] && src2->data[plane]; plane++) { in filter_slice()
108 uint8_t *src1_data = src1->data[plane] + start * src1->linesize[plane]; in filter_slice()
112 s->blend(src1_data, src1->linesize[plane], src2_data, src2->linesize[plane], in filter_slice()
238 uint##nbits##_t *src1w = (uint##nbits##_t *)src1; \
/third_party/node/deps/v8/src/compiler/backend/mips64/
H A Dcode-generator-mips64.cc220 ool_name(CodeGenerator* gen, T dst, T src1, T src2) \
221 : OutOfLineCode(gen), dst_(dst), src1_(src1), src2_(src2) {} \
1364 FPURegister src1 = i.InputSingleRegister(0); in AssembleArchInstruction() local
1366 auto ool = zone()->New<OutOfLineFloat32Max>(this, dst, src1, src2); in AssembleArchInstruction()
1367 __ Float32Max(dst, src1, src2, ool->entry()); in AssembleArchInstruction()
1373 FPURegister src1 = i.InputDoubleRegister(0); in AssembleArchInstruction() local
1375 auto ool = zone()->New<OutOfLineFloat64Max>(this, dst, src1, src2); in AssembleArchInstruction()
1376 __ Float64Max(dst, src1, src2, ool->entry()); in AssembleArchInstruction()
1382 FPURegister src1 = i.InputSingleRegister(0); in AssembleArchInstruction() local
1384 auto ool = zone()->New<OutOfLineFloat32Min>(this, dst, src1, src in AssembleArchInstruction()
1391 FPURegister src1 = i.InputDoubleRegister(0); AssembleArchInstruction() local
2137 Simd128Register src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
2160 Simd128Register src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
2593 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
2646 Simd128Register src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
2669 Simd128Register src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3360 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3370 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3380 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3390 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3400 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3410 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3420 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3474 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3484 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3494 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3504 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3514 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3524 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3548 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3558 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3568 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3578 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3588 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3598 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3615 src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3725 Simd128Register src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3735 Simd128Register src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3762 Simd128Register src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
3772 Simd128Register src1 = i.InputSimd128Register(1); AssembleArchInstruction() local
[all...]
/third_party/mesa3d/src/gallium/drivers/lima/ir/pp/
H A Dlower.c201 ppir_src *src1 = &alu->src[1]; in ppir_lower_select() local
225 /* src1 could also be a reference from the same node as in ppir_lower_select()
227 if (src1->node && src1->node == cond) in ppir_lower_select()
228 ppir_node_target_assign(src1, cond); in ppir_lower_select()
265 /* src1 could also be a reference from the same node as in ppir_lower_select()
267 if (src1->node && src1->node == pred) in ppir_lower_select()
268 ppir_node_target_assign(src1, move); in ppir_lower_select()
/third_party/ffmpeg/libavcodec/x86/
H A Dcavsidct.asm35 mova m5, [%1+1*16] ; m5 = src1
48 paddw m3, m3 ; m3 = 2*src1
52 paddw m5, m3 ; m5 = 3*src1
55 psubw m5, m4 ; m5 = 3*src1 - 2*src7 = a0
58 paddw m3, m0 ; m3 = 2*src1 - 3*src7 = a3
H A Dhuffyuvencdsp.asm33 ; void ff_diff_int16(uint8_t *dst, const uint8_t *src1, const uint8_t *src2,
38 cglobal diff_int16, 5,5,5, dst, src1, src2, mask, w, tmp
59 cglobal sub_hfyu_median_pred_int16, 7,7,0, dst, src1, src2, mask, w, left, left_top
/third_party/mesa3d/src/compiler/nir/
H A Dnir_opt_uniform_atomics.c114 nir_ssa_scalar src1 = nir_ssa_scalar_chase_alu_src(scalar, 1); in get_dim() local
119 unsigned src1_dim = get_dim(src1); in get_dim()
120 if (!src1_dim && src1.def->divergent) in get_dim()
126 nir_ssa_scalar src1 = nir_ssa_scalar_chase_alu_src(scalar, 1); in get_dim() local
127 return src1.def->divergent ? 0 : get_dim(src0); in get_dim()
/third_party/mesa3d/src/gallium/drivers/r600/sfn/tests/
H A Dsfn_valuefactory_test.cpp76 nir_src src1 = NIR_SRC_INIT; in TEST_F() local
77 src1.reg.reg = nir_local_reg_create(b.impl); in TEST_F()
78 src1.reg.reg->num_components = 1; in TEST_F()
83 ASSERT_FALSE(src1.is_ssa); in TEST_F()
87 auto value = factory->src(src1, 0); in TEST_F()
H A Dsfn_instr_test.cpp127 auto src1 = alu.psrc(1); in TEST_F() local
128 ASSERT_TRUE(src1); in TEST_F()
130 EXPECT_EQ(src1->sel(), 129); in TEST_F()
131 EXPECT_EQ(src1->chan(), 3); in TEST_F()
132 EXPECT_EQ(src1->pin(), pin_none); in TEST_F()
171 auto src1 = alu.psrc(1); in TEST_F() local
172 ASSERT_TRUE(src1); in TEST_F()
174 EXPECT_EQ(src1->sel(), 129); in TEST_F()
175 EXPECT_EQ(src1->chan(), 3); in TEST_F()
176 EXPECT_EQ(src1 in TEST_F()
[all...]
/third_party/pcre2/pcre2/src/sljit/
H A DsljitNativeARM_64.c1421 sljit_s32 src1, sljit_sw src1w, in sljit_emit_op2()
1427 CHECK(check_sljit_emit_op2(compiler, op, 0, dst, dstw, src1, src1w, src2, src2w)); in sljit_emit_op2()
1429 ADJUST_LOCAL_OFFSET(src1, src1w); in sljit_emit_op2()
1444 if (src1 & SLJIT_MEM) { in sljit_emit_op2()
1445 FAIL_IF(emit_op_mem(compiler, mem_flags, TMP_REG1, src1, src1w, TMP_REG1)); in sljit_emit_op2()
1446 src1 = TMP_REG1; in sljit_emit_op2()
1454 if (src1 & SLJIT_IMM) in sljit_emit_op2()
1457 src1w = src1; in sljit_emit_op2()
1472 sljit_s32 src1, sljit_sw src1w, in sljit_emit_op2u()
1476 CHECK(check_sljit_emit_op2(compiler, op, 1, 0, 0, src1, src1 in sljit_emit_op2u()
1419 sljit_emit_op2(struct sljit_compiler *compiler, sljit_s32 op, sljit_s32 dst, sljit_sw dstw, sljit_s32 src1, sljit_sw src1w, sljit_s32 src2, sljit_sw src2w) sljit_emit_op2() argument
1471 sljit_emit_op2u(struct sljit_compiler *compiler, sljit_s32 op, sljit_s32 src1, sljit_sw src1w, sljit_s32 src2, sljit_sw src2w) sljit_emit_op2u() argument
1482 sljit_emit_shift_into(struct sljit_compiler *compiler, sljit_s32 op, sljit_s32 src_dst, sljit_s32 src1, sljit_sw src1w, sljit_s32 src2, sljit_sw src2w) sljit_emit_shift_into() argument
1721 sljit_emit_fop1_cmp(struct sljit_compiler *compiler, sljit_s32 op, sljit_s32 src1, sljit_sw src1w, sljit_s32 src2, sljit_sw src2w) sljit_emit_fop1_cmp() argument
1786 sljit_emit_fop2(struct sljit_compiler *compiler, sljit_s32 op, sljit_s32 dst, sljit_sw dstw, sljit_s32 src1, sljit_sw src1w, sljit_s32 src2, sljit_sw src2w) sljit_emit_fop2() argument
[all...]
/third_party/ffmpeg/libswscale/x86/
H A Drgb2rgb_template.c1746 static void RENAME(interleaveBytes)(const uint8_t *src1, const uint8_t *src2, uint8_t *dest, in interleaveBytes() argument
1756 if (!((((intptr_t)src1) | ((intptr_t)src2) | ((intptr_t)dest))&15)) { in interleaveBytes()
1772 ::"r"(dest), "r"(src1), "r"(src2), "r" ((x86_reg)width-15) in interleaveBytes()
1798 ::"r"(dest), "r"(src1), "r"(src2), "r" ((x86_reg)width-15) in interleaveBytes()
1804 dest[2*w+0] = src1[w]; in interleaveBytes()
1808 src1 += src1Stride; in interleaveBytes()
1823 const uint8_t *src1,
1848 static inline void RENAME(vu9_to_vu12)(const uint8_t *src1, const uint8_t *src2, in vu9_to_vu12() argument
1860 ::"m"(*(src1+srcStride1)),"m"(*(src2+srcStride2)):"memory"); in vu9_to_vu12()
1862 const uint8_t* s1=src1 in vu9_to_vu12()
1940 yvu9_to_yuy2(const uint8_t *src1, const uint8_t *src2, const uint8_t *src3, uint8_t *dst, int width, int height, int srcStride1, int srcStride2, int srcStride3, int dstStride) yvu9_to_yuy2() argument
2149 extract_even2avg(const uint8_t *src0, const uint8_t *src1, uint8_t *dst0, uint8_t *dst1, x86_reg count) extract_even2avg() argument
2249 extract_odd2avg(const uint8_t *src0, const uint8_t *src1, uint8_t *dst0, uint8_t *dst1, x86_reg count) extract_odd2avg() argument
[all...]
/third_party/node/deps/v8/src/codegen/mips/
H A Dmacro-assembler-mips.h289 void Push(Register src1, Register src2) { in Push() argument
291 sw(src1, MemOperand(sp, 1 * kPointerSize)); in Push()
296 void Push(Register src1, Register src2, Register src3) { in Push() argument
298 sw(src1, MemOperand(sp, 2 * kPointerSize)); in Push()
304 void Push(Register src1, Register src2, Register src3, Register src4) { in Push() argument
306 sw(src1, MemOperand(sp, 3 * kPointerSize)); in Push()
313 void Push(Register src1, Register src2, Register src3, Register src4, in Push() argument
316 sw(src1, MemOperand(sp, 4 * kPointerSize)); in Push()
381 void Pop(Register src1, Register src2) { in Pop() argument
382 DCHECK(src1 ! in Pop()
389 Pop(Register src1, Register src2, Register src3) Pop() argument
[all...]
/third_party/mesa3d/src/compiler/spirv/
H A Dvtn_alu.c68 struct vtn_ssa_value *src1 = wrap_matrix(b, _src1); in matrix_multiply() local
74 unsigned src1_columns = glsl_get_matrix_columns(src1->type); in matrix_multiply()
90 src1 = src0_transpose; in matrix_multiply()
99 /* We already have the rows of src0 and the columns of src1 available, in matrix_multiply()
108 src1->elems[i]->def); in matrix_multiply()
113 /* We don't handle the case where src1 is transposed but not src0, since in matrix_multiply()
114 * the general case only uses individual components of src1 so the in matrix_multiply()
115 * optimizer should chew through the transpose we emitted for src1. in matrix_multiply()
119 /* dest[i] = sum(src0[j] * src1[i][j] for all j) */ in matrix_multiply()
122 nir_channel(&b->nb, src1 in matrix_multiply()
204 vtn_handle_matrix_alu(struct vtn_builder *b, SpvOp opcode, struct vtn_ssa_value *src0, struct vtn_ssa_value *src1) vtn_handle_matrix_alu() argument
1159 nir_ssa_def *const src1 = vtn_handle_integer_dot() local
[all...]
/third_party/node/deps/v8/src/codegen/ppc/
H A Dassembler-ppc.cc798 void Assembler::addc(Register dst, Register src1, Register src2, OEBit o, in addc() argument
800 xo_form(EXT2 | ADDCX, dst, src1, src2, o, r); in addc()
803 void Assembler::adde(Register dst, Register src1, Register src2, OEBit o, in adde() argument
805 xo_form(EXT2 | ADDEX, dst, src1, src2, o, r); in adde()
808 void Assembler::addze(Register dst, Register src1, OEBit o, RCBit r) { in addze() argument
810 emit(EXT2 | ADDZEX | dst.code() * B21 | src1.code() * B16 | o | r); in addze()
813 void Assembler::sub(Register dst, Register src1, Register src2, OEBit o, in sub() argument
815 xo_form(EXT2 | SUBFX, dst, src2, src1, o, r); in sub()
818 void Assembler::subc(Register dst, Register src1, Register src2, OEBit o, in subc() argument
820 xo_form(EXT2 | SUBFCX, dst, src2, src1, in subc()
823 sube(Register dst, Register src1, Register src2, OEBit o, RCBit r) sube() argument
832 add(Register dst, Register src1, Register src2, OEBit o, RCBit r) add() argument
838 mullw(Register dst, Register src1, Register src2, OEBit o, RCBit r) mullw() argument
848 mulhw(Register dst, Register src1, Register src2, RCBit r) mulhw() argument
853 mulhwu(Register dst, Register src1, Register src2, RCBit r) mulhwu() argument
858 divw(Register dst, Register src1, Register src2, OEBit o, RCBit r) divw() argument
864 divwu(Register dst, Register src1, Register src2, OEBit o, RCBit r) divwu() argument
899 cmpi(Register src1, const Operand& src2, CRegister cr) cmpi() argument
912 cmpli(Register src1, const Operand& src2, CRegister cr) cmpli() argument
925 cmpwi(Register src1, const Operand& src2, CRegister cr) cmpwi() argument
942 cmplwi(Register src1, const Operand& src2, CRegister cr) cmplwi() argument
1128 mulld(Register dst, Register src1, Register src2, OEBit o, RCBit r) mulld() argument
1133 divd(Register dst, Register src1, Register src2, OEBit o, RCBit r) divd() argument
1138 divdu(Register dst, Register src1, Register src2, OEBit o, RCBit r) divdu() argument
[all...]
/third_party/node/deps/v8/src/codegen/ia32/
H A Dassembler-ia32.cc2865 void Assembler::vss(byte op, XMMRegister dst, XMMRegister src1, Operand src2) { in vss() argument
2866 vinstr(op, dst, src1, src2, kF3, k0F, kWIG); in vss()
2869 void Assembler::vps(byte op, XMMRegister dst, XMMRegister src1, Operand src2) { in vps() argument
2870 vinstr(op, dst, src1, src2, kNoPrefix, k0F, kWIG); in vps()
2873 void Assembler::vpd(byte op, XMMRegister dst, XMMRegister src1, Operand src2) { in vpd() argument
2874 vinstr(op, dst, src1, src2, k66, k0F, kWIG); in vpd()
2877 void Assembler::vshufpd(XMMRegister dst, XMMRegister src1, Operand src2, in vshufpd() argument
2880 vpd(0xC6, dst, src1, src2); in vshufpd()
2884 void Assembler::vmovhlps(XMMRegister dst, XMMRegister src1, XMMRegister src2) { in vmovhlps() argument
2885 vinstr(0x12, dst, src1, src in vmovhlps()
2888 vmovlhps(XMMRegister dst, XMMRegister src1, XMMRegister src2) vmovlhps() argument
2892 vmovlps(XMMRegister dst, XMMRegister src1, Operand src2) vmovlps() argument
2900 vmovhps(XMMRegister dst, XMMRegister src1, Operand src2) vmovhps() argument
2908 vcmpps(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t cmp) vcmpps() argument
2914 vcmppd(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t cmp) vcmppd() argument
2920 vshufps(XMMRegister dst, XMMRegister src1, Operand src2, byte imm8) vshufps() argument
2990 vblendvps(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask) vblendvps() argument
2996 vblendvpd(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask) vblendvpd() argument
3002 vpblendvb(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask) vpblendvb() argument
3008 vpblendw(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t mask) vpblendw() argument
3014 vpalignr(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t mask) vpalignr() argument
3035 vinsertps(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t offset) vinsertps() argument
3041 vpinsrb(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t offset) vpinsrb() argument
3047 vpinsrw(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t offset) vpinsrw() argument
3053 vpinsrd(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t offset) vpinsrd() argument
3059 vroundsd(XMMRegister dst, XMMRegister src1, XMMRegister src2, RoundingMode mode) vroundsd() argument
3064 vroundss(XMMRegister dst, XMMRegister src1, XMMRegister src2, RoundingMode mode) vroundss() argument
3107 vpcmpgtq(XMMRegister dst, XMMRegister src1, XMMRegister src2) vpcmpgtq() argument
3205 vinstr(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2, SIMDPrefix pp, LeadingOpcode m, VexW w, CpuFeature feature) vinstr() argument
3211 vinstr(byte op, XMMRegister dst, XMMRegister src1, Operand src2, SIMDPrefix pp, LeadingOpcode m, VexW w, CpuFeature feature) vinstr() argument
3217 vinstr(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2, VectorLength l, SIMDPrefix pp, LeadingOpcode m, VexW w, CpuFeature feature) vinstr() argument
3227 vinstr(byte op, XMMRegister dst, XMMRegister src1, Operand src2, VectorLength l, SIMDPrefix pp, LeadingOpcode m, VexW w, CpuFeature feature) vinstr() argument
[all...]
/third_party/ffmpeg/libavcodec/
H A Dgdv.c144 uint8_t *src1 = dst + PREAMBLE_SIZE + (y>>!!gdv->scale_h) * (w>>1); in rescale() local
146 scaleup_rev(dst1, src1, w); in rescale()
152 uint8_t *src1 = dst + PREAMBLE_SIZE + (y>>1) * w; in rescale() local
153 memcpy(dst1, src1, w); in rescale()
160 uint8_t *src1 = dst + PREAMBLE_SIZE + y*2 * w; in rescale() local
161 scaledown(dst1, src1, w>>1); in rescale()
166 uint8_t *src1 = dst + PREAMBLE_SIZE + y*2 * w; in rescale() local
167 memcpy(dst1, src1, w); in rescale()
H A Dmss2dsp.c106 uint8_t *src1, *src2, *dst1, *dst2, *p, a, b; in upsample_plane_c() local
124 src1 = plane + plane_stride * ((j + 1) >> 1); in upsample_plane_c()
128 a = src1[i]; in upsample_plane_c()
H A Dh264pred_template.c421 const pixel * src1 = src +8*stride-1; in pred16x16_plane_compat() local
422 const pixel * src2 = src1-2*stride; // == src+6*stride-1; in pred16x16_plane_compat()
424 int V = src1[0] - src2[ 0]; in pred16x16_plane_compat()
426 src1 += stride; src2 -= stride; in pred16x16_plane_compat()
428 V += k*(src1[0] - src2[ 0]); in pred16x16_plane_compat()
444 a = 16*(src1[0] + src2[16] + 1) - 7*(V+H); in pred16x16_plane_compat()
755 const pixel * src1 = src +4*stride-1; in pred8x8_plane() local
756 const pixel * src2 = src1-2*stride; // == src+2*stride-1; in pred8x8_plane()
758 int V = src1[0] - src2[ 0]; in pred8x8_plane()
760 src1 in pred8x8_plane()
791 const pixel * src1 = src +8*stride-1; pred8x16_plane() local
[all...]
H A Dh264qpel_template.c108 const int src1= src[1 *srcStride];\
112 OP(dst[0*dstStride], (src0+src1)*20 - (srcA+src2)*5 + (srcB+src3));\
113 OP(dst[1*dstStride], (src1+src2)*20 - (src0+src3)*5 + (srcA+src4));\
185 const int src1= src[1 *srcStride];\
191 OP(dst[0*dstStride], (src0+src1)*20 - (srcA+src2)*5 + (srcB+src3));\
192 OP(dst[1*dstStride], (src1+src2)*20 - (src0+src3)*5 + (srcA+src4));\
193 OP(dst[2*dstStride], (src2+src3)*20 - (src1+src4)*5 + (src0+src5));\
194 OP(dst[3*dstStride], (src3+src4)*20 - (src2+src5)*5 + (src1+src6));\
277 const int src1= src[1 *srcStride];\
287 OP(dst[0*dstStride], (src0+src1)*2
[all...]
/third_party/ffmpeg/libavcodec/mips/
H A Dac3dsp_mips.c209 float src0, src1, src2, src3, src4, src5, src6, src7; in float_to_fixed24_mips() local
215 "lwc1 %[src1], 4(%[src]) \n\t" in float_to_fixed24_mips()
223 "mul.s %[src1], %[src1], %[scale] \n\t" in float_to_fixed24_mips()
231 "cvt.w.s %[src1], %[src1] \n\t" in float_to_fixed24_mips()
239 "mfc1 %[temp1], %[src1] \n\t" in float_to_fixed24_mips()
256 [src0] "=&f" (src0), [src1] "=&f" (src1), in float_to_fixed24_mips()
/third_party/mesa3d/src/amd/compiler/
H A Daco_lower_to_hw_instr.cpp189 emit_vadd32(Builder& bld, Definition def, Operand src0, Operand src1) in emit_vadd32() argument
191 Instruction* instr = bld.vadd32(def, src0, src1, false, Operand(s2), true); in emit_vadd32()
207 Operand src1[] = {Operand(src1_reg, v1), Operand(PhysReg{src1_reg + 1}, v1)}; in emit_int64_dpp_op() local
217 bld.vop3(aco_opcode::v_add_co_u32_e64, dst[0], bld.def(bld.lm, vcc), vtmp_op[0], src1[0]); in emit_int64_dpp_op()
219 bld.vop2_dpp(aco_opcode::v_add_co_u32, dst[0], bld.def(bld.lm, vcc), src0[0], src1[0], in emit_int64_dpp_op()
222 bld.vop2_dpp(aco_opcode::v_addc_co_u32, dst[1], bld.def(bld.lm, vcc), src0[1], src1[1], in emit_int64_dpp_op()
225 bld.vop2_dpp(aco_opcode::v_and_b32, dst[0], src0[0], src1[0], dpp_ctrl, row_mask, bank_mask, in emit_int64_dpp_op()
227 bld.vop2_dpp(aco_opcode::v_and_b32, dst[1], src0[1], src1[1], dpp_ctrl, row_mask, bank_mask, in emit_int64_dpp_op()
230 bld.vop2_dpp(aco_opcode::v_or_b32, dst[0], src0[0], src1[0], dpp_ctrl, row_mask, bank_mask, in emit_int64_dpp_op()
232 bld.vop2_dpp(aco_opcode::v_or_b32, dst[1], src0[1], src1[ in emit_int64_dpp_op()
306 Operand src1[] = {Operand(src1_reg, v1), Operand(PhysReg{src1_reg + 1}, v1)}; emit_int64_op() local
1024 create_bperm(Builder& bld, uint8_t swiz[4], Definition dst, Operand src1, Operand src0 = Operand(v1)) create_bperm() argument
1195 addsub_subdword_gfx11(Builder& bld, Definition dst, Operand src0, Operand src1, bool sub) addsub_subdword_gfx11() argument
[all...]
/third_party/mesa3d/src/gallium/auxiliary/tgsi/
H A Dtgsi_ureg.h734 struct ureg_src src1 ) \
748 ureg_emit_src( ureg, src1 ); \
757 struct ureg_src src1 ) \
774 ureg_emit_src( ureg, src1 ); \
782 struct ureg_src src1, \
797 ureg_emit_src( ureg, src1 ); \
806 struct ureg_src src1, \
822 ureg_emit_src( ureg, src1 ); \
833 struct ureg_src src1, \
852 ureg_emit_src( ureg, src1 ); \
[all...]
/third_party/libwebsockets/lib/core-net/
H A Dlws-dsh.c38 _lws_dsh_alloc_tail(lws_dsh_t *dsh, int kind, const void *src1, size_t size1,
150 _lws_dsh_alloc_tail(lws_dsh_t *dsh, int kind, const void *src1, size_t size1, in _lws_dsh_alloc_tail() argument
194 memcpy(&s.best[1], src1, size1); in _lws_dsh_alloc_tail()
242 memcpy(&obj[1], src1, size1); in _lws_dsh_alloc_tail()
273 lws_dsh_alloc_tail(lws_dsh_t *dsh, int kind, const void *src1, size_t size1, in lws_dsh_alloc_tail() argument
276 return _lws_dsh_alloc_tail(dsh, kind, src1, size1, src2, size2, NULL); in lws_dsh_alloc_tail()
/third_party/mesa3d/src/gallium/auxiliary/gallivm/
H A Dlp_bld_tgsi_info.c410 struct lp_tgsi_channel_info src1; in analyse_instruction() local
413 analyse_src(ctx, &src1, &inst->Src[1].Register, chan); in analyse_instruction()
417 } else if (is_immediate(&src1, 0.0f)) { in analyse_instruction()
418 res[chan] = src1; in analyse_instruction()
420 res[chan] = src1; in analyse_instruction()
421 } else if (is_immediate(&src1, 1.0f)) { in analyse_instruction()
/third_party/node/deps/v8/src/codegen/riscv64/
H A Dmacro-assembler-riscv64.h298 void Push(Register src1, Register src2) { in Push() argument
300 Sd(src1, MemOperand(sp, 1 * kSystemPointerSize)); in Push()
305 void Push(Register src1, Register src2, Register src3) { in Push() argument
307 Sd(src1, MemOperand(sp, 2 * kSystemPointerSize)); in Push()
313 void Push(Register src1, Register src2, Register src3, Register src4) { in Push() argument
315 Sd(src1, MemOperand(sp, 3 * kSystemPointerSize)); in Push()
322 void Push(Register src1, Register src2, Register src3, Register src4, in Push() argument
325 Sd(src1, MemOperand(sp, 4 * kSystemPointerSize)); in Push()
388 void Pop(Register src1, Register src2) { in Pop() argument
389 DCHECK(src1 ! in Pop()
396 Pop(Register src1, Register src2, Register src3) Pop() argument
[all...]

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