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Searched refs:screen (Results 151 - 175 of 2172) sorted by relevance

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/third_party/mesa3d/src/gallium/drivers/zink/
H A Dzink_program.c92 get_shader_module_for_stage(struct zink_context *ctx, struct zink_screen *screen, in get_shader_module_for_stage() argument
109 if (zs->can_inline && (screen->is_cpu || prog->inlined_variant_count[pstage] < ZINK_MAX_INLINED_VARIANTS)) in get_shader_module_for_stage()
134 mod = zink_shader_tcs_compile(screen, zs, patch_vertices); in get_shader_module_for_stage()
136 mod = zink_shader_compile(screen, zs, prog->nir[stage], key); in get_shader_module_for_stage()
172 zink_destroy_shader_module(struct zink_screen *screen, struct zink_shader_module *zm) in zink_destroy_shader_module() argument
174 VKSCR(DestroyShaderModule)(screen->dev, zm->shader, NULL); in zink_destroy_shader_module()
179 destroy_shader_cache(struct zink_screen *screen, struct list_head *sc) in destroy_shader_cache() argument
184 zink_destroy_shader_module(screen, zm); in destroy_shader_cache()
190 struct zink_screen *screen, in update_gfx_shader_modules()
200 struct zink_shader_module *zm = get_shader_module_for_stage(ctx, screen, pro in update_gfx_shader_modules()
189 update_gfx_shader_modules(struct zink_context *ctx, struct zink_screen *screen, struct zink_gfx_program *prog, uint32_t mask, struct zink_gfx_pipeline_state *state) update_gfx_shader_modules() argument
291 struct zink_screen *screen = zink_screen(ctx->base.screen); update_cs_shader_module() local
364 zink_pipeline_layout_create(struct zink_screen *screen, struct zink_program *pg, uint32_t *compat) zink_pipeline_layout_create() argument
434 struct zink_screen *screen = zink_screen(ctx->base.screen); zink_create_gfx_program() local
546 struct zink_screen *screen = zink_screen(ctx->base.screen); zink_create_compute_program() local
686 struct zink_screen *screen = zink_screen(ctx->base.screen); zink_destroy_gfx_program() local
734 struct zink_screen *screen = zink_screen(ctx->base.screen); zink_destroy_compute_program() local
812 struct zink_screen *screen = zink_screen(ctx->base.screen); zink_get_gfx_pipeline() local
889 zink_get_compute_pipeline(struct zink_screen *screen, struct zink_compute_program *comp, struct zink_compute_pipeline_state *state) zink_get_compute_pipeline() argument
1005 struct zink_screen *screen = zink_screen(ctx->base.screen); bind_last_vertex_stage() local
1185 struct zink_screen *screen = zink_screen(pctx->screen); zink_delete_cached_shader_state() local
1193 struct zink_screen *screen = zink_screen(pctx->screen); zink_create_cached_shader_state() local
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H A Dzink_bo.h181 zink_bo_init(struct zink_screen *screen);
184 zink_bo_deinit(struct zink_screen *screen);
187 zink_bo_create(struct zink_screen *screen, uint64_t size, unsigned alignment, enum zink_heap heap, enum zink_alloc_flag flags, const void *pNext);
190 zink_bo_get_kms_handle(struct zink_screen *screen, struct zink_bo *bo, int fd, uint32_t *handle);
211 zink_bo_map(struct zink_screen *screen, struct zink_bo *bo);
213 zink_bo_unmap(struct zink_screen *screen, struct zink_bo *bo);
216 zink_bo_commit(struct zink_screen *screen, struct zink_resource *res, unsigned level, struct pipe_box *box, bool commit, VkSemaphore *sem);
240 zink_bo_usage_check_completion(struct zink_screen *screen, struct zink_bo *bo, enum zink_resource_access access) in zink_bo_usage_check_completion() argument
242 if (access & ZINK_RESOURCE_ACCESS_READ && !zink_screen_usage_check_completion(screen, bo->reads)) in zink_bo_usage_check_completion()
244 if (access & ZINK_RESOURCE_ACCESS_WRITE && !zink_screen_usage_check_completion(screen, b in zink_bo_usage_check_completion()
277 zink_bo_unref(struct zink_screen *screen, struct zink_bo *bo) zink_bo_unref() argument
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H A Dzink_descriptors.c144 (is_buffer ? zink_screen(ctx->base.screen)->null_descriptor_hashes.buffer_view : in zink_get_sampler_view_hash()
145 zink_screen(ctx->base.screen)->null_descriptor_hashes.image_view); in zink_get_sampler_view_hash()
152 (is_buffer ? zink_screen(ctx->base.screen)->null_descriptor_hashes.buffer_view : in zink_get_image_view_hash()
153 zink_screen(ctx->base.screen)->null_descriptor_hashes.image_view); in zink_get_image_view_hash()
160 return dsurf->is_buffer ? (dsurf->bufferview ? dsurf->bufferview->hash : zink_screen(ctx->base.screen)->null_descriptor_hashes.buffer_view) : in get_descriptor_surface_hash()
161 (dsurf->surface ? dsurf->surface->hash : zink_screen(ctx->base.screen)->null_descriptor_hashes.image_view); in get_descriptor_surface_hash()
271 descriptor_pool_free(struct zink_screen *screen, struct zink_descriptor_pool *pool) in descriptor_pool_free() argument
276 VKSCR(DestroyDescriptorPool)(screen->dev, pool->descpool, NULL); in descriptor_pool_free()
297 struct zink_screen *screen = zink_screen(ctx->base.screen); in descriptor_pool_delete() local
305 descriptor_pool_create(struct zink_screen *screen, enum zink_descriptor_type type, const struct zink_descriptor_pool_key *pool_key) descriptor_pool_create() argument
348 descriptor_layout_create(struct zink_screen *screen, enum zink_descriptor_type t, VkDescriptorSetLayoutBinding *bindings, unsigned num_bindings) descriptor_layout_create() argument
413 struct zink_screen *screen = zink_screen(ctx->base.screen); create_layout() local
527 get_push_types(struct zink_screen *screen, enum zink_descriptor_type *dsl_type) get_push_types() argument
538 struct zink_screen *screen = zink_screen(ctx->base.screen); create_gfx_layout() local
557 struct zink_screen *screen = zink_screen(ctx->base.screen); zink_descriptor_util_push_layouts_get() local
617 zink_descriptor_util_alloc_sets(struct zink_screen *screen, VkDescriptorSetLayout dsl, VkDescriptorPool pool, VkDescriptorSet *sets, unsigned num_sets) zink_descriptor_util_alloc_sets() argument
641 struct zink_screen *screen = zink_screen(ctx->base.screen); allocate_desc_set() local
786 struct zink_screen *screen = zink_screen(ctx->base.screen); zink_descriptor_set_get() local
1114 struct zink_screen *screen = zink_screen(ctx->base.screen); zink_descriptor_program_init() local
1281 struct zink_screen *screen = zink_screen(ctx->base.screen); update_push_ubo_descriptors() local
1371 struct zink_screen *screen = zink_screen(ctx->base.screen); update_descriptors_internal() local
1575 zink_batch_descriptor_deinit(struct zink_screen *screen, struct zink_batch_state *bs) zink_batch_descriptor_deinit() argument
1584 zink_batch_descriptor_reset(struct zink_screen *screen, struct zink_batch_state *bs) zink_batch_descriptor_reset() argument
1604 zink_batch_descriptor_init(struct zink_screen *screen, struct zink_batch_state *bs) zink_batch_descriptor_init() argument
1764 struct zink_screen *screen = zink_screen(ctx->base.screen); zink_context_update_descriptor_states() local
1888 struct zink_screen *screen = zink_screen(ctx->base.screen); zink_descriptor_layouts_deinit() local
1906 struct zink_screen *screen = zink_screen(ctx->base.screen); zink_descriptor_util_init_fbfetch() local
1936 struct zink_screen *screen = zink_screen(ctx->base.screen); zink_descriptors_init_bindless() local
1991 struct zink_screen *screen = zink_screen(ctx->base.screen); zink_descriptors_deinit_bindless() local
2001 struct zink_screen *screen = zink_screen(ctx->base.screen); zink_descriptors_update_bindless() local
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H A Dzink_state.c44 struct zink_screen *screen = zink_screen(pctx->screen); in zink_create_vertex_elements_state() local
73 assert(!elem->instance_divisor || zink_screen(pctx->screen)->info.have_EXT_vertex_attribute_divisor); in zink_create_vertex_elements_state()
74 if (elem->instance_divisor > screen->info.vdiv_props.maxVertexAttribDivisor) in zink_create_vertex_elements_state()
75 debug_printf("zink: clamping instance divisor %u to %u\n", elem->instance_divisor, screen->info.vdiv_props.maxVertexAttribDivisor); in zink_create_vertex_elements_state()
76 ves->divisor[binding] = MIN2(elem->instance_divisor, screen->info.vdiv_props.maxVertexAttribDivisor); in zink_create_vertex_elements_state()
79 if (screen->format_props[elem->src_format].bufferFeatures & VK_FORMAT_FEATURE_VERTEX_BUFFER_BIT) in zink_create_vertex_elements_state()
80 format = zink_get_format(screen, elem->src_format); in zink_create_vertex_elements_state()
85 assert(screen->format_props[new_format].bufferFeatures & VK_FORMAT_FEATURE_VERTEX_BUFFER_BIT); in zink_create_vertex_elements_state()
92 format = zink_get_format(screen, new_forma in zink_create_vertex_elements_state()
570 struct zink_screen *screen = zink_screen(pctx->screen); zink_create_rasterizer_state() local
631 struct zink_screen *screen = zink_screen(pctx->screen); zink_bind_rasterizer_state() local
772 struct zink_screen *screen = zink_screen(pscreen); zink_cache_create_vertex_state() local
781 struct zink_screen *screen = zink_screen(pscreen); zink_cache_vertex_state_destroy() local
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/third_party/mesa3d/src/gallium/drivers/nouveau/nvc0/
H A Dnvc0_query_hw_sm.c2233 nvc0_hw_sm_get_queries(struct nvc0_screen *screen) in nvc0_hw_sm_get_queries() argument
2235 struct nouveau_device *dev = screen->base.device; in nvc0_hw_sm_get_queries()
2237 switch (screen->base.class_3d) { in nvc0_hw_sm_get_queries()
2258 nvc0_hw_sm_get_num_queries(struct nvc0_screen *screen) in nvc0_hw_sm_get_num_queries() argument
2260 struct nouveau_device *dev = screen->base.device; in nvc0_hw_sm_get_num_queries()
2262 switch (screen->base.class_3d) { in nvc0_hw_sm_get_num_queries()
2285 struct nvc0_screen *screen = nvc0->screen; in nvc0_hw_sm_query_get_cfg() local
2290 num_queries = nvc0_hw_sm_get_num_queries(screen); in nvc0_hw_sm_query_get_cfg()
2291 queries = nvc0_hw_sm_get_queries(screen); in nvc0_hw_sm_query_get_cfg()
2313 struct nvc0_screen *screen = nvc0->screen; nve4_hw_sm_begin_query() local
2398 struct nvc0_screen *screen = nvc0->screen; nvc0_hw_sm_begin_query() local
2465 nvc0_hw_sm_get_program(struct nvc0_screen *screen) nvc0_hw_sm_get_program() argument
2504 struct nvc0_screen *screen = nvc0->screen; nvc0_hw_sm_upload_input() local
2537 struct nvc0_screen *screen = nvc0->screen; nvc0_hw_sm_end_query() local
2719 struct nvc0_screen *screen = nvc0->screen; nvc0_hw_sm_create_query() local
2796 nvc0_hw_sm_get_driver_query_info(struct nvc0_screen *screen, unsigned id, struct pipe_driver_query_info *info) nvc0_hw_sm_get_driver_query_info() argument
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H A Dnvc0_query_hw_metric.c398 nvc0_hw_metric_get_queries(struct nvc0_screen *screen) in nvc0_hw_metric_get_queries() argument
400 struct nouveau_device *dev = screen->base.device; in nvc0_hw_metric_get_queries()
402 switch (screen->base.class_3d) { in nvc0_hw_metric_get_queries()
422 nvc0_hw_metric_get_num_queries(struct nvc0_screen *screen) in nvc0_hw_metric_get_num_queries() argument
424 struct nouveau_device *dev = screen->base.device; in nvc0_hw_metric_get_num_queries()
426 switch (screen->base.class_3d) { in nvc0_hw_metric_get_num_queries()
448 struct nvc0_screen *screen = nvc0->screen; in nvc0_hw_metric_query_get_cfg() local
453 num_queries = nvc0_hw_metric_get_num_queries(screen); in nvc0_hw_metric_query_get_cfg()
454 queries = nvc0_hw_metric_get_queries(screen); in nvc0_hw_metric_query_get_cfg()
672 struct nvc0_screen *screen = nvc0->screen; nvc0_hw_metric_get_query_result() local
750 nvc0_hw_metric_get_driver_query_info(struct nvc0_screen *screen, unsigned id, struct pipe_driver_query_info *info) nvc0_hw_metric_get_driver_query_info() argument
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H A Dnvc0_state_validate.c92 struct nvc0_screen *screen = nvc0->screen; in gm200_validate_sample_locations() local
99 screen->base.base.get_sample_pixel_grid( in gm200_validate_sample_locations()
100 &screen->base.base, ms, &grid_width, &grid_height); in gm200_validate_sample_locations()
110 &screen->base.base, nvc0->framebuffer.height, ms, locations); in gm200_validate_sample_locations()
133 PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(4)); in gm200_validate_sample_locations()
134 PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(4)); in gm200_validate_sample_locations()
166 struct nvc0_screen *screen = nvc0->screen; in nvc0_validate_sample_locations() local
171 PUSH_DATAh(push, screen in nvc0_validate_sample_locations()
475 struct nvc0_screen *screen = nvc0->screen; nvc0_upload_uclip_planes() local
637 struct nvc0_screen *screen = nvc0->screen; nvc0_validate_buffers() local
716 struct nvc0_screen *screen = nvc0->screen; nvc0_validate_driverconst() local
804 struct nvc0_screen *screen = nvc0->screen; nvc0_validate_fbread() local
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/third_party/mesa3d/src/gallium/frontends/nine/
H A Dquery9.c35 d3dquerytype_to_pipe_query(struct pipe_screen *screen, D3DQUERYTYPE type) in d3dquerytype_to_pipe_query() argument
41 return screen->get_param(screen, PIPE_CAP_OCCLUSION_QUERY) ? in d3dquerytype_to_pipe_query()
44 return screen->get_param(screen, PIPE_CAP_QUERY_TIMESTAMP) ? in d3dquerytype_to_pipe_query()
48 return screen->get_param(screen, PIPE_CAP_QUERY_TIMESTAMP) ? in d3dquerytype_to_pipe_query()
51 return screen->get_param(screen, in d3dquerytype_to_pipe_query()
78 nine_is_query_supported(struct pipe_screen *screen, D3DQUERYTYP argument
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/third_party/mesa3d/src/gallium/frontends/clover/core/
H A Devent.cpp142 pipe_screen *screen = queue()->device().pipe; in ~hard_event() local
143 screen->fence_reference(screen, &_fence, NULL); in ~hard_event()
148 pipe_screen *screen = queue()->device().pipe; in status() local
156 else if (!screen->fence_finish(screen, NULL, _fence, 0)) in status()
175 pipe_screen *screen = queue()->device().pipe; in wait() local
183 !screen->fence_finish(screen, NULL, _fence, PIPE_TIMEOUT_INFINITE)) in wait()
210 pipe_screen *screen in fence() local
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/third_party/mesa3d/src/gallium/auxiliary/vl/
H A Dvl_decoder.c36 vl_profile_supported(struct pipe_screen *screen, enum pipe_video_profile profile, in vl_profile_supported() argument
39 assert(screen); in vl_profile_supported()
49 vl_level_supported(struct pipe_screen *screen, enum pipe_video_profile profile) in vl_level_supported() argument
51 assert(screen); in vl_level_supported()
74 pot_buffers = !pipe->screen->get_video_param in vl_create_decoder()
76 pipe->screen, in vl_create_decoder()
/third_party/skia/tools/sk_app/mac/
H A DWindowContextFactory_mac.h24 UIScreen* screen = view.window.screen ?: [UIScreen mainScreen]; in GetBackingScaleFactor() local
25 return screen.nativeScale; in GetBackingScaleFactor()
27 NSScreen* screen = view.window.screen ?: [NSScreen mainScreen]; in GetBackingScaleFactor()
28 return screen.backingScaleFactor; in GetBackingScaleFactor()
/third_party/mesa3d/src/gallium/drivers/crocus/
H A Dcrocus_pipe_control.c62 const struct intel_device_info *devinfo = &batch->screen->devinfo; in crocus_emit_pipe_control_flush()
83 batch->screen->vtbl.emit_raw_pipe_control(batch, reason, flags, NULL, 0, 0); in crocus_emit_pipe_control_flush()
100 batch->screen->vtbl.emit_raw_pipe_control(batch, reason, flags, bo, offset, imm); in crocus_emit_pipe_control_write()
118 UNUSED const struct intel_device_info *devinfo = &batch->screen->devinfo; in crocus_emit_depth_stall_flushes()
161 const struct intel_device_info *devinfo = &batch->screen->devinfo; in crocus_emit_end_of_pipe_sync()
192 if (batch->screen->devinfo.platform == INTEL_PLATFORM_HSW) { in crocus_emit_end_of_pipe_sync()
194 batch->screen->vtbl.load_register_mem32(batch, GEN7_3DPRIM_START_INSTANCE, in crocus_emit_end_of_pipe_sync()
206 * render appears on the screen in DRI1.
213 const struct intel_device_info *devinfo = &batch->screen->devinfo; in crocus_emit_mi_flush()
301 const struct intel_device_info *devinfo = &render_batch->screen in crocus_texture_barrier()
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/third_party/mesa3d/src/gallium/drivers/radeonsi/
H A Dsi_fence.c91 struct si_screen *sscreen = ctx->screen; in si_cp_release_mem()
97 assert(ctx->screen->info.has_tmz_support); in si_cp_release_mem()
110 assert(16 * ctx->screen->info.max_render_backends <= scratch->b.b.width0); in si_cp_release_mem()
164 unsigned si_cp_write_fence_dwords(struct si_screen *screen) in si_cp_write_fence_dwords() argument
168 if (screen->info.gfx_level == GFX7 || screen->info.gfx_level == GFX8) in si_cp_write_fence_dwords()
200 static void si_fence_reference(struct pipe_screen *screen, struct pipe_fence_handle **dst, in si_fence_reference() argument
203 struct radeon_winsys *ws = ((struct si_screen *)screen)->ws; in si_fence_reference()
282 static bool si_fence_finish(struct pipe_screen *screen, struct pipe_context *ctx, in si_fence_finish() argument
285 struct radeon_winsys *rws = ((struct si_screen *)screen) in si_fence_finish()
422 si_fence_get_fd(struct pipe_screen *screen, struct pipe_fence_handle *fence) si_fence_get_fd() argument
458 struct pipe_screen *screen = ctx->screen; si_flush_all_queues() local
614 si_init_screen_fence_functions(struct si_screen *screen) si_init_screen_fence_functions() argument
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/third_party/mesa3d/src/gallium/drivers/r600/
H A Dr600_perfcounter.c118 static bool r600_pc_query_prepare_buffer(struct r600_common_screen *screen, in r600_pc_query_prepare_buffer() argument
130 struct r600_perfcounters *pc = ctx->screen->perfcounters; in r600_pc_query_emit_start()
161 struct r600_perfcounters *pc = ctx->screen->perfcounters; in r600_pc_query_emit_stop()
173 se_end = ctx->screen->info.max_se; in r600_pc_query_emit_stop()
233 static struct r600_pc_group *get_group_state(struct r600_common_screen *screen, in get_group_state() argument
260 sub_gids = sub_gids * screen->info.max_se; in get_group_state()
264 shaders = screen->perfcounters->shader_type_bits[shader_id]; in get_group_state()
304 struct r600_common_screen *screen = in r600_create_batch_query() local
305 (struct r600_common_screen *)ctx->screen; in r600_create_batch_query()
306 struct r600_perfcounters *pc = screen in r600_create_batch_query()
430 r600_init_block_names(struct r600_common_screen *screen, struct r600_perfcounter_block *block) r600_init_block_names() argument
514 r600_get_perfcounter_info(struct r600_common_screen *screen, unsigned index, struct pipe_driver_query_info *info) r600_get_perfcounter_info() argument
556 r600_get_perfcounter_group_info(struct r600_common_screen *screen, unsigned index, struct pipe_driver_query_group_info *info) r600_get_perfcounter_group_info() argument
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/third_party/mesa3d/src/gallium/frontends/dri/
H A Ddri_context.c52 struct dri_screen *screen = dri_screen(sPriv); in dri_create_context() local
53 struct st_api *stapi = screen->st_api; in dri_create_context()
65 screen->sPriv->dri2.backgroundCallable; in dri_create_context()
66 const struct driOptionCache *optionCache = &screen->dev->option_cache; in dri_create_context()
68 if (screen->has_reset_status_query) { in dri_create_context()
161 driQueryOptionb(&screen->dev->option_cache, "mesa_no_error")) in dri_create_context()
167 attribs.options = screen->options; in dri_create_context()
168 dri_fill_st_visual(&attribs.visual, screen, visual); in dri_create_context()
169 ctx->st = stapi->create_context(stapi, &screen->base, &attribs, &ctx_err, in dri_create_context()
201 ctx->pp = pp_init(ctx->st->pipe, screen in dri_create_context()
263 struct dri_screen *screen = dri_screen(cPriv->driScreenPriv); dri_unbind_context() local
321 struct dri_screen *screen = dri_screen(sPriv); dri_get_current() local
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/third_party/mesa3d/src/gallium/drivers/d3d12/
H A Dd3d12_batch.cpp43 struct d3d12_screen *screen = d3d12_screen(ctx->base.screen); in d3d12_init_batch() local
60 if (FAILED(screen->dev->CreateCommandAllocator(D3D12_COMMAND_LIST_TYPE_DIRECT, in d3d12_init_batch()
66 d3d12_descriptor_heap_new(screen->dev, in d3d12_init_batch()
72 d3d12_descriptor_heap_new(screen->dev, in d3d12_init_batch()
162 struct d3d12_screen *screen = d3d12_screen(ctx->base.screen); in d3d12_start_batch() local
176 if (FAILED(screen->dev->CreateCommandList(0, D3D12_COMMAND_LIST_TYPE_DIRECT, in d3d12_start_batch()
201 struct d3d12_screen *screen = d3d12_screen(ctx->base.screen); in d3d12_end_batch() local
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/third_party/mesa3d/src/gallium/drivers/asahi/
H A Dagx_pipe.c153 agx_resource_create(struct pipe_screen *screen, in agx_resource_create() argument
156 struct agx_device *dev = agx_device(screen); in agx_resource_create()
164 nresource->base.screen = screen; in agx_resource_create()
202 struct sw_winsys *winsys = ((struct agx_screen *) screen)->winsys; in agx_resource_create()
245 agx_resource_destroy(struct pipe_screen *screen, in agx_resource_destroy() argument
252 struct agx_screen *agx_screen = (struct agx_screen*)screen; in agx_resource_destroy()
440 struct agx_device *dev = agx_device(pctx->screen); in agx_flush()
612 agx_create_context(struct pipe_screen *screen, in agx_create_context() argument
621 pctx->screen in agx_create_context()
1087 agx_destroy_screen(struct pipe_screen *screen) agx_destroy_screen() argument
1095 agx_fence_reference(struct pipe_screen *screen, struct pipe_fence_handle **ptr, struct pipe_fence_handle *fence) agx_fence_reference() argument
1102 agx_fence_finish(struct pipe_screen *screen, struct pipe_context *ctx, struct pipe_fence_handle *fence, uint64_t timeout) agx_fence_finish() argument
1152 struct pipe_screen *screen; agx_screen_create() local
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/third_party/mesa3d/src/glx/apple/
H A Dappledri.h94 Bool XAppleDRIQueryDirectRenderingCapable(Display * dpy, int screen,
100 Bool XAppleDRIAuthConnection(Display * dpy, int screen, unsigned int magic);
102 Bool XAppleDRICreateSurface(Display * dpy, int screen, Drawable drawable,
106 Bool XAppleDRIDestroySurface(Display * dpy, int screen, Drawable drawable);
110 Bool XAppleDRICreateSharedBuffer(Display * dpy, int screen, Drawable drawable,
114 Bool XAppleDRISwapBuffers(Display * dpy, int screen, Drawable drawable);
116 Bool XAppleDRICreatePixmap(Display * dpy, int screen, Drawable drawable,
/third_party/mesa3d/src/gallium/drivers/freedreno/a2xx/
H A Dfd2_screen.c120 struct fd_screen *screen = fd_screen(pscreen); in fd2_screen_init() local
122 screen->max_rts = 1; in fd2_screen_init()
126 screen->setup_slices = fd2_setup_slices; in fd2_screen_init()
128 screen->tile_mode = fd2_tile_mode; in fd2_screen_init()
132 if (screen->gpu_id >= 220) { in fd2_screen_init()
133 screen->primtypes = a22x_primtypes; in fd2_screen_init()
135 screen->primtypes = a20x_primtypes; in fd2_screen_init()
/third_party/mesa3d/src/gallium/drivers/freedreno/a3xx/
H A Dfd3_context.c65 struct fd_screen *screen = fd_screen(pscreen); variable
73 pctx->screen = pscreen;
76 fd3_ctx->base.dev = fd_device_ref(screen->dev);
77 fd3_ctx->base.screen = fd_screen(pscreen);
98 fd_bo_new(screen->dev, 0x2000, 0, "vs_pvt");
101 fd_bo_new(screen->dev, 0x2000, 0, "fs_pvt");
104 fd_bo_new(screen->dev, 0x1000, 0, "vsc_size");
/third_party/mesa3d/src/gallium/drivers/freedreno/a4xx/
H A Dfd4_context.c66 struct fd_screen *screen = fd_screen(pscreen); variable
74 pctx->screen = pscreen;
77 fd4_ctx->base.dev = fd_device_ref(screen->dev);
78 fd4_ctx->base.screen = fd_screen(pscreen);
100 fd_bo_new(screen->dev, 0x2000, 0, "vs_pvt");
103 fd_bo_new(screen->dev, 0x2000, 0, "fs_pvt");
106 fd_bo_new(screen->dev, 0x1000, 0, "vsc_size");
/third_party/mesa3d/src/gallium/drivers/r300/
H A Dr300_texture_desc.c114 static unsigned r300_texture_get_stride(struct r300_screen *screen, in r300_texture_get_stride() argument
119 boolean is_rs690 = (screen->caps.family == CHIP_RS600 || in r300_texture_get_stride()
120 screen->caps.family == CHIP_RS690 || in r300_texture_get_stride()
121 screen->caps.family == CHIP_RS740); in r300_texture_get_stride()
128 SCREEN_DBG(screen, DBG_TEX, "%s: level (%u) > last_level (%u)\n", in r300_texture_get_stride()
212 static void r300_setup_miptree(struct r300_screen *screen, in r300_setup_miptree() argument
218 boolean rv350_mode = screen->caps.family >= CHIP_R350; in r300_setup_miptree()
223 SCREEN_DBG(screen, DBG_TEXALLOC, in r300_setup_miptree()
235 stride = r300_texture_get_stride(screen, tex, i); in r300_setup_miptree()
262 SCREEN_DBG(screen, DBG_TEXALLO in r300_setup_miptree()
314 r300_setup_hyperz_properties(struct r300_screen *screen, struct r300_resource *tex) r300_setup_hyperz_properties() argument
414 r300_setup_cmask_properties(struct r300_screen *screen, struct r300_resource *tex) r300_setup_cmask_properties() argument
467 r300_setup_tiling(struct r300_screen *screen, struct r300_resource *tex) r300_setup_tiling() argument
[all...]
/third_party/mesa3d/src/gallium/frontends/xvmc/
H A Dsubpicture.c51 static enum pipe_format XvIDToPipe(struct pipe_screen *screen, in XvIDToPipe() argument
55 assert(screen); in XvIDToPipe()
64 if (!screen->is_format_supported( in XvIDToPipe()
65 screen, ret, PIPE_TEXTURE_2D, 0, 0, PIPE_BIND_SAMPLER_VIEW)) in XvIDToPipe()
71 if (!screen->is_format_supported( in XvIDToPipe()
72 screen, ret, PIPE_TEXTURE_2D, 0, 0, PIPE_BIND_SAMPLER_VIEW)) in XvIDToPipe()
81 if (!screen->is_format_supported( in XvIDToPipe()
82 screen, ret, PIPE_TEXTURE_2D, 0, 0, PIPE_BIND_SAMPLER_VIEW)) { in XvIDToPipe()
106 static int PipeToComponentOrder(struct pipe_screen *screen, in PipeToComponentOrder() argument
111 assert(screen); in PipeToComponentOrder()
[all...]
/third_party/mesa3d/src/gallium/auxiliary/util/
H A Du_helpers.c340 ctx->screen->fence_finish(ctx->screen, NULL, fence, PIPE_TIMEOUT_INFINITE); in util_wait_for_idle()
350 util_throttle_deinit(struct pipe_screen *screen, struct util_throttle *t) in util_throttle_deinit() argument
353 screen->fence_reference(screen, &t->ring[i].fence, NULL); in util_throttle_deinit()
399 struct pipe_screen *screen = pipe->screen; in util_throttle_memory_usage() local
413 screen->fence_reference(screen, fence, NULL); in util_throttle_memory_usage()
424 screen in util_throttle_memory_usage()
502 util_init_pipe_vertex_state(struct pipe_screen *screen, struct pipe_vertex_buffer *buffer, const struct pipe_vertex_element *elements, unsigned num_elements, struct pipe_resource *indexbuf, uint32_t full_velem_mask, struct pipe_vertex_state *state) util_init_pipe_vertex_state() argument
[all...]
/third_party/mesa3d/src/gallium/drivers/softpipe/
H A Dsp_fence.c35 softpipe_fence_reference(struct pipe_screen *screen, in softpipe_fence_reference() argument
44 softpipe_fence_finish(struct pipe_screen *screen, in softpipe_fence_finish() argument
55 softpipe_init_screen_fence_funcs(struct pipe_screen *screen) in softpipe_init_screen_fence_funcs() argument
57 screen->fence_reference = softpipe_fence_reference; in softpipe_init_screen_fence_funcs()
58 screen->fence_finish = softpipe_fence_finish; in softpipe_init_screen_fence_funcs()

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