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Searched refs:regs (Results 26 - 50 of 314) sorted by relevance

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/third_party/backends/backend/
H A Du12-motor.c142 saveModel = dev->regs.RD_ModelControl; in u12motor_PositionModuleToHome()
170 dev->regs.RD_ModelControl = saveModel; in u12motor_PositionModuleToHome()
230 dev->regs.RD_ModeControl = _ModeScan; in u12motor_BackToHomeSensor()
264 _SET_REG( rb, c, REG_LINECONTROL, dev->regs.RD_LineControl); in u12motor_BackToHomeSensor()
265 _SET_REG( rb, c, REG_XSTEPTIME, dev->regs.RD_XStepTime); in u12motor_BackToHomeSensor()
269 dev->regs.RD_LineControl, dev->regs.RD_XStepTime ); in u12motor_BackToHomeSensor()
285 (SANE_Byte)(dev->regs.RD_Motor0Control|_MotorDirForward)); in u12motor_ModuleToHome()
331 bXStep < dev->regs.RD_XStepTime ) { in u12motor_WaitForPositionY()
338 (SANE_Byte)(dev->regs in u12motor_WaitForPositionY()
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H A Dlexmark_low.c74 static SANE_Status low_write_all_regs (SANE_Int devnum, SANE_Byte * regs);
81 static void low_rewind (Lexmark_Device * dev, SANE_Byte * regs);
86 SANE_Byte * regs,
98 SANE_Byte * regs, Lexmark_Device * dev);
127 rts88xx_is_color (SANE_Byte * regs) in rts88xx_is_color() argument
129 if ((regs[0x2f] & 0x11) == 0x11) in rts88xx_is_color()
135 rts88xx_set_gray_scan (SANE_Byte * regs) in rts88xx_set_gray_scan() argument
137 regs[0x2f] = (regs[0x2f] & 0x0f) | 0x20; in rts88xx_set_gray_scan()
142 rts88xx_set_color_scan (SANE_Byte * regs)
149 rts88xx_set_offset(SANE_Byte * regs, SANE_Byte red, SANE_Byte green, SANE_Byte blue) rts88xx_set_offset() argument
164 rts88xx_set_gain(SANE_Byte * regs, SANE_Byte red, SANE_Byte green, SANE_Byte blue) rts88xx_set_gain() argument
174 rts88xx_set_scan_frequency(SANE_Byte * regs, int frequency) rts88xx_set_scan_frequency() argument
373 SANE_Byte regs[14] = lexmark_low_set_idle() local
956 low_start_scan(SANE_Int devnum, SANE_Byte * regs) low_start_scan() argument
1035 low_simple_scan(Lexmark_Device * dev, SANE_Byte * regs, int xoffset, int pixels, int yoffset, int lines, SANE_Byte ** data) low_simple_scan() argument
1258 low_write_all_regs(SANE_Int devnum, SANE_Byte * regs) low_write_all_regs() argument
1464 sanei_lexmark_low_move_fwd(SANE_Int distance, Lexmark_Device * dev, SANE_Byte * regs) sanei_lexmark_low_move_fwd() argument
2401 low_set_scan_area(SANE_Int res, SANE_Int tlx, SANE_Int tly, SANE_Int brx, SANE_Int bry, SANE_Int offset, SANE_Bool half_step, SANE_Byte * regs, Lexmark_Device * dev) low_set_scan_area() argument
5101 low_rewind(Lexmark_Device * dev, SANE_Byte * regs) low_rewind() argument
5477 average_area(SANE_Byte * regs, SANE_Byte * data, int width, int height, int *ra, int *ga, int *ba) average_area() argument
5525 SANE_Byte regs[255]; /* we have our own copy of shadow registers */ sanei_lexmark_low_offset_calibration() local
5667 SANE_Byte regs[255]; /* we have our own copy of shadow registers */ sanei_lexmark_low_gain_calibration() local
5763 SANE_Byte regs[255]; /* we have our own copy of shadow registers */ sanei_lexmark_low_shading_calibration() local
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/third_party/mesa3d/src/panfrost/bifrost/
H A Dbi_print.c44 bi_print_slots(bi_registers *regs, FILE *fp) in bi_print_slots() argument
47 if (regs->enabled[i]) in bi_print_slots()
48 fprintf(fp, "slot %u: %u\n", i, regs->slot[i]); in bi_print_slots()
51 if (regs->slot23.slot2) { in bi_print_slots()
53 bi_reg_op_name(regs->slot23.slot2), in bi_print_slots()
54 regs->slot23.slot2 >= BIFROST_OP_WRITE ? in bi_print_slots()
56 regs->slot[2]); in bi_print_slots()
59 if (regs->slot23.slot3) { in bi_print_slots()
61 bi_reg_op_name(regs->slot23.slot3), in bi_print_slots()
62 regs in bi_print_slots()
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H A Ddisassemble.c56 static unsigned get_reg0(struct bifrost_regs regs) in get_reg0() argument
58 if (regs.ctrl == 0) in get_reg0()
59 return regs.reg0 | ((regs.reg1 & 0x1) << 5); in get_reg0()
61 return regs.reg0 <= regs.reg1 ? regs.reg0 : 63 - regs.reg0; in get_reg0()
64 static unsigned get_reg1(struct bifrost_regs regs) in get_reg1() argument
66 return regs in get_reg1()
136 DecodeRegCtrl(FILE *fp, struct bifrost_regs regs, bool first) DecodeRegCtrl() argument
652 struct bifrost_regs regs, next_regs; dump_clause() local
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/third_party/mesa3d/src/gallium/frontends/nine/
H A Dnine_shader.c354 /* number of regs parsed outside of special handler */
489 } regs; member
490 unsigned num_temp; /* ARRAY_SIZE(regs.r) */
772 if (tx->num_scratch >= ARRAY_SIZE(tx->regs.t)) { in tx_scratch()
774 return tx->regs.t[0]; in tx_scratch()
776 if (ureg_dst_is_undef(tx->regs.t[tx->num_scratch])) in tx_scratch()
777 tx->regs.t[tx->num_scratch] = ureg_DECL_local_temporary(tx->ureg); in tx_scratch()
778 return tx->regs.t[tx->num_scratch++]; in tx_scratch()
804 tx->regs.r = REALLOC(tx->regs in tx_temp_alloc()
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/third_party/mesa3d/src/amd/vulkan/
H A Dradv_perfcounter.c107 uint32_t regs[8]; member
150 .impl = {.op = arg_op, .regs = {__VA_ARGS__}}, \
332 unsigned full_reg_cnt = num_indices * ARRAY_SIZE(descs->impl.regs); in radv_get_counter_registers()
333 uint32_t *regs = malloc(full_reg_cnt * sizeof(uint32_t)); in radv_get_counter_registers() local
334 if (!regs) in radv_get_counter_registers()
341 for (unsigned j = 0; j < ARRAY_SIZE(descs[index].impl.regs) && descs[index].impl.regs[j]; in radv_get_counter_registers()
343 if (!G_REG_CONSTANT(descs[index].impl.regs[j])) in radv_get_counter_registers()
344 regs[reg_cnt++] = descs[index].impl.regs[ in radv_get_counter_registers()
370 radv_get_num_counter_passes(const struct radv_physical_device *pdevice, unsigned num_regs, const uint32_t *regs) radv_get_num_counter_passes() argument
491 struct ac_pc_block_base *regs = block->b->b; radv_emit_select() local
516 struct ac_pc_block_base *regs = block->b->b; radv_pc_emit_block_instance_read() local
915 uint32_t *regs = NULL; radv_GetPhysicalDeviceQueueFamilyPerformanceQueryPassesKHR() local
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/third_party/backends/backend/genesys/
H A Dtables_frontend.cpp46 fe.regs = { in genesys_init_frontend_tables()
68 fe.regs = { in genesys_init_frontend_tables()
90 fe.regs = { in genesys_init_frontend_tables()
112 fe.regs = { in genesys_init_frontend_tables()
135 fe.regs = { in genesys_init_frontend_tables()
157 fe.regs = { in genesys_init_frontend_tables()
180 fe.regs = { in genesys_init_frontend_tables()
203 fe.regs = { in genesys_init_frontend_tables()
226 fe.regs = { in genesys_init_frontend_tables()
249 fe.regs in genesys_init_frontend_tables()
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H A Dgl646.cpp436 Genesys_Register_Set* regs, in init_regs_for_scan_session()
467 scanner_setup_sensor(*dev, sensor, *regs); in init_regs_for_scan_session()
480 regs->find_reg(0x01).value |= REG_0x01_DOGENB | REG_0x01_SCAN; in init_regs_for_scan_session()
482 regs->find_reg(0x01).value |= REG_0x01_CISSET; in init_regs_for_scan_session()
484 regs->find_reg(0x01).value &= ~REG_0x01_CISSET; in init_regs_for_scan_session()
491 regs->find_reg(0x01).value &= ~REG_0x01_DVDSET; in init_regs_for_scan_session()
493 regs->find_reg(0x01).value |= REG_0x01_DVDSET; in init_regs_for_scan_session()
496 regs->find_reg(0x01).value &= ~REG_0x01_FASTMOD; in init_regs_for_scan_session()
498 regs->find_reg(0x01).value |= REG_0x01_FASTMOD; in init_regs_for_scan_session()
510 sanei_genesys_set_motor_power(*regs, tru in init_regs_for_scan_session()
435 init_regs_for_scan_session(Genesys_Device* dev, const Genesys_Sensor& sensor, Genesys_Register_Set* regs, const ScanSession& session) const init_regs_for_scan_session() argument
2317 coarse_gain_calibration(Genesys_Device* dev, const Genesys_Sensor& sensor, Genesys_Register_Set& regs, int dpi) const coarse_gain_calibration() argument
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H A Dcommand_set.h47 Genesys_Register_Set* regs) const = 0;
50 Genesys_Register_Set& regs) const = 0;
64 Genesys_Register_Set* regs, bool start_motor) const = 0;
65 virtual void end_scan(Genesys_Device* dev, Genesys_Register_Set* regs,
75 Genesys_Register_Set& regs) const = 0;
77 Genesys_Register_Set& regs, int dpi) const = 0;
79 Genesys_Register_Set& regs) const = 0;
129 virtual void set_motor_mode(Genesys_Device& dev, Genesys_Register_Set& regs,
H A Dlow.cpp566 Genesys_Register_Set& regs, bool set) in sanei_genesys_set_lamp_power()
571 regs.find_reg(0x03).value |= REG_0x03_LAMPPWR; in sanei_genesys_set_lamp_power()
574 regs_set_exposure(dev->model->asic_type, regs, in sanei_genesys_set_lamp_power()
576 regs.set8(0x19, 0x50); in sanei_genesys_set_lamp_power()
580 regs_set_exposure(dev->model->asic_type, regs, sensor.exposure); in sanei_genesys_set_lamp_power()
591 regs.find_reg(0x03).value &= ~REG_0x03_LAMPPWR; in sanei_genesys_set_lamp_power()
594 regs.find_reg(0x03).value &= ~REG_0x03_LAMPPWR; in sanei_genesys_set_lamp_power()
597 regs_set_exposure(dev->model->asic_type, regs, sanei_genesys_fixup_exposure({0, 0, 0})); in sanei_genesys_set_lamp_power()
598 regs.set8(0x19, 0xff); in sanei_genesys_set_lamp_power()
601 regs_set_exposure(dev->model->asic_type, regs, sanei_genesys_fixup_exposur in sanei_genesys_set_lamp_power()
565 sanei_genesys_set_lamp_power(Genesys_Device* dev, const Genesys_Sensor& sensor, Genesys_Register_Set& regs, bool set) sanei_genesys_set_lamp_power() argument
607 sanei_genesys_set_motor_power(Genesys_Register_Set& regs, bool set) sanei_genesys_set_motor_power() argument
1501 sanei_genesys_set_dpihw(Genesys_Register_Set& regs, unsigned dpihw) sanei_genesys_set_dpihw() argument
1530 regs_set_exposure(AsicType asic_type, Genesys_Register_Set& regs, const SensorExposure& exposure) regs_set_exposure() argument
1582 regs_set_optical_off(AsicType asic_type, Genesys_Register_Set& regs) regs_set_optical_off() argument
1620 get_registers_gain4_bit(AsicType asic_type, const Genesys_Register_Set& regs) get_registers_gain4_bit() argument
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H A Dgl842.h40 Genesys_Register_Set* regs) const override;
43 Genesys_Register_Set& regs) const override;
54 Genesys_Register_Set* regs, bool start_motor) const override;
56 void end_scan(Genesys_Device* dev, Genesys_Register_Set* regs, bool check_stop) const override;
61 Genesys_Register_Set& regs) const override;
64 Genesys_Register_Set& regs, int dpi) const override;
67 Genesys_Register_Set& regs) const override;
H A Dgl843.h40 Genesys_Register_Set* regs) const override;
43 Genesys_Register_Set& regs) const override;
54 Genesys_Register_Set* regs, bool start_motor) const override;
56 void end_scan(Genesys_Device* dev, Genesys_Register_Set* regs, bool check_stop) const override;
61 Genesys_Register_Set& regs) const override;
64 Genesys_Register_Set& regs, int dpi) const override;
67 Genesys_Register_Set& regs) const override;
H A Dgl846.h40 Genesys_Register_Set* regs) const override;
43 Genesys_Register_Set& regs) const override;
54 Genesys_Register_Set* regs, bool start_motor) const override;
56 void end_scan(Genesys_Device* dev, Genesys_Register_Set* regs, bool check_stop) const override;
61 Genesys_Register_Set& regs) const override;
64 Genesys_Register_Set& regs, int dpi) const override;
67 Genesys_Register_Set& regs) const override;
H A Dgl847.h40 Genesys_Register_Set* regs) const override;
43 Genesys_Register_Set& regs) const override;
54 Genesys_Register_Set* regs, bool start_motor) const override;
56 void end_scan(Genesys_Device* dev, Genesys_Register_Set* regs, bool check_stop) const override;
61 Genesys_Register_Set& regs) const override;
64 Genesys_Register_Set& regs, int dpi) const override;
67 Genesys_Register_Set& regs) const override;
H A Dgl124.h40 Genesys_Register_Set* regs) const override;
43 Genesys_Register_Set& regs) const override;
54 Genesys_Register_Set* regs, bool start_motor) const override;
56 void end_scan(Genesys_Device* dev, Genesys_Register_Set* regs, bool check_stop) const override;
61 Genesys_Register_Set& regs) const override;
64 Genesys_Register_Set& regs, int dpi) const override;
67 Genesys_Register_Set& regs) const override;
H A Dgl646.h44 Genesys_Register_Set* regs) const override;
47 Genesys_Register_Set& regs) const override;
58 Genesys_Register_Set* regs, bool start_motor) const override;
60 void end_scan(Genesys_Device* dev, Genesys_Register_Set* regs, bool check_stop) const override;
65 Genesys_Register_Set& regs) const override;
68 Genesys_Register_Set& regs, int dpi) const override;
71 Genesys_Register_Set& regs) const override;
H A Dgl841.h40 Genesys_Register_Set* regs) const override;
43 Genesys_Register_Set& regs) const override;
54 Genesys_Register_Set* regs, bool start_motor) const override;
56 void end_scan(Genesys_Device* dev, Genesys_Register_Set* regs, bool check_stop) const override;
61 Genesys_Register_Set& regs) const override;
64 Genesys_Register_Set& regs, int dpi) const override;
67 Genesys_Register_Set& regs) const override;
/third_party/elfutils/backends/
H A Dppc_initreg.c104 struct pt_regs regs; in ppc_set_initial_registers_tid()
105 struct pt_regs32 *regs32 = (struct pt_regs32 *) &regs; in ppc_set_initial_registers_tid()
107 iovec.iov_base = &regs; in ppc_set_initial_registers_tid()
108 iovec.iov_len = sizeof (regs); in ppc_set_initial_registers_tid()
116 dwarf_regs[gpr] = get32 ? regs32->gpr[gpr] : regs.gpr[gpr]; in ppc_set_initial_registers_tid()
120 Dwarf_Word link = get32 ? regs32->link : regs.link; in ppc_set_initial_registers_tid()
125 Dwarf_Word pc = get32 ? (Dwarf_Word) regs32->nip : regs.nip; in ppc_set_initial_registers_tid()
H A Dsparc_initreg.c59 struct pt_regs regs; in set_initial_registers_tid()
60 if (ptrace (PTRACE_GETREGS, tid, &regs, 0) == -1) in set_initial_registers_tid()
64 if (!setfunc (-1, 1, (Dwarf_Word *) &regs.tpc, arg)) in set_initial_registers_tid()
71 if (!setfunc (1, 7, (Dwarf_Word *) &regs.u_regs[0], arg)) in set_initial_registers_tid()
75 if (!setfunc (8, 8, (Dwarf_Word *) &regs.u_regs[7], arg)) in set_initial_registers_tid()
83 Dwarf_Word sp = regs.u_regs[13]; in set_initial_registers_tid()
/third_party/mesa3d/src/gallium/drivers/r600/
H A Degd_tables.py147 def parse(filename, regs, packets):
159 for it in regs:
165 regs.append(reg)
200 for reg in regs:
205 for reg in regs:
214 def write_tables(regs, packets):
255 for reg in regs:
279 for reg in regs:
299 regs = []
302 parse(arg, regs, packet
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/third_party/ltp/testcases/kernel/syscalls/ptrace/
H A Dptrace04.c31 } regs[] = { variable
65 for (i = 0; i < ARRAY_SIZE(regs); ++i) { in compare_registers()
68 (void *)regs[i].off, NULL); in compare_registers()
73 regs[i].name, regs[i].off); in compare_registers()
78 long *pt_val = (void *)&_pt_regs + regs[i].off; in compare_registers()
84 regs[i].name, regs[i].off, *pt_val, in compare_registers()
104 if (ARRAY_SIZE(regs) == 0) in main()
/third_party/mesa3d/src/imagination/vulkan/
H A Dpvr_job_render.c1175 pvr_csb_pack (&state->regs.pds_ctrl, CR_PDS_CTRL, value) { in pvr_render_job_ws_geometry_state_init()
1179 state->regs.pds_ctrl = 0; in pvr_render_job_ws_geometry_state_init()
1182 pvr_csb_pack (&state->regs.ppp_ctrl, CR_PPP_CTRL, value) { in pvr_render_job_ws_geometry_state_init()
1187 pvr_csb_pack (&state->regs.te_psg, CR_TE_PSG, value) { in pvr_render_job_ws_geometry_state_init()
1199 pvr_csb_pack (&state->regs.tpu, CR_TPU, value) { in pvr_render_job_ws_geometry_state_init()
1203 pvr_csb_pack (&state->regs.tpu_border_colour_table, in pvr_render_job_ws_geometry_state_init()
1209 pvr_csb_pack (&state->regs.vdm_ctrl_stream_base, in pvr_render_job_ws_geometry_state_init()
1219 pvr_csb_pack (&state->regs.vdm_ctx_resume_task0_size, in pvr_render_job_ws_geometry_state_init()
1316 &state->regs.usc_pixel_output_ctrl); in pvr_render_job_ws_fragment_state_init()
1318 pvr_csb_pack (&state->regs in pvr_render_job_ws_fragment_state_init()
[all...]
/third_party/mesa3d/src/gallium/drivers/etnaviv/
H A Detnaviv_compiler_nir_ra.c87 struct ra_regs *regs = ra_alloc_reg_set(mem_ctx, ETNA_MAX_TEMPS * in etna_ra_setup() local
95 classes[c] = ra_alloc_reg_class(regs); in etna_ra_setup()
104 ra_add_reg_conflict(regs, NUM_REG_TYPES * r + i, in etna_ra_setup()
110 ra_set_finalize(regs, q_values); in etna_ra_setup()
112 return regs; in etna_ra_setup()
119 struct ra_regs *regs = compiler->regs; in etna_ra_assign() local
141 struct ra_graph *g = ra_alloc_interference_graph(regs, num_nodes); in etna_ra_assign()
176 ra_set_node_class(g, i, ra_get_class_from_index(regs, comp)); in etna_ra_assign()
201 ra_set_node_class(g, index, ra_get_class_from_index(regs, REG_CLASS_VEC in etna_ra_assign()
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/third_party/mesa3d/src/imagination/vulkan/winsys/pvrsrvkm/
H A Dpvr_srv_job_compute.c95 * reset_cmd.regs size from reset_cmd size to only pass empty flags field. in pvr_srv_winsys_compute_ctx_create()
100 sizeof(reset_cmd) - sizeof(reset_cmd.regs), in pvr_srv_winsys_compute_ctx_create()
143 struct rogue_fwif_cdm_regs *fw_regs = &cmd->regs; in pvr_srv_compute_cmd_init()
149 fw_regs->tpu_border_colour_table = submit_info->regs.tpu_border_colour_table; in pvr_srv_compute_cmd_init()
150 fw_regs->cdm_item = submit_info->regs.cdm_item; in pvr_srv_compute_cmd_init()
151 fw_regs->compute_cluster = submit_info->regs.compute_cluster; in pvr_srv_compute_cmd_init()
152 fw_regs->cdm_ctrl_stream_base = submit_info->regs.cdm_ctrl_stream_base; in pvr_srv_compute_cmd_init()
154 submit_info->regs.cdm_ctx_state_base_addr; in pvr_srv_compute_cmd_init()
155 fw_regs->tpu = submit_info->regs.tpu; in pvr_srv_compute_cmd_init()
156 fw_regs->cdm_resume_pds1 = submit_info->regs in pvr_srv_compute_cmd_init()
[all...]
/third_party/vixl/test/aarch64/examples/
H A Dtest-examples.cc163 RegisterDump regs; \
182 regs.Dump(&masm); \
193 VIXL_CHECK(static_cast<uint64_t>(regs.xreg(0)) == FactorialC(N)); \
218 VIXL_CHECK(static_cast<uint64_t>(regs.xreg(0)) == FactorialC(N)); \
349 VIXL_CHECK(regs.dreg(0) == Add3DoubleC(A, B, C)); \
375 VIXL_CHECK(regs.dreg(0) == Add4DoubleC(A, B, C, D)); \
401 VIXL_CHECK(regs.xreg(0) == SumArrayC(Array, ARRAY_SIZE(Array))); \
429 VIXL_CHECK(regs.xreg(0) == abs(X)); \
462 VIXL_CHECK(regs.xreg(0) == chksum); in TEST()
484 VIXL_CHECK(regs in TEST()
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