| /base/hiviewdfx/faultloggerd/interfaces/common/ |
| H A D | unwind_riscv64_define.h | 88 uint64_t regs[31]; member
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| /base/hiviewdfx/faultloggerd/tools/process_dump/ |
| H A D | dfx_thread.h | 47 void SetThreadRegs(const std::shared_ptr<DfxRegs> ®s);
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| H A D | cppcrash_reporter.h | 61 static std::string GetRegsString(std::shared_ptr<DfxRegs> regs);
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| H A D | printer.h | 43 static void PrintRegsByConfig(std::shared_ptr<DfxRegs> regs);
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| /base/hiviewdfx/faultloggerd/interfaces/innerkits/unwinder/include/ |
| H A D | unwind_context.h | 69 std::shared_ptr<DfxRegs> regs = nullptr; member
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| H A D | arm_exidx.h | 33 std::vector<int32_t> regs; member
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| /third_party/elfutils/backends/ |
| H A D | aarch64_initreg.c | 67 if (! setfunc (0, 32, (Dwarf_Word *) &gregs.regs[0], arg)) in aarch64_set_initial_registers_tid()
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| H A D | csky_initreg.c | 71 dwarf_regs[i] = user_regs.regs[i - 4]; in csky_set_initial_registers_tid()
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| H A D | arm_initreg.c | 85 uint32_t *u32_ptr = (uint32_t *) &gregs.regs[0]; in arm_set_initial_registers_tid()
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| /third_party/musl/arch/or1k/bits/ |
| H A D | signal.h | 16 } regs; member
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| /third_party/musl/arch/x32/bits/ |
| H A D | user.h | 20 struct user_regs_struct regs; member
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| /third_party/musl/arch/i386/bits/ |
| H A D | user.h | 23 struct user_regs_struct regs; member
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| /third_party/musl/arch/x86_64/bits/ |
| H A D | user.h | 20 struct user_regs_struct regs; member
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| /third_party/rust/crates/libc/src/unix/linux_like/linux/gnu/b64/aarch64/ |
| H A D | align.rs | 21 pub regs: [::c_ulonglong; 31],
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| /third_party/python/Modules/_sre/ |
| H A D | sre.h | 47 PyObject* regs; /* cached list of matching spans */ member
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| /third_party/backends/backend/ |
| H A D | u12-image.c | 74 dev->regs.RD_ModeControl = _ModeFifoBSel; in fnReadToDriver()
78 dev->regs.RD_ModeControl = _ModeFifoGSel; in fnReadToDriver()
91 dev->regs.RD_ModeControl = _ModeFifoRSel; in fnReadToDriver()
129 dev->regs.RD_ModeControl = _ModeFifoBSel; in fnReadOutScanner()
137 dev->regs.RD_ModeControl = _ModeFifoGSel; in fnReadOutScanner()
470 dev->regs.RD_ThresholdControl = brightness; in imageSetupScanSettings()
696 dev->regs.RD_ModeControl = _ModeFifoGSel; in u12image_DataIsReady()
708 dev->regs.RD_ModeControl = _ModeFifoGSel; in u12image_DataIsReady()
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| H A D | hp4200.c | 123 return (unsigned char) LOBYTE (s->regs[reg]); in getreg()
134 s->regs[reg] = reg_value; /* dirty bit should be clear with this */ in setreg()
144 s->regs[reg] = (s->regs[reg] & 0xff) | bitmap; in setbits()
147 lm9830_write_register (s->fd, reg, LOBYTE (s->regs[reg])); in setbits()
154 s->regs[reg] = (s->regs[reg] & ~mask) & 0xff; in clearbits()
157 lm9830_write_register (s->fd, reg, LOBYTE (s->regs[reg])); in clearbits()
172 if (!(s->regs[i] & 0x100)) in cache_write()
182 lm9830_write_register (s->fd, i, s->regs[ in cache_write()
[all...] |
| /third_party/mesa3d/src/intel/compiler/ |
| H A D | brw_fs_reg_allocate.cpp | 68 fail("Ran out of regs on trivial allocator (%d/%d)\n", in assign_regs_trivial()
113 * instruction, and on gfx4 we need 8 contiguous regs for workaround simd16 in brw_alloc_reg_set()
121 struct ra_regs *regs = ra_alloc_reg_set(compiler, BRW_MAX_GRF, false); in brw_alloc_reg_set() local
123 ra_set_allocate_round_robin(regs); in brw_alloc_reg_set()
131 classes[i] = ra_alloc_contig_reg_class(regs, class_sizes[i]); in brw_alloc_reg_set()
158 aligned_bary_class = ra_alloc_contig_reg_class(regs, contig_len); in brw_alloc_reg_set()
164 ra_set_finalize(regs, NULL); in brw_alloc_reg_set()
166 compiler->fs_reg_sets[index].regs = regs; in brw_alloc_reg_set()
221 /* Since payload regs ar in calculate_payload_ranges()
[all...] |
| /third_party/mesa3d/src/freedreno/ir3/ |
| H A D | ir3_postsched.c | 354 * Note, this table is twice as big as the # of regs, to deal with
355 * half-precision regs. The approach differs depending on whether
362 struct ir3_postsched_node *regs[2 * 256]; member
371 assert((idx) < ARRAY_SIZE((state)->regs)); \
372 &(state)->regs[(idx)]; \
448 num += ARRAY_SIZE(state->regs) / 2; in add_reg_dep()
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/DartARM32/ |
| H A D | assembler_arm.cc | 140 RegList regs) {
148 regs;
523 void Assembler::ldm(BlockAddressMode am, Register base, RegList regs,
525 ASSERT(regs != 0);
526 EmitMultiMemOp(cond, am, true, base, regs);
531 void Assembler::stm(BlockAddressMode am, Register base, RegList regs,
533 ASSERT(regs != 0);
534 EmitMultiMemOp(cond, am, false, base, regs);
1764 RegList regs = (1 << CODE_REG) | (1 << LR);
1766 regs |
[all...] |
| /third_party/backends/backend/genesys/ |
| H A D | gl843.cpp | 37 static int gl843_get_step_multiplier(Genesys_Register_Set* regs) in gl843_get_step_multiplier() argument
39 switch (regs->get8(REG_0x9D) & 0x0c) { in gl843_get_step_multiplier()
613 for (const auto& reg : dev->frontend.regs) { in gl843_set_ad_fe()
643 dev->interface->write_fe_register(i, dev->frontend.regs.get_value(0x00 + i)); in set_fe()
655 dev->interface->write_fe_register(0x24 + i, dev->frontend.regs.get_value(0x24 + i)); in set_fe()
1344 Genesys_Register_Set& regs) const in init_regs_for_shading()
1423 init_regs_for_scan_session(dev, calib_sensor, ®s, session); in init_regs_for_shading()
1465 Genesys_Register_Set& regs) const in led_calibration()
1467 return scanner_led_calibration(*dev, sensor, regs); in led_calibration()
1471 Genesys_Register_Set& regs) cons in offset_calibration()
1476 coarse_gain_calibration(Genesys_Device* dev, const Genesys_Sensor& sensor, Genesys_Register_Set& regs, int dpi) const coarse_gain_calibration() argument
[all...] |
| H A D | scanner_interface_usb.h | 40 void write_registers(const Genesys_Register_Set& regs) override;
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| H A D | scanner_interface.h | 43 virtual void write_registers(const Genesys_Register_Set& regs) = 0;
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| /third_party/elfutils/libdw/ |
| H A D | dwarf_frame_register.c | 56 const struct dwarf_frame_register *reg = &fs->regs[regno]; in dwarf_frame_register()
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| /third_party/musl/src/thread/powerpc/ |
| H A D | clone.s | 17 # store non-volatile regs r30, r31 on stack in order to put our
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