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/third_party/mesa3d/src/amd/vulkan/
H A Dradv_debug.c970 struct radv_sq_hw_reg *regs = (struct radv_sq_hw_reg *)&device->tma_ptr[6]; in radv_dump_sq_hw_regs() local
975 regs->status, ~0); in radv_dump_sq_hw_regs()
977 regs->trap_sts, ~0); in radv_dump_sq_hw_regs()
979 regs->hw_id, ~0); in radv_dump_sq_hw_regs()
981 regs->ib_sts, ~0); in radv_dump_sq_hw_regs()
984 regs->status, ~0); in radv_dump_sq_hw_regs()
986 regs->trap_sts, ~0); in radv_dump_sq_hw_regs()
988 regs->hw_id, ~0); in radv_dump_sq_hw_regs()
990 regs->ib_sts, ~0); in radv_dump_sq_hw_regs()
/third_party/pcre2/pcre2/src/sljit/
H A DsljitNativeX86_32.c1210 sljit_u8 regs[2]; in sljit_emit_mem() local
1220 regs[0] = U8(REG_PAIR_FIRST(reg)); in sljit_emit_mem()
1221 regs[1] = U8(REG_PAIR_SECOND(reg)); in sljit_emit_mem()
1225 if (!(type & SLJIT_MEM_STORE) && (regs[0] == (mem & REG_MASK) || regs[0] == OFFS_REG(mem))) { in sljit_emit_mem()
1226 if (regs[1] == (mem & REG_MASK) || regs[1] == OFFS_REG(mem)) { in sljit_emit_mem()
1230 if (regs[1] == OFFS_REG(mem)) in sljit_emit_mem()
1244 reg = regs[reg_idx]; in sljit_emit_mem()
H A DsljitNativeX86_64.c947 sljit_u8 regs[2]; in sljit_emit_mem() local
971 regs[0] = U8(REG_PAIR_FIRST(reg)); in sljit_emit_mem()
972 regs[1] = U8(REG_PAIR_SECOND(reg)); in sljit_emit_mem()
976 if (!(type & SLJIT_MEM_STORE) && (regs[0] == (mem & REG_MASK) || regs[0] == OFFS_REG(mem))) { in sljit_emit_mem()
977 if (regs[1] == (mem & REG_MASK) || regs[1] == OFFS_REG(mem)) { in sljit_emit_mem()
981 if (regs[1] == OFFS_REG(mem)) in sljit_emit_mem()
995 reg = regs[reg_idx]; in sljit_emit_mem()
/third_party/mesa3d/src/amd/compiler/
H A Daco_register_allocation.cpp252 RegisterFile() { regs.fill(0); } in RegisterFile()
254 std::array<uint32_t, 512> regs; member in aco::__anon6956::RegisterFile
257 const uint32_t& operator[](PhysReg index) const { return regs[index]; } in operator []()
259 uint32_t& operator[](PhysReg index) { return regs[index]; } in operator []()
265 res += !regs[reg]; in count_zero()
274 if (regs[i] & 0x0FFFFFFF) in test()
276 if (regs[i] == 0xF0000000) { in test()
297 if (regs[start] == 0xFFFFFFFF) in is_blocked()
299 if (regs[start] == 0xF0000000) { in is_blocked()
311 if (regs[star in is_empty_or_blocked()
420 PhysRegInterval regs = get_reg_bounds(ctx.program, vgprs ? RegType::vgpr : RegType::sgpr); print_regs() local
1682 const PhysRegInterval regs = get_reg_bounds(ctx.program, info.rc.type()); get_reg() local
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/third_party/musl/arch/microblaze/
H A Dpthread_arch.h8 #define MC_PC regs.pc
/device/soc/rockchip/common/sdk_linux/drivers/tty/serial/8250/
H A D8250_dw.c497 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); in dw8250_probe() local
505 if (!regs) { in dw8250_probe()
516 p->mapbase = regs->start; in dw8250_probe()
529 p->membase = devm_ioremap(dev, regs->start, resource_size(regs)); in dw8250_probe()
/third_party/musl/arch/aarch64/bits/
H A Duser.h2 unsigned long long regs[31]; member
/device/soc/rockchip/common/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd_wifi6/
H A Dhndlhl.c530 lhl_reg_set_t *regs = lv_sleep_mode_4369_lhl_reg_set; in si_set_lv_sleep_mode_lhl_config_4369() local
536 si_corereg(sih, coreidx, regs[i].offset, regs[i].mask, regs[i].val); in si_set_lv_sleep_mode_lhl_config_4369()
H A Ddhd_sdio.c487 R_SDREG(intstatuserr, &bus->regs->intstatus, retries); \
1518 sdpcmd_regs_t *regs = bus->regs; in dhdsdio_bussleep() local
1574 W_SDREG(SMB_USE_OOB, &regs->tosbmailbox, retries); in dhdsdio_bussleep()
1590 W_SDREG(SMB_USE_OOB, &regs->tosbmailbox, retries); in dhdsdio_bussleep()
1623 W_SDREG(0, &regs->tosbmailboxdata, retries); in dhdsdio_bussleep()
1625 W_SDREG(SMB_DEV_INT, &regs->tosbmailbox, retries); in dhdsdio_bussleep()
1642 W_SDREG(0, &regs->tosbmailboxdata, retries); in dhdsdio_bussleep()
1644 W_SDREG(SMB_DEV_INT, &regs->tosbmailbox, retries); in dhdsdio_bussleep()
1796 sdpcmd_regs_t *regs in dhd_enable_oob_intr()
2442 sdpcmd_regs_t *regs = bus->regs; dhdsdio_sendfromq() local
5202 sdpcmd_regs_t *regs = bus->regs; dhdsdio_rxfail() local
6561 sdpcmd_regs_t *regs = bus->regs; dhdsdio_hostmail() local
6666 sdpcmd_regs_t *regs = bus->regs; dhdsdio_dpc() local
9904 sdpcmd_regs_t *regs = bus->regs; dhd_enableOOB() local
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/third_party/mesa3d/src/imagination/vulkan/pds/
H A Dpvr_pds_printer.c43 static const char *const regs[][2] = { PVR_PDS_OPERAND_TYPES }; in pvr_pds_disassemble_operand() local
50 regs[op->type][0], in pvr_pds_disassemble_operand()
58 regs[op->type][0], in pvr_pds_disassemble_operand()
60 regs[op->type][1]); in pvr_pds_disassemble_operand()
/device/soc/rockchip/rk3568/hardware/mpp/mpp/legacy/inc/
H A Dmpp_dec_cb_param.h37 RK_U32 *regs; member
/third_party/mesa3d/src/imagination/vulkan/winsys/pvrsrvkm/fw-api/
H A Dpvr_rogue_fwif_rf.h43 struct rogue_fwif_rf_regs ALIGN_ATTR(8) regs; member
/third_party/musl/arch/mips/bits/
H A Duser.h2 unsigned long regs[45+64]; member
/third_party/musl/arch/mips64/bits/
H A Duser.h2 unsigned long regs[102]; member
/third_party/musl/arch/or1k/
H A Dpthread_arch.h16 #define MC_PC regs.pc
/third_party/musl/arch/mipsn32/bits/
H A Duser.h2 unsigned long regs[102]; member
/device/soc/rockchip/common/sdk_linux/drivers/gpu/drm/rockchip/
H A Drockchip_drm_vop2.c65 if ((win)->regs->cluster) \
66 REG_SET(x, name, 0, (win)->regs->cluster->name, v, true); \
71 if ((win)->regs->afbc) \
72 REG_SET(x, name, (win)->offset, (win)->regs->afbc->name, v, true); \
77 #define VOP_SCL_SET(x, win, name, v) REG_SET(x, name, (win)->offset, (win)->regs->scl->name, v, true)
85 #define VOP_MODULE_SET(vop2, module, name, v) REG_SET(vop2, name, 0, (module)->regs->name, v, false)
103 #define VOP_MODULE_GET(x, module, name) vop2_read_reg((x), 0, &(module)->regs->name)
107 #define VOP_WIN_NAME(win, name) (vop2_get_win_regs((win), &(win)->regs->name)->name)
384 const struct vop2_win_regs *regs; member
412 const struct vop2_layer_regs *regs; member
427 const struct vop2_wb_regs *regs; global() member
446 const struct vop2_dsc_regs *regs; global() member
476 const struct vop2_video_port_regs *regs; global() member
661 void __iomem *regs; global() member
1015 const struct vop2_video_port_regs *regs = vp->regs; vop2_load_hdr2sdr_table() local
1038 const struct vop2_video_port_regs *regs = vp->regs; vop2_load_sdr2hdr_table() local
4747 } regs[] = { vop2_crtc_regs_dump() local
8509 const struct vop2_win_regs *regs = win_data->area[j]; vop2_win_init() local
[all...]
H A Dinno_hdmi.c56 void __iomem *regs; member
133 return readl_relaxed(hdmi->regs + (offset)*0x04); in hdmi_readb()
138 writel_relaxed(val, hdmi->regs + (offset)*0x04); in hdmi_writeb()
780 hdmi->regs = devm_ioremap_resource(dev, iores); in inno_hdmi_bind()
781 if (IS_ERR(hdmi->regs)) { in inno_hdmi_bind()
782 return PTR_ERR(hdmi->regs); in inno_hdmi_bind()
H A Drk3066_hdmi.c47 void __iomem *regs; member
65 return readl_relaxed(hdmi->regs + offset); in hdmi_readb()
70 writel_relaxed(val, hdmi->regs + offset); in hdmi_writeb()
727 hdmi->regs = devm_platform_ioremap_resource(pdev, 0); in rk3066_hdmi_bind()
728 if (IS_ERR(hdmi->regs)) { in rk3066_hdmi_bind()
729 return PTR_ERR(hdmi->regs); in rk3066_hdmi_bind()
/device/soc/rockchip/rk3588/kernel/drivers/gpu/drm/rockchip/
H A Drockchip_drm_vop2.c67 if (win->regs->cluster) \
68 REG_SET(x, name, 0, win->regs->cluster->name, v, true); \
73 if (win->regs->afbc) \
74 REG_SET(x, name, win->offset, win->regs->afbc->name, v, true); \
81 REG_SET(x, name, win->offset, win->regs->scl->name, v, true)
93 REG_SET(vop2, name, 0, module->regs->name, v, false)
114 vop2_read_reg(x, 0, &module->regs->name)
120 (vop2_get_win_regs(win, &win->regs->name)->name)
400 const struct vop2_win_regs *regs; member
428 const struct vop2_layer_regs *regs; member
444 const struct vop2_wb_regs *regs; global() member
464 const struct vop2_dsc_regs *regs; global() member
495 const struct vop2_video_port_regs *regs; global() member
685 void __iomem *regs; global() member
1028 const struct vop2_video_port_regs *regs = vp->regs; vop2_load_hdr2sdr_table() local
1051 const struct vop2_video_port_regs *regs = vp->regs; vop2_load_sdr2hdr_table() local
4758 } regs[] = { vop2_crtc_regs_dump() local
8619 const struct vop2_win_regs *regs = win_data->area[j]; vop2_win_init() local
[all...]
/third_party/mesa3d/src/nouveau/codegen/
H A Dnv50_ir_ra.cpp66 // for regs of size >= 4, id is counted in 4-byte words (like nv50/c0 binary)
381 if (begin != end) // empty ranges are only added as hazards for fixed regs in addLiveRange()
710 if (i->getDef(d)->reg.data.id >= 0) // add hazard for fixed regs in visit()
727 if (it->get()->reg.data.id >= 0) // add hazard for fixed regs in visit()
854 RegisterSet regs; member in nv50_ir::GCRA
922 GCRA::RIG_Node::init(const RegisterSet& regs, LValue *lval) in init() argument
928 colors = regs.units(lval->reg.file, lval->reg.size); in init()
932 reg = regs.idToUnits(lval); in init()
936 maxReg = regs.getFileSize(f); in init()
939 if (regs in init()
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/device/soc/rockchip/common/sdk_linux/include/linux/soc/rockchip/
H A Drk_fiq_debugger.h6 void fiq_debugger_fiq(void *regs, u32 cpu);
/device/soc/rockchip/rk3588/kernel/include/linux/soc/rockchip/
H A Drk_fiq_debugger.h6 void fiq_debugger_fiq(void *regs, u32 cpu);
/third_party/musl/arch/loongarch64/bits/
H A Duser.h5 unsigned long regs[32]; member
/third_party/ffmpeg/libavcodec/ppc/
H A Dfft_altivec.S338 .macro lvm b, r, regs:vararg
341 .ifnb \regs
342 lvm \b, \regs
346 .macro stvm b, r, regs:vararg
349 .ifnb \regs
350 stvm \b, \regs

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