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/third_party/node/deps/v8/src/libsampler/
H A Dsampler.cc348 static void FillRegisterState(void* context, RegisterState* regs);
407 state->fp = reinterpret_cast<void*>(mcontext.regs[29]); in FillRegisterState()
409 state->lr = reinterpret_cast<void*>(mcontext.regs[30]); in FillRegisterState()
424 state->pc = reinterpret_cast<void*>(ucontext->uc_mcontext.regs->nip); in FillRegisterState()
425 state->sp = reinterpret_cast<void*>(ucontext->uc_mcontext.regs->gpr[PT_R1]); in FillRegisterState()
426 state->fp = reinterpret_cast<void*>(ucontext->uc_mcontext.regs->gpr[PT_R31]); in FillRegisterState()
427 state->lr = reinterpret_cast<void*>(ucontext->uc_mcontext.regs->link); in FillRegisterState()
429 // Some C libraries, notably Musl, define the regs member as a void pointer in FillRegisterState()
/third_party/ltp/testcases/kernel/device-drivers/usb/tusb/
H A Dst_tusb.h58 void *regs; /* device memory/io */ member
61 int region; /* pci region for regs */
73 void (*irq) (struct usb_hcd *hcd, struct pt_regs *regs);
/third_party/mesa3d/src/imagination/vulkan/
H A Dpvr_job_compute.c55 pvr_csb_pack (&submit_info->regs.cdm_ctx_state_base_addr, in pvr_compute_job_ws_submit_info_init()
62 pvr_csb_pack (&submit_info->regs.cdm_resume_pds1, in pvr_compute_job_ws_submit_info_init()
/third_party/libunwind/libunwind/src/riscv/
H A DGinit.c54 unw_word_t *regs = (unw_word_t*)&uc->uc_mcontext; in uc_addr() local
56 return &regs[reg]; in uc_addr()
59 unw_fpreg_t *fpregs = (unw_fpreg_t*)(regs + 32); in uc_addr()
63 return &regs[0]; in uc_addr()
/third_party/mesa3d/src/amd/registers/
H A Dparse_kernel_headers.py706 regs = {}
731 regs[name] = {
750 if name not in regs.keys():
801 for (name, reg) in regs.items():
/third_party/mesa3d/src/imagination/vulkan/winsys/
H A Dpvr_winsys.h289 struct pvr_winsys_transfer_regs regs; member
316 } regs; member
366 } regs; member
395 } regs; member
/third_party/backends/backend/genesys/
H A Dgl847.cpp36 static unsigned gl847_get_step_multiplier (Genesys_Register_Set * regs) in gl847_get_step_multiplier() argument
38 unsigned value = (regs->get8(0x9d) & 0x0f) >> 1; in gl847_get_step_multiplier()
271 for (const auto& reg : dev->frontend.regs) { in set_fe()
812 Genesys_Register_Set& regs) const in init_regs_for_shading()
870 init_regs_for_scan_session(dev, calib_sensor, &regs, session); in init_regs_for_shading()
949 Genesys_Register_Set& regs) const in led_calibration()
951 return scanner_led_calibration(*dev, sensor, regs); in led_calibration()
962 apply_registers_ordered(dev->gpo.regs, {0xa6, 0xa7, 0x6f, 0x6e}, in gl847_init_gpio()
972 dev->interface->write_register(addr, dev->gpo.regs.find_reg(addr).value); in gl847_init_gpio()
978 dev->interface->write_register(addr, dev->gpo.regs in gl847_init_gpio()
1155 coarse_gain_calibration(Genesys_Device* dev, const Genesys_Sensor& sensor, Genesys_Register_Set& regs, int dpi) const coarse_gain_calibration() argument
[all...]
H A Dgl124.cpp372 dev->interface->write_fe_register(addr, dev->frontend.regs.get_value(addr)); in gl124_set_ti_fe()
380 dev->interface->write_fe_register(0x05 + i, dev->frontend.regs.get_value(0x24 + i)); in gl124_set_ti_fe()
921 Genesys_Register_Set& regs) const in init_regs_for_shading()
961 init_regs_for_scan_session(dev, calib_sensor, &regs, session); in init_regs_for_shading()
963 catch_all_exceptions(__func__, [&](){ sanei_genesys_set_motor_power(regs, false); }); in init_regs_for_shading()
966 sanei_genesys_set_motor_power(regs, false); in init_regs_for_shading()
1062 Genesys_Register_Set& regs) in move_to_calibration_area()
1074 regs = dev->reg; in move_to_calibration_area()
1097 dev->cmd_set->init_regs_for_scan_session(dev, move_sensor, &regs, session); in move_to_calibration_area()
1100 dev->interface->write_registers(regs); in move_to_calibration_area()
1061 move_to_calibration_area(Genesys_Device* dev, const Genesys_Sensor& sensor, Genesys_Register_Set& regs) move_to_calibration_area() argument
1138 coarse_gain_calibration(Genesys_Device* dev, const Genesys_Sensor& sensor, Genesys_Register_Set& regs, int dpi) const coarse_gain_calibration() argument
[all...]
H A Dgl842.cpp242 for (const auto& reg : dev->frontend.regs) { in set_fe()
252 dev->interface->write_fe_register(i, dev->frontend.regs.get_value(0x00 + i)); in set_fe()
757 Genesys_Register_Set& regs) const in init_regs_for_shading()
831 init_regs_for_scan_session(dev, calib_sensor, &regs, session); in init_regs_for_shading()
865 Genesys_Register_Set& regs) const in led_calibration()
867 return scanner_led_calibration(*dev, sensor, regs); in led_calibration()
871 Genesys_Register_Set& regs) const in offset_calibration()
873 scanner_offset_calibration(*dev, sensor, regs); in offset_calibration()
877 Genesys_Register_Set& regs, int dpi) const in coarse_gain_calibration()
879 scanner_coarse_gain_calibration(*dev, sensor, regs, dp in coarse_gain_calibration()
876 coarse_gain_calibration(Genesys_Device* dev, const Genesys_Sensor& sensor, Genesys_Register_Set& regs, int dpi) const coarse_gain_calibration() argument
[all...]
/third_party/mesa3d/src/amd/vulkan/
H A Dradv_spm.c79 struct ac_pc_block_base *regs = block_sel->b->b->b; in radv_emit_spm_counters() local
89 radeon_set_uconfig_reg_seq(cs, regs->select0[c], 1); in radv_emit_spm_counters()
92 radeon_set_uconfig_reg_seq(cs, regs->select1[c], 1); in radv_emit_spm_counters()
H A Dradv_debug.c970 struct radv_sq_hw_reg *regs = (struct radv_sq_hw_reg *)&device->tma_ptr[6]; in radv_dump_sq_hw_regs() local
975 regs->status, ~0); in radv_dump_sq_hw_regs()
977 regs->trap_sts, ~0); in radv_dump_sq_hw_regs()
979 regs->hw_id, ~0); in radv_dump_sq_hw_regs()
981 regs->ib_sts, ~0); in radv_dump_sq_hw_regs()
984 regs->status, ~0); in radv_dump_sq_hw_regs()
986 regs->trap_sts, ~0); in radv_dump_sq_hw_regs()
988 regs->hw_id, ~0); in radv_dump_sq_hw_regs()
990 regs->ib_sts, ~0); in radv_dump_sq_hw_regs()
/third_party/mesa3d/src/panfrost/bifrost/valhall/
H A Dasm.py185 regs = [parse_int(x[1:], 0, 63) for x in parts]
190 sr_count = len(regs)
193 base = regs[0] if len(regs) > 0 else 0
194 die_if(any([reg != (base + i) for i, reg in enumerate(regs)]),
/third_party/mesa3d/src/gallium/auxiliary/gallivm/
H A Dlp_bld_tgsi_info.c254 /* We don't track insts with additional regs, although we could */ in analyse_sample()
289 struct lp_tgsi_channel_info (*regs)[4]; in analyse_instruction()
304 regs = ctx->temp; in analyse_instruction()
307 regs = info->output; in analyse_instruction()
385 regs[index][chan].file = TGSI_FILE_NULL; in analyse_instruction()
431 regs[dst->Index][chan] = res[chan]; in analyse_instruction()
/third_party/node/deps/v8/src/codegen/arm64/
H A Dmacro-assembler-arm64.h1762 inline void PushXRegList(RegList regs) { in PushXRegList() argument
1763 PushSizeRegList(regs, kXRegSizeInBits); in PushXRegList()
1765 inline void PopXRegList(RegList regs) { in PopXRegList() argument
1766 PopSizeRegList(regs, kXRegSizeInBits); in PopXRegList()
1768 inline void PushWRegList(RegList regs) { in PushWRegList() argument
1769 PushSizeRegList(regs, kWRegSizeInBits); in PushWRegList()
1771 inline void PopWRegList(RegList regs) { in PopWRegList() argument
1772 PopSizeRegList(regs, kWRegSizeInBits); in PopWRegList()
1774 inline void PushQRegList(DoubleRegList regs) { in PushQRegList() argument
1775 PushSizeRegList(regs, kQRegSizeInBit in PushQRegList()
1777 PopQRegList(DoubleRegList regs) PopQRegList() argument
1780 PushDRegList(DoubleRegList regs) PushDRegList() argument
1783 PopDRegList(DoubleRegList regs) PopDRegList() argument
1786 PushSRegList(DoubleRegList regs) PushSRegList() argument
1789 PopSRegList(DoubleRegList regs) PopSRegList() argument
[all...]
/third_party/backends/backend/
H A Dsm3840_lib.h84 static void write_regs (p_usb_dev_handle udev, int regs, int reg1, int val1,
124 static void write_regs (p_usb_dev_handle udev, int regs, int reg1, int val1,
H A Dlexmark.h254 SANE_Byte * regs);
256 SANE_Byte * regs);
/third_party/libunwind/libunwind/include/
H A Dlibunwind-aarch64.h58 Calculation is regs used (64 + 34) * 2 + 40 (bytes of rest of
194 uint64_t regs[31]; member
237 register uint64_t unw_base __asm__ ("x0") = (uint64_t) unw_ctx->uc_mcontext.regs; \
/third_party/libunwind/libunwind/src/s390x/
H A DGstep.c51 gprs = ((struct sigcontext*)sc_addr)->sregs->regs.gprs; in s390x_handle_signal_frame()
53 psw = &((struct sigcontext*)sc_addr)->sregs->regs.psw.addr; in s390x_handle_signal_frame()
H A DGresume.c63 sc->sregs->regs.gprs[i-UNW_S390X_R0] = uc.uc_mcontext.gregs[i-UNW_S390X_R0]; in s390x_local_resume()
66 sc->sregs->regs.psw.addr = uc.uc_mcontext.psw.addr; in s390x_local_resume()
/third_party/mesa3d/src/freedreno/decode/scripts/
H A Danalyze.lua24 -- * regs - table of values for draw
69 local draw = {["primtype"] = primtype, ["regs"] = regtbl}
74 -- populate current regs. For now just consider ones that have
78 if regs.written(regbase) ~= 0 then
79 local regval = regs.val(regbase)
99 -- TODO maybe we want to whitelist a few well known regs, for the
/third_party/python/Modules/_sre/
H A Dsre.c1996 Py_VISIT(self->regs); in match_traverse()
2005 Py_CLEAR(self->regs); in match_clear()
2336 PyObject* regs; in match_regs() local
2340 regs = PyTuple_New(self->groups); in match_regs()
2341 if (!regs) in match_regs()
2347 Py_DECREF(regs); in match_regs()
2350 PyTuple_SET_ITEM(regs, index, item); in match_regs()
2353 Py_INCREF(regs); in match_regs()
2354 self->regs = regs; in match_regs()
[all...]
/third_party/vixl/src/aarch64/
H A Dregisters-aarch64.h989 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8};
991 for (size_t i = 0; i < ArrayLength(regs); i++) {
992 switch (regs[i].GetBank()) {
995 unique_regs |= regs[i].GetBit();
999 unique_vregs |= regs[i].GetBit();
1003 unique_pregs |= regs[i].GetBit();
1006 VIXL_ASSERT(regs[i].IsNone());
/third_party/ltp/testcases/kernel/kvm/
H A Dlib_host.c241 struct kvm_regs regs; in tst_kvm_run_instance() local
263 SAFE_IOCTL(inst->vcpu_fd, KVM_GET_REGS, &regs); in tst_kvm_run_instance()
266 regs.rip, inst->vcpu_info->exit_reason); in tst_kvm_run_instance()
/third_party/musl/arch/microblaze/
H A Dpthread_arch.h8 #define MC_PC regs.pc
/third_party/pcre2/pcre2/src/sljit/
H A DsljitNativeX86_32.c1210 sljit_u8 regs[2]; in sljit_emit_mem() local
1220 regs[0] = U8(REG_PAIR_FIRST(reg)); in sljit_emit_mem()
1221 regs[1] = U8(REG_PAIR_SECOND(reg)); in sljit_emit_mem()
1225 if (!(type & SLJIT_MEM_STORE) && (regs[0] == (mem & REG_MASK) || regs[0] == OFFS_REG(mem))) { in sljit_emit_mem()
1226 if (regs[1] == (mem & REG_MASK) || regs[1] == OFFS_REG(mem)) { in sljit_emit_mem()
1230 if (regs[1] == OFFS_REG(mem)) in sljit_emit_mem()
1244 reg = regs[reg_idx]; in sljit_emit_mem()

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