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/third_party/node/deps/v8/src/execution/mips/
H A Dsimulator-mips.cc917 void Simulator::set_register(int reg, int32_t value) { in set_register() argument
918 DCHECK((reg >= 0) && (reg < kNumSimuRegisters)); in set_register()
919 if (reg == pc) { in set_register()
924 registers_[reg] = (reg == 0) ? 0 : value; in set_register()
927 void Simulator::set_dw_register(int reg, const int* dbl) { in set_dw_register() argument
928 DCHECK((reg >= 0) && (reg < kNumSimuRegisters)); in set_dw_register()
929 registers_[reg] in set_dw_register()
983 get_double_from_register_pair(int reg) get_double_from_register_pair() argument
3692 int32_t reg = registers_[rt_reg()]; DecodeTypeRegisterCOP1() local
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/third_party/mesa3d/src/compiler/nir/tests/
H A Dnegative_equal_tests.cpp309 nir_register *reg = nir_local_reg_create(bld.impl); in TEST_F() local
310 nir_instr_rewrite_dest(&instr->instr, &instr->dest.dest, nir_dest_for_reg(reg)); in TEST_F()
/third_party/mesa3d/src/broadcom/compiler/
H A Dv3d40_tex.c241 (1 << instr->dest.reg.reg->num_components) - 1; in v3d40_vir_emit_tex()
H A Dnir_to_vir.c321 _mesa_set_add(c->tmu.outstanding_regs, dest->reg.reg); in ntq_add_pending_tmu_flush()
757 * If it's a NIR reg, then we need to update the existing qreg assigned to the
763 * its destination to be the NIR reg's destination
794 nir_register *reg = dest->reg.reg; in ntq_store_dest() local
795 assert(dest->reg.base_offset == 0); in ntq_store_dest()
796 assert(reg->num_array_elems == 0); in ntq_store_dest()
798 _mesa_hash_table_search(c->def_ht, reg); in ntq_store_dest()
860 nir_register *reg = src.reg.reg; ntq_get_src() local
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/third_party/mesa3d/src/gallium/drivers/radeonsi/
H A Dradeon_vcn_dec_jpeg.c57 static void set_reg_jpeg(struct radeon_decoder *dec, unsigned reg, unsigned cond, unsigned type, in set_reg_jpeg() argument
60 radeon_emit(&dec->jcs[dec->cb_idx], RDECODE_PKTJ(reg, cond, type)); in set_reg_jpeg()
/third_party/mesa3d/src/nouveau/codegen/
H A Dnv50_ir_target.cpp428 CodeEmitter::addInterp(int ipa, int reg, FixupApply apply) in addInterp() argument
444 fixupInfo->entry[n] = FixupEntry(apply, ipa, reg, codeSize >> 2); in addInterp()
H A Dnv50_ir_build_util.h237 lval->reg.size = size; in getScratch()
246 lval->reg.size = size; in getSSA()
H A Dnv50_ir_target_gv100.cpp337 if (targ->isCS2RSV(i->getSrc(0)->reg.data.sv.sv)) in getOpInfo()
480 if (ld->src(0).getFile() == FILE_IMMEDIATE && ld->getSrc(0)->reg.data.u64 == 0) in insnCanLoad()
505 if (ld->getSrc(0)->asImm()->reg.data.u64 & 0x00000000ffffffff) in insnCanLoad()
/third_party/node/deps/v8/src/snapshot/embedded/
H A Dembedded-data.cc211 Register reg = descriptor.GetRegisterParameter(i); in BuiltinAliasesOffHeapTrampolineRegister() local
212 if (reg == kOffHeapTrampolineRegister) return true; in BuiltinAliasesOffHeapTrampolineRegister()
/third_party/mesa3d/src/gallium/drivers/lima/ir/gp/
H A Dlower.c112 nload->reg = load->reg; in gpir_lower_load()
262 /* dummy_f/m are auxiliary nodes for value reg alloc: in gpir_lower_node_may_consume_two_slots()
263 * 1. before reg alloc, create fake nodes dummy_f, dummy_m, in gpir_lower_node_may_consume_two_slots()
267 * 2. After reg allocation and fake dep add, merge all deps of in gpir_lower_node_may_consume_two_slots()
270 * We may also not use dummy_f/m, but alloc two value reg for in gpir_lower_node_may_consume_two_slots()
279 * otherwise a move. And the node can be spilled with one reg. in gpir_lower_node_may_consume_two_slots()
/third_party/mesa3d/src/gallium/drivers/lima/ir/pp/
H A Dnode.c372 /* reg has 4 slots for each component write node */ in ppir_node_create()
375 snprintf(node->name, sizeof(node->name), "reg%d", index); in ppir_node_create()
524 printf("reg %d", dest->reg->index); in ppir_node_print_dest()
546 printf("reg %d", src->reg->index); in ppir_node_print_src()
/third_party/mesa3d/src/gallium/auxiliary/gallivm/
H A Dlp_bld_nir_aos.c170 const nir_reg_src *reg, in emit_load_reg()
182 const nir_reg_dest *reg, in emit_store_reg()
168 emit_load_reg(struct lp_build_nir_context *bld_base, struct lp_build_context *reg_bld, const nir_reg_src *reg, LLVMValueRef indir_src, LLVMValueRef reg_storage) emit_load_reg() argument
180 emit_store_reg(struct lp_build_nir_context *bld_base, struct lp_build_context *reg_bld, const nir_reg_dest *reg, unsigned writemask, LLVMValueRef indir_src, LLVMValueRef reg_storage, LLVMValueRef vals[NIR_MAX_VEC_COMPONENTS]) emit_store_reg() argument
/third_party/vk-gl-cts/external/vulkan-docs/src/xml/
H A DMakefile130 VKH_DEPENDS = $(VKXML) $(GENSCRIPT) $(SCRIPTS)/reg.py $(SCRIPTS)/generator.py
164 $(VIDEO_INCLUDE)/%.h: $(CODECXML) $(GENSCRIPT) $(SCRIPTS)/reg.py $(SCRIPTS)/generator.py
/third_party/skia/third_party/externals/swiftshader/src/OpenGL/libGLESv2/
H A DProgram.h109 LinkedVarying(const std::string &name, GLenum type, GLsizei size, int reg, int col);
117 int reg; // First varying register, assigned during link member
/third_party/skia/third_party/externals/spirv-cross/
H A Dspirv_cpp.cpp282 for (auto &reg : resource_registrations) in emit_resources()
283 statement(reg); in emit_resources()
/third_party/node/deps/v8/src/builtins/ia32/
H A Dbuiltins-ia32.cc2868 for (Register reg : wasm::kGpParamRegisters) { in Generate_WasmCompileLazy()
2869 __ Push(reg); in Generate_WasmCompileLazy()
2876 for (DoubleRegister reg : wasm::kFpParamRegisters) { in Generate_WasmCompileLazy()
2877 __ movdqu(Operand(esp, offset), reg); in Generate_WasmCompileLazy() local
2905 for (DoubleRegister reg : base::Reversed(wasm::kFpParamRegisters)) { in Generate_WasmCompileLazy()
2907 __ movdqu(reg, Operand(esp, offset)); in Generate_WasmCompileLazy()
2911 for (Register reg : base::Reversed(wasm::kGpParamRegisters)) { in Generate_WasmCompileLazy()
2912 __ Pop(reg); in Generate_WasmCompileLazy()
2927 for (Register reg : in Generate_WasmDebugBreak()
2929 __ Push(reg); in Generate_WasmDebugBreak()
2939 __ movdqu(Operand(esp, offset), reg); Generate_WasmDebugBreak() local
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/third_party/node/deps/v8/src/execution/riscv64/
H A Dsimulator-riscv64.cc2246 void Simulator::set_register(int reg, int64_t value) { in set_register() argument
2247 DCHECK((reg >= 0) && (reg < kNumSimuRegisters)); in set_register()
2248 if (reg == pc) { in set_register()
2253 registers_[reg] = (reg == 0) ? 0 : value; in set_register()
2256 void Simulator::set_dw_register(int reg, const int* dbl) { in set_dw_register() argument
2257 DCHECK((reg >= 0) && (reg < kNumSimuRegisters)); in set_dw_register()
2258 registers_[reg] in set_dw_register()
2312 get_double_from_register_pair(int reg) get_double_from_register_pair() argument
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/third_party/mesa3d/src/gallium/winsys/radeon/drm/
H A Dradeon_drm_winsys.c738 uint32_t reg = reg_offset + i*4; in radeon_read_registers() local
740 if (!radeon_get_drm_value(ws->fd, RADEON_INFO_READ_REG, NULL, &reg)) in radeon_read_registers()
742 out[i] = reg; in radeon_read_registers()
/third_party/mesa3d/src/intel/vulkan/
H A DgenX_state.c347 anv_batch_write_reg(&batch, GENX(HIZ_CHICKEN), reg) { in init_render_queue_state()
348 reg.HZDepthTestLEGEOptimizationDisable = true; in init_render_queue_state()
349 reg.HZDepthTestLEGEOptimizationDisableMask = true; in init_render_queue_state()
/third_party/node/deps/v8/src/codegen/loong64/
H A Dconstants-loong64.h81 static const char* Name(int reg);
87 int reg; member
103 static const char* Name(int reg);
/third_party/mesa3d/src/gallium/drivers/crocus/
H A Dcrocus_query.c253 uint32_t reg = index_to_reg[q->index]; in write_value() local
260 reg = GENX(CL_INVOCATION_COUNT_num); in write_value()
263 screen->vtbl.store_register_mem64(batch, reg, bo, offset, false); in write_value()
/third_party/node/deps/openssl/openssl/crypto/
H A Dsparccpuid.S39 call .walk.reg.wins
147 .walk.reg.wins:
155 call .walk.reg.wins
/third_party/openssl/crypto/
H A Dsparccpuid.S39 call .walk.reg.wins
147 .walk.reg.wins:
155 call .walk.reg.wins
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
H A DGCNRegBankReassign.cpp86 Candidate(MachineInstr *mi, unsigned reg, unsigned freebanks, in Candidate() argument
88 : MI(mi), Reg(reg), FreeBanks(freebanks), Weight(weight) {} in Candidate()
164 // Returns bank for a phys reg.
220 // Returns phys reg or NoRegister.
364 // the same phys reg within the same instruction.
592 const TargetRegisterClass *RC = MRI->getRegClass(LI.reg);
/third_party/toybox/generated/
H A Dglobals.h890 regex_t reg; member
1241 regex_t reg; member
1313 struct double_list *reg; member

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