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/third_party/vixl/src/aarch32/
H A Ddisasm-aarch32.h176 IndexedRegisterPrinter(DRegister reg, uint32_t index) in IndexedRegisterPrinter() argument
177 : reg_(reg), index_(index) {} in IndexedRegisterPrinter()
181 IndexedRegisterPrinter reg) { in operator <<()
182 return os << reg.GetReg() << "[" << reg.GetIndex() << "]"; in operator <<()
345 virtual DisassemblerStream& operator<<(Register reg) { in operator <<() argument
346 os_ << reg; in operator <<() local
349 virtual DisassemblerStream& operator<<(SRegister reg) { in operator <<() argument
350 os_ << reg; in operator <<() local
353 virtual DisassemblerStream& operator<<(DRegister reg) { in operator <<() argument
180 operator <<(std::ostream& os, IndexedRegisterPrinter reg) operator <<() argument
354 os_ << reg; operator <<() local
357 operator <<(QRegister reg) operator <<() argument
358 os_ << reg; operator <<() local
361 operator <<(const RegisterOrAPSR_nzcv reg) operator <<() argument
362 os_ << reg; operator <<() local
365 operator <<(SpecialRegister reg) operator <<() argument
366 os_ << reg; operator <<() local
369 operator <<(MaskedSpecialRegister reg) operator <<() argument
370 os_ << reg; operator <<() local
373 operator <<(SpecialFPRegister reg) operator <<() argument
374 os_ << reg; operator <<() local
377 operator <<(BankedRegister reg) operator <<() argument
378 os_ << reg; operator <<() local
397 operator <<(const DRegisterLane& reg) operator <<() argument
398 os_ << reg; operator <<() local
401 operator <<(const IndexedRegisterPrinter& reg) operator <<() argument
402 os_ << reg; operator <<() local
409 operator <<(CRegister reg) operator <<() argument
410 os_ << reg; operator <<() local
[all...]
/third_party/mesa3d/src/amd/compiler/
H A Daco_ir.h436 constexpr unsigned reg() const { return reg_b >> 2; } in reg() function
438 constexpr operator unsigned() const { return reg(); } in operator unsigned()
506 explicit Operand(Temp r, PhysReg reg) noexcept
511 setFixed(reg); variable
666 explicit Operand(PhysReg reg, RegClass type) noexcept
669 setFixed(reg); variable
766 constexpr void setFixed(PhysReg reg) noexcept
768 isFixed_ = reg != unsigned(-1);
769 reg_ = reg;
927 Definition(PhysReg reg, RegClas in temp() variable
[all...]
/third_party/mesa3d/src/amd/common/
H A Dac_shadowed_regs.h54 typedef void (*set_context_reg_seq_array_fn)(struct radeon_cmdbuf *cs, unsigned reg, unsigned num,
/third_party/mesa3d/src/intel/compiler/
H A Dbrw_vec4_vs.h47 virtual void emit_urb_slot(dst_reg reg, int varying);
/third_party/rust/crates/libc/src/unix/nto/
H A Daarch64.rs14 pub reg: [::aarch64_qreg_t; 32],
/third_party/vk-gl-cts/external/vulkan-docs/src/scripts/
H A DstripAPI.py8 from reg import stripNonmatchingAPIs
21 import reg
22 reg.stripNonmatchingAPIs(tree.getroot(), keepAPI, actuallyDelete=True)
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
H A DR600RegisterInfo.h32 unsigned getHWRegChan(unsigned reg) const;
/third_party/vixl/examples/aarch64/
H A Dcustom-disassembler.h49 const vixl::aarch64::CPURegister& reg) VIXL_OVERRIDE;
/third_party/vulkan-headers/registry/
H A DstripAPI.py8 from reg import stripNonmatchingAPIs
21 import reg
22 reg.stripNonmatchingAPIs(tree.getroot(), keepAPI, actuallyDelete=True)
/test/ostest/wukong/input_factory/src/
H A Drecord_input.cpp53 std::regex reg(delim); in split()
54 std::vector<std::string> res = {std::sregex_token_iterator(in.begin(), in.end(), reg, -1), in split()
/third_party/icu/icu4c/source/i18n/
H A Dtransreg.h418 Enumeration(const TransliteratorRegistry& reg);
427 const TransliteratorRegistry& reg; member in TransliteratorRegistry::Enumeration
/third_party/libunwind/libunwind/doc/
H A Dunw_set_reg.tex15 \Type{int} \Func{unw\_set\_reg}(\Type{unw\_cursor\_t~*}\Var{cp}, \Type{unw\_regnum\_t} \Var{reg}, \Type{unw\_word\_t} \Var{val});\\
20 \Var{reg} in the stack frame identified by cursor \Var{cp} to the
H A Dunw_get_fpreg.tex15 \Type{int} \Func{unw\_get\_fpreg}(\Type{unw\_cursor\_t~*}\Var{cp}, \Type{unw\_regnum\_t} \Var{reg}, \Type{unw\_fpreg\_t~*}\Var{valp});\\
20 register \Var{reg} in the stack frame identified by cursor \Var{cp}
H A Dunw_get_reg.tex15 \Type{int} \Func{unw\_get\_reg}(\Type{unw\_cursor\_t~*}\Var{cp}, \Type{unw\_regnum\_t} \Var{reg}, \Type{unw\_word\_t~*}\Var{valp});\\
20 \Var{reg} in the stack frame identified by cursor \Var{cp} and stores
H A Dunw_set_fpreg.tex15 \Type{int} \Func{unw\_set\_fpreg}(\Type{unw\_cursor\_t~*}\Var{cp}, \Type{unw\_regnum\_t} \Var{reg}, \Type{unw\_fpreg\_t} \Var{val});\\
20 \Var{reg} in the stack frame identified by cursor \Var{cp} to the
/third_party/mesa3d/src/gallium/drivers/radeonsi/
H A Dsi_cp_reg_shadowing.c183 static void si_set_context_reg_array(struct radeon_cmdbuf *cs, unsigned reg, unsigned num, in si_set_context_reg_array() argument
187 radeon_set_context_reg_seq(reg, num); in si_set_context_reg_array()
209 /* We need to clear the shadowed reg buffer. */ in si_init_cp_reg_shadowing()
/third_party/node/deps/icu-small/source/i18n/
H A Dtransreg.h418 Enumeration(const TransliteratorRegistry& reg);
428 const TransliteratorRegistry& reg; member in TransliteratorRegistry::Enumeration
/third_party/mesa3d/src/panfrost/bifrost/test/
H A Dtest-dual-texture.cpp66 reg = bi_register(0); in DualTexture()
78 bi_index reg, x, y; member in DualTexture
/third_party/mesa3d/src/panfrost/lib/
H A Dpan_shader.h106 #define pan_preloads(reg) (preload & BITFIELD64_BIT(reg))
H A Dpan_props.c254 unsigned reg = panfrost_query_raw(fd, in panfrost_query_afbc() local
258 return (arch >= 5) && (reg == 0); in panfrost_query_afbc()
/third_party/node/deps/v8/src/execution/
H A Dsimulator-base.h175 static void* ReverseRedirection(intptr_t reg) { in ReverseRedirection() argument
177 reinterpret_cast<Instruction*>(reinterpret_cast<void*>(reg))); in ReverseRedirection()
/third_party/node/deps/v8/src/interpreter/
H A Dbytecode-decoder.cc169 Register reg = in Decode() local
171 os << reg.ToString(); in Decode()
/third_party/mesa3d/src/gallium/drivers/freedreno/a6xx/
H A Dfd6_emit.h305 #define WRITE(reg, val) \
307 OUT_PKT4(ring, reg, 1); \
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
H A DBreakFalseDeps.cpp114 // Update only undef operands that have reg units that are mapped to one root. in pickBestRegisterForUndef()
165 Register reg = MI->getOperand(OpIdx).getReg(); in shouldBreakDependence() local
166 unsigned Clearance = RDA->getClearance(MI, reg); in shouldBreakDependence()
H A DRegAllocBasic.cpp230 if (!VRM->hasPhys(Spill.reg)) in spillInterferences()
262 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo, Matrix); in selectOrSplit()
281 // Try to spill another interfering reg with less spill weight. in selectOrSplit()

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