Home
last modified time | relevance | path

Searched refs:reg (Results 701 - 725 of 1118) sorted by relevance

1...<<21222324252627282930>>...45

/third_party/node/deps/v8/src/interpreter/
H A Dinterpreter-assembler.h112 TNode<Object> LoadRegister(Register reg);
113 TNode<IntPtrT> LoadAndUntagRegister(Register reg);
117 void StoreRegister(TNode<Object> value, Register reg);
306 TNode<IntPtrT> RegisterLocation(Register reg);
/third_party/node/deps/v8/src/regexp/
H A Dregexp-bytecode-generator.cc87 for (int reg = reg_from; reg <= reg_to; reg++) { in ClearRegisters()
88 SetRegister(reg, -1); in ClearRegisters()
/third_party/node/deps/v8/src/torque/ls/
H A Dmessage-handler.cc234 Registration reg = request.params().add_registrations(); in HandleInitializedNotification() local
236 reg.registerOptions<DidChangeWatchedFilesRegistrationOptions>(); in HandleInitializedNotification()
241 reg.set_id("did-change-id"); in HandleInitializedNotification()
242 reg.set_method("workspace/didChangeWatchedFiles"); in HandleInitializedNotification()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
H A DStackSlotColoring.cpp225 int FI = Register::stackSlot2Index(li.reg); in InitializeSlots()
272 int FI = Register::stackSlot2Index(li->reg); in ColorSlot()
334 int SS = Register::stackSlot2Index(li->reg); in ColorSlots()
347 int SS = Register::stackSlot2Index(li->reg); in ColorSlots()
H A DLiveIntervals.cpp188 LiveInterval* LiveIntervals::createInterval(unsigned reg) { in createInterval() argument
189 float Weight = Register::isPhysicalRegister(reg) ? huge_valf : 0.0F; in createInterval()
190 return new LiveInterval(reg, Weight); in createInterval()
198 LRCalc->calculate(LI, MRI->shouldTrackSubRegLiveness(LI.reg)); in computeVirtRegInterval()
318 LLVM_DEBUG(dbgs() << "Computing live-in reg-units in ABI blocks.\n"); in computeLiveInRegUnits()
449 assert(Register::isVirtualRegister(li->reg) && in shrinkToUses()
455 shrinkToUses(S, li->reg); in shrinkToUses()
465 // Visit all instructions reading li->reg. in shrinkToUses()
466 unsigned Reg = li->reg; in shrinkToUses()
519 unsigned VReg = LI.reg; in computeDeadValues()
879 addSegmentToEndOfBlock(unsigned reg, MachineInstr &startInst) addSegmentToEndOfBlock() argument
[all...]
/third_party/mesa3d/src/intel/compiler/
H A Dbrw_vec4_generator.cpp342 inst->base_mrf, /* starting mrf reg nr */ in generate_vs_urb_write()
357 inst->base_mrf, /* starting mrf reg nr */ in generate_gs_urb_write()
374 inst->base_mrf, /* starting mrf reg nr */ in generate_gs_urb_write_allocate()
397 inst->base_mrf, /* starting mrf reg nr */ in generate_gs_thread_end()
1021 inst->base_mrf, /* starting mrf reg nr */ in generate_tcs_thread_end()
1402 struct brw_reg dst, struct brw_reg reg, in generate_mov_indirect()
1408 unsigned imm_byte_offset = reg.nr * REG_SIZE + reg.subnr * (REG_SIZE / 2); in generate_mov_indirect()
1416 reg.nr = imm_byte_offset / REG_SIZE; in generate_mov_indirect()
1417 reg in generate_mov_indirect()
1400 generate_mov_indirect(struct brw_codegen *p, vec4_instruction *, struct brw_reg dst, struct brw_reg reg, struct brw_reg indirect) generate_mov_indirect() argument
[all...]
H A Dbrw_disasm.c832 reg(FILE *file, unsigned _reg_file, unsigned _reg_nr) in reg() function
887 err |= control(file, "src reg file", reg_file, _reg_file, NULL); in reg()
906 err |= reg(file, brw_inst_send_dst_reg_file(devinfo, inst), in dest()
910 err |= reg(file, brw_inst_send_dst_reg_file(devinfo, inst), in dest()
928 err |= reg(file, brw_inst_dst_reg_file(devinfo, inst), in dest()
955 err |= reg(file, brw_inst_dst_reg_file(devinfo, inst), in dest()
996 err |= reg(file, reg_file, brw_inst_3src_dst_reg_nr(devinfo, inst)); in dest_3src()
1056 err |= reg(file, _reg_file, reg_num); in src_da1()
1143 err |= reg(file, _reg_file, _reg_nr); in src_da16()
1322 err |= reg(fil in src0_3src()
[all...]
H A Dbrw_vec4_vs.h47 virtual void emit_urb_slot(dst_reg reg, int varying);
/third_party/mesa3d/src/freedreno/rnn/
H A Dcolors.h34 const char *reg; /* ISA register */ member
/third_party/musl/src/thread/powerpc/
H A D__set_thread_area.s8 # put 0 into return reg
/third_party/node/deps/v8/src/maglev/
H A Dmaglev-graph-builder.cc74 interpreter::Register reg = interpreter::Register::FromParameterIndex(i); in MaglevGraphBuilder() local
75 current_interpreter_frame_.set(reg, AddNewNode<InitialValue>({}, reg)); in MaglevGraphBuilder()
83 for (interpreter::Register& reg : regs) { in MaglevGraphBuilder()
84 current_interpreter_frame_.set(reg, AddNewNode<InitialValue>({}, reg)); in MaglevGraphBuilder()
/third_party/libunwind/libunwind/src/hppa/
H A DGget_save_loc.c29 unw_get_save_loc (unw_cursor_t *cursor, int reg, unw_save_loc_t *sloc) in unw_get_save_loc() argument
H A Dunwind_i.h44 extern dwarf_loc_t hppa_scratch_loc (struct cursor *c, unw_regnum_t reg);
/third_party/libunwind/libunwind/src/ppc64/
H A Dunwind_i.h49 extern dwarf_loc_t ppc64_scratch_loc (struct cursor *c, unw_regnum_t reg);
/third_party/ltp/testcases/kernel/syscalls/ptrace/
H A Dptrace.h12 # include <sys/reg.h>
/third_party/EGL/api/
H A Dreg.py745 self.reg = self.tree.getroot()
754 for type in self.reg.findall('types/type'):
766 for group in self.reg.findall('groups/group'):
776 for enum in self.reg.findall('enums/enum'):
786 for cmd in self.reg.findall('commands/command'):
798 for feature in self.reg.findall('feature'):
801 self.extensions = self.reg.findall('extensions/extension')
1139 for cmd in self.reg.findall('commands/command'):
/third_party/mesa3d/src/amd/compiler/
H A Daco_insert_waitcnt.cpp239 void wait_and_remove_from_entry(PhysReg reg, wait_entry& entry, counter_type counter) in wait_and_remove_from_entry()
267 PhysReg reg{op.physReg() + j}; in check_instr()
268 std::map<PhysReg, wait_entry>::iterator it = ctx.gpr_map.find(reg); in check_instr()
279 PhysReg reg{def.physReg() + j}; in check_instr()
281 std::map<PhysReg, wait_entry>::iterator it = ctx.gpr_map.find(reg); in check_instr()
582 insert_wait_entry(wait_ctx& ctx, PhysReg reg, RegClass rc, wait_event event, bool wait_on_read, in insert_wait_entry() argument
600 auto it = ctx.gpr_map.emplace(PhysReg{reg.reg() + i}, new_entry); in insert_wait_entry()
H A Daco_ir.h436 constexpr unsigned reg() const { return reg_b >> 2; } in reg() function
438 constexpr operator unsigned() const { return reg(); } in operator unsigned()
506 explicit Operand(Temp r, PhysReg reg) noexcept
511 setFixed(reg); variable
666 explicit Operand(PhysReg reg, RegClass type) noexcept
669 setFixed(reg); variable
766 constexpr void setFixed(PhysReg reg) noexcept
768 isFixed_ = reg != unsigned(-1);
769 reg_ = reg;
927 Definition(PhysReg reg, RegClas in temp() variable
[all...]
/third_party/openGLES/xml/
H A Dreg.py736 self.reg = self.tree.getroot()
745 for type in self.reg.findall('types/type'):
757 for group in self.reg.findall('groups/group'):
767 for enum in self.reg.findall('enums/enum'):
777 for cmd in self.reg.findall('commands/command'):
789 for feature in self.reg.findall('feature'):
792 self.extensions = self.reg.findall('extensions/extension')
1130 for cmd in self.reg.findall('commands/command'):
/third_party/skia/third_party/externals/opengl-registry/xml/
H A Dreg.py747 self.reg = self.tree.getroot()
756 for type in self.reg.findall('types/type'):
768 for group in self.reg.findall('groups/group'):
778 for enum in self.reg.findall('enums/enum'):
788 for cmd in self.reg.findall('commands/command'):
800 for feature in self.reg.findall('feature'):
803 self.extensions = self.reg.findall('extensions/extension')
1141 for cmd in self.reg.findall('commands/command'):
/third_party/skia/third_party/externals/egl-registry/api/
H A Dreg.py756 self.reg = self.tree.getroot()
765 for type in self.reg.findall('types/type'):
777 for group in self.reg.findall('groups/group'):
787 for enum in self.reg.findall('enums/enum'):
797 for cmd in self.reg.findall('commands/command'):
809 for feature in self.reg.findall('feature'):
812 self.extensions = self.reg.findall('extensions/extension')
1150 for cmd in self.reg.findall('commands/command'):
/third_party/alsa-lib/src/topology/
H A Dctl.c623 /* set channel reg to default state */ in tplg_parse_control_enum()
625 ec->channel[j].reg = -1; in tplg_parse_control_enum()
761 /* set channel reg to default state */ in tplg_parse_control_mixer()
763 mc->channel[j].reg = -1; in tplg_parse_control_mixer()
1011 /* set channel reg to default state */ in tplg_add_mixer()
1013 mc->channel[i].reg = -1; in tplg_add_mixer()
1022 mc->channel[i].reg = channel->reg; in tplg_add_mixer()
1075 /* set channel reg to default state */ in tplg_add_enum()
1077 ec->channel[i].reg in tplg_add_enum()
[all...]
/third_party/node/deps/v8/src/codegen/mips/
H A Dmacro-assembler-mips.h257 void Drop(int count, Condition cond = cc_always, Register reg = no_reg,
274 void DropAndRet(int drop, Condition cond, Register reg, const Operand& op);
470 void SmiUntag(Register reg) { sra(reg, reg, kSmiTagSize); } in SmiUntag() argument
969 // the tagged HeapObject pointer. For use with FieldOperand(reg, off).
1112 void SmiTag(Register reg) { Addu(reg, reg, reg); } in SmiTag() argument
1157 DecodeField(Register reg) DecodeField() argument
[all...]
/third_party/vixl/src/aarch32/
H A Ddisasm-aarch32.h176 IndexedRegisterPrinter(DRegister reg, uint32_t index) in IndexedRegisterPrinter() argument
177 : reg_(reg), index_(index) {} in IndexedRegisterPrinter()
181 IndexedRegisterPrinter reg) { in operator <<()
182 return os << reg.GetReg() << "[" << reg.GetIndex() << "]"; in operator <<()
345 virtual DisassemblerStream& operator<<(Register reg) { in operator <<() argument
346 os_ << reg; in operator <<() local
349 virtual DisassemblerStream& operator<<(SRegister reg) { in operator <<() argument
350 os_ << reg; in operator <<() local
353 virtual DisassemblerStream& operator<<(DRegister reg) { in operator <<() argument
180 operator <<(std::ostream& os, IndexedRegisterPrinter reg) operator <<() argument
354 os_ << reg; operator <<() local
357 operator <<(QRegister reg) operator <<() argument
358 os_ << reg; operator <<() local
361 operator <<(const RegisterOrAPSR_nzcv reg) operator <<() argument
362 os_ << reg; operator <<() local
365 operator <<(SpecialRegister reg) operator <<() argument
366 os_ << reg; operator <<() local
369 operator <<(MaskedSpecialRegister reg) operator <<() argument
370 os_ << reg; operator <<() local
373 operator <<(SpecialFPRegister reg) operator <<() argument
374 os_ << reg; operator <<() local
377 operator <<(BankedRegister reg) operator <<() argument
378 os_ << reg; operator <<() local
397 operator <<(const DRegisterLane& reg) operator <<() argument
398 os_ << reg; operator <<() local
401 operator <<(const IndexedRegisterPrinter& reg) operator <<() argument
402 os_ << reg; operator <<() local
409 operator <<(CRegister reg) operator <<() argument
410 os_ << reg; operator <<() local
[all...]
/third_party/mesa3d/src/amd/common/
H A Dac_shadowed_regs.h54 typedef void (*set_context_reg_seq_array_fn)(struct radeon_cmdbuf *cs, unsigned reg, unsigned num,

Completed in 30 milliseconds

1...<<21222324252627282930>>...45