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/third_party/mesa3d/src/gallium/drivers/svga/
H A Dsvga_tgsi_vgpu10.c304 unsigned out_index; /**< the real position output reg */
305 unsigned tmp_index; /**< the fake/temp position output reg */
306 unsigned so_index; /**< the non-adjusted position output reg */
337 unsigned color_tmp_index; /**< fake/temp color output reg */
341 unsigned face_input_index; /**< real fragment shader face reg (bool) */
342 unsigned face_tmp_index; /**< temp face reg converted to -1 / +1 */
347 unsigned fragcoord_input_index; /**< real fragment position input reg */
348 unsigned fragcoord_tmp_index; /**< 1/w modified position temp reg */
353 unsigned sample_pos_tmp_index; /**< which temp reg has the sample pos */
464 /* For all shaders: const reg inde
1269 emit_dst_register(struct svga_shader_emitter_v10 *emit, const struct tgsi_full_dst_register *reg) emit_dst_register() argument
1551 emit_src_register(struct svga_shader_emitter_v10 *emit, const struct tgsi_full_src_register *reg) emit_src_register() argument
2337 struct tgsi_full_src_register reg; make_src_reg() local
2357 struct tgsi_full_src_register reg; make_src_scalar_reg() local
2409 struct tgsi_full_dst_register reg; make_dst_reg() local
2443 negate_src(const struct tgsi_full_src_register *reg) negate_src() argument
2454 absolute_src(const struct tgsi_full_src_register *reg) absolute_src() argument
2464 get_swizzle(const struct tgsi_full_src_register *reg, enum tgsi_swizzle term) get_swizzle() argument
2486 swizzle_src(const struct tgsi_full_src_register *reg, enum tgsi_swizzle swizzleX, enum tgsi_swizzle swizzleY, enum tgsi_swizzle swizzleZ, enum tgsi_swizzle swizzleW) swizzle_src() argument
2505 scalar_src(const struct tgsi_full_src_register *reg, enum tgsi_swizzle swizzle) scalar_src() argument
2522 writemask_dst(const struct tgsi_full_dst_register *reg, unsigned mask) writemask_dst() argument
2534 same_swizzle_terms(const struct tgsi_full_src_register *reg) same_swizzle_terms() argument
2622 struct tgsi_full_src_register reg; make_immediate_reg_4() local
2670 struct tgsi_full_src_register reg; make_immediate_reg() local
2751 struct tgsi_full_src_register reg; make_immediate_reg_double() local
5591 unsigned total_temps, reg, i; emit_temporaries_declaration() local
9280 check_double_src(struct svga_shader_emitter_v10 *emit, const struct tgsi_full_src_register *reg) check_double_src() argument
10051 const struct tgsi_full_dst_register *reg = &inst->Dst[regIndex]; emit_memory_register() local
10060 const struct tgsi_full_src_register *reg = &inst->Src[regIndex]; emit_memory_register() local
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/third_party/cmsis/CMSIS/Core/Include/
H A Dcore_ca.h2720 \param [in] reg Section attributes
2724 __STATIC_INLINE int MMU_GetSectionDescriptor(uint32_t *descriptor, mmu_region_attributes_Type reg) in MMU_GetSectionDescriptor() argument
2728 MMU_MemorySection(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t); in MMU_GetSectionDescriptor()
2729 MMU_XNSection(descriptor,reg.xn_t); in MMU_GetSectionDescriptor()
2730 MMU_DomainSection(descriptor, reg.domain); in MMU_GetSectionDescriptor()
2731 MMU_PSection(descriptor, reg.e_t); in MMU_GetSectionDescriptor()
2732 MMU_APSection(descriptor, reg.user_t, reg in MMU_GetSectionDescriptor()
2751 MMU_GetPageDescriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg) MMU_GetPageDescriptor() argument
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/third_party/mesa3d/src/amd/compiler/
H A Daco_validate.cpp748 PhysReg reg; member
952 PhysReg reg = assignments[tmp.id()].reg; in validate_instr_defs() local
954 if (regs[reg.reg_b + j]) in validate_instr_defs()
956 ra_fail(program, loc, assignments[regs[reg.reg_b + j]].defloc, in validate_instr_defs()
958 tmp.id(), regs[reg.reg_b + j]); in validate_instr_defs()
959 regs[reg.reg_b + j] = tmp.id(); in validate_instr_defs()
965 for (unsigned j = reg.byte() & ~(written - 1); j < written; j++) { in validate_instr_defs()
966 unsigned written_reg = reg.reg() * in validate_instr_defs()
1094 PhysReg reg = assignments[id].reg; validate_ra() local
1112 PhysReg reg = assignments[tmp.id()].reg; validate_ra() local
1143 PhysReg reg = assignments[id].reg; validate_ra() local
1154 PhysReg reg = assignments[tmp.id()].reg; validate_ra() local
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/third_party/libunwind/libunwind/src/ppc64/
H A Dregname.c158 unw_regname (unw_regnum_t reg) in unw_regname() argument
160 if (reg < (unw_regnum_t) ARRAY_SIZE (regname)) in unw_regname()
161 return regname[reg]; in unw_regname()
/third_party/mesa3d/src/gallium/drivers/etnaviv/
H A Detnaviv_compiler.h61 int reg; /* native register */ member
68 struct etna_shader_inout reg[ETNA_NUM_INPUTS]; member
139 uint8_t reg; member
143 /* each PS input is annotated with the VS output reg */
/third_party/mesa3d/src/nouveau/codegen/
H A Dnv50_ir_emit_gm107.cpp243 emitField(16, 3, insn->getSrc(insn->predSrc)->rep()->reg.data.id); in emitPred()
263 val->reg.data.id : 255); in emitGPR()
269 int id = val ? val->reg.data.id : -1; in emitSYS()
278 case SV_TID : id = 0x21 + val->reg.data.sv.index; break; in emitSYS()
279 case SV_CTAID : id = 0x25 + val->reg.data.sv.index; break; in emitSYS()
285 case SV_CLOCK : id = 0x50 + val->reg.data.sv.index; break; in emitSYS()
298 emitField(pos, 3, val ? val->reg.data.id : 7); in emitPRED()
306 assert(!(v->reg.data.offset & ((1 << shr) - 1))); in emitADDR()
309 emitField(off, len, v->reg.data.offset >> shr); in emitADDR()
319 assert(!(s->reg in emitCBUF()
2572 int reg = entry->reg; gm107_interpApply() local
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/third_party/node/deps/v8/src/codegen/x64/
H A Dassembler-x64.h244 // Does not check the "reg" part of the Operand.
245 bool AddressUsesRegister(Register reg) const;
379 // Distance between the address of the imm64 in the 'movq reg, imm64'
650 void testb(Register reg, Operand op) { testb(op, reg); } in testb() argument
652 void testw(Register reg, Operand op) { testw(op, reg); } in testw() argument
664 void xchgb(Register reg, Operand op);
665 void xchgw(Register reg, Operand op);
672 void negb(Register reg);
978 sse2_instr(XMMRegister reg, byte imm8, byte prefix, byte escape, byte opcode, int extension) sse2_instr() argument
2246 emit_operand(Register reg, Operand adr) emit_operand() argument
2256 emit_modrm(Register reg, Register rm_reg) emit_modrm() argument
2474 emit_test(Register reg, Operand op, int size) emit_test() argument
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/third_party/node/deps/v8/src/diagnostics/x64/
H A Ddisasm-x64.cc286 const char* NameOfYMMRegister(int reg);
427 const char* NameOfCPURegister(int reg) const { in NameOfCPURegister()
428 return converter_.NameOfCPURegister(reg); in NameOfCPURegister()
431 const char* NameOfByteCPURegister(int reg) const { in NameOfByteCPURegister()
432 return converter_.NameOfByteCPURegister(reg); in NameOfByteCPURegister()
435 const char* NameOfXMMRegister(int reg) const { in NameOfXMMRegister()
436 return converter_.NameOfXMMRegister(reg); in NameOfXMMRegister()
439 const char* NameOfAVXRegister(int reg) const { in NameOfAVXRegister()
441 return NameOfYMMRegister(reg); in NameOfAVXRegister()
443 return converter_.NameOfXMMRegister(reg); in NameOfAVXRegister()
2097 int reg = (opcode - 0xC8) | (rex_r() ? 8 : 0); TwoByteOpcodeInstruction() local
2593 int reg = (*data & 0x7) | (rex_b() ? 8 : 0); InstructionDecode() local
2624 int reg = (opcode & 0x7) | (rex_b() ? 8 : 0); InstructionDecode() local
2823 NameOfYMMRegister(int reg) NameOfYMMRegister() argument
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/device/soc/hisilicon/common/platform/mmc/himci_v200/proc/
H A Dhimci_proc.c175 speedClass = dev->reg.ssr.speedClass; in ProcStatsSpeedPrint()
176 uhsSpeedGrade = dev->reg.ssr.uhsSpeedGrade; in ProcStatsSpeedPrint()
244 card->reg.rawCid[0], card->reg.rawCid[1], card->reg.rawCid[2], card->reg.rawCid[3]); in ProcStatsCidPrint()
/device/soc/hisilicon/common/platform/mmc/sdhci/proc/
H A Dsdhci_proc.c174 speedClass = dev->reg.ssr.speedClass; in ProcStatsSpeedPrint()
175 uhsSpeedGrade = dev->reg.ssr.uhsSpeedGrade; in ProcStatsSpeedPrint()
243 card->reg.rawCid[0], card->reg.rawCid[1], card->reg.rawCid[2], card->reg.rawCid[3]); in ProcStatsCidPrint()
/device/soc/hisilicon/common/platform/mmc/himci_v200/
H A Dhimci.h97 #define HIMCI_CLEARL(host, reg, v) OSAL_WRITEL(OSAL_READL((uintptr_t)(host)->base + (reg)) & (~(v)), \
98 (uintptr_t)(host)->base + (reg));
100 #define HIMCI_SETL(host, reg, v) OSAL_WRITEL(OSAL_READL((uintptr_t)(host)->base + (reg)) | (v), \
101 (uintptr_t)(host)->base + (reg));
124 #define REG_CTRL_EMMC_START IO_DEVICE_ADDR(0x10ff0000 + 0x0) /* eMMC pad ctrl reg */
125 #define REG_CTRL_SD_START IO_DEVICE_ADDR(0x10ff0000 + 0x24) /* sd pad ctrl reg */
126 #define REG_CTRL_SDIO_START IO_DEVICE_ADDR(0x112f0000 + 0x8) /* sdio pad ctrl reg */
/third_party/ffmpeg/compat/cuda/
H A Dcuda_runtime.h90 #define GETCOMP(reg, comp) \
91 asm("mov.u32 %0, %%" #reg "." #comp ";" : "=r"(tmp)); \
94 #define GET(name, reg) static inline __device__ uint3 name() {\
97 GETCOMP(reg, x) \
98 GETCOMP(reg, y) \
99 GETCOMP(reg, z) \
/third_party/mesa3d/src/gallium/drivers/r600/sfn/
H A Dsfn_liverangeevaluator_helpers.cpp642 RegisterCompAccess& RegisterAccess::operator() (const Register& reg) in operator ()() argument
644 assert(reg.chan() < 4); in operator ()()
645 assert(m_access_record[reg.chan()].size() > (size_t)reg.index()); in operator ()()
646 return m_access_record[reg.chan()][reg.index()]; in operator ()()
/third_party/mesa3d/src/gallium/drivers/freedreno/
H A Dfreedreno_util.h230 #define CP_REG(reg) ((0x4 << 16) | ((unsigned int)((reg) - (0x2000))))
404 unsigned reg = REG_AXXX_CP_SCRATCH_REG0 + scratch_idx; in emit_marker() local
405 assert(reg != HW_QUERY_BASE_REG); in emit_marker()
406 if (reg == HW_QUERY_BASE_REG) in emit_marker()
410 OUT_PKT0(ring, reg, 1); in emit_marker()
/third_party/mesa3d/src/panfrost/util/
H A Dpan_ir.h469 assert(!src->reg.indirect); in pan_src_index()
470 return (src->reg.reg->index << 1) | PAN_IS_REG; in pan_src_index()
480 assert(!dst->reg.indirect); in pan_dest_index()
481 return (dst->reg.reg->index << 1) | PAN_IS_REG; in pan_dest_index()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
H A DGCNNSAReassign.cpp117 if (VRM->hasPhys(Intervals[N]->reg)) in tryAssignRegisters()
299 dbgs() << " " << llvm::printReg((VRM->getPhys(LI->reg)), TRI); in runOnMachineFunction()
305 if (VRM->hasPhys(Intervals.back()->reg)) // Did not change allocation. in runOnMachineFunction()
324 if (VRM->hasPhys(Intervals[I]->reg)) in runOnMachineFunction()
336 << llvm::printReg((VRM->getPhys(Intervals.front()->reg)), TRI) in runOnMachineFunction()
338 << llvm::printReg((VRM->getPhys(Intervals.back()->reg)), TRI) in runOnMachineFunction()
/third_party/vulkan-loader/scripts/
H A Dloader_genvk.py366 from reg import *
398 reg = Registry(gen, options) variable
407 reg.loadElementTree(tree)
411 reg.validateGroups()
415 reg.dumpReg(filehandle = open('regdump.txt', 'w', encoding='utf-8'))
419 pdb.run('reg.apiGen()')
422 reg.apiGen()
/device/soc/hisilicon/hi3861v100/sdk_liteos/app/demo/src/
H A Des8311_codec.c28 hi_u32 codec_write_reg(hi_u8 reg, hi_u8 val) in codec_write_reg() argument
31 hi_u8 send_data[2] = { reg, val }; /* size 2 */ in codec_write_reg()
39 hi_u32 codec_read_reg(hi_u8 reg, hi_u8 *val) in codec_read_reg() argument
43 i2c_data.send_buf = (hi_u8*)&reg; in codec_read_reg()
/device/soc/rockchip/common/vendor/drivers/rockchip/
H A Dgrf.c19 u32 reg; member
233 pr_debug("%s: adjusting %s in %#6x to %#10x\n", __func__, val->desc, val->reg, val->val); in rockchip_grf_init()
234 ret = regmap_write(grf, val->reg, val->val); in rockchip_grf_init()
236 pr_err("%s: write to %#6x failed with %d\n", __func__, val->reg, ret); in rockchip_grf_init()
/device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/device/
H A Dmali_kbase_device_hw.c38 writel(value, kbdev->reg + offset); in kbase_reg_write()
42 kbase_io_history_add(&kbdev->io_history, kbdev->reg + offset, value, 1); in kbase_reg_write()
45 dev_dbg(kbdev->dev, "w: reg %08x val %08x", offset, value); in kbase_reg_write()
57 val = readl(kbdev->reg + offset); in kbase_reg_read()
61 kbase_io_history_add(&kbdev->io_history, kbdev->reg + offset, val, 0); in kbase_reg_read()
64 dev_dbg(kbdev->dev, "r: reg %08x val %08x", offset, val); in kbase_reg_read()
/device/soc/rockchip/common/sdk_linux/drivers/soc/rockchip/
H A Dgrf.c19 u32 reg; member
235 pr_debug("%s: adjusting %s in %#6x to %#10x\n", __func__, val->desc, val->reg, val->val); in rockchip_grf_init()
236 ret = regmap_write(grf, val->reg, val->val); in rockchip_grf_init()
238 pr_err("%s: write to %#6x failed with %d\n", __func__, val->reg, ret); in rockchip_grf_init()
/third_party/backends/backend/
H A Dhp4200_lm9830.c48 lm9830_read_register (int fd, unsigned char reg, unsigned char *data) in lm9830_read_register() argument
54 retval = sanei_pv8630_write_byte (fd, PV8630_REPPADDRESS, reg); in lm9830_read_register()
61 lm9830_write_register (int fd, unsigned char reg, unsigned char value) in lm9830_write_register() argument
65 retval = sanei_pv8630_write_byte (fd, PV8630_REPPADDRESS, reg); in lm9830_write_register()
/third_party/mesa3d/src/compiler/nir/
H A Dnir_propagate_invariant.c32 _mesa_set_add(invariants, src->reg.reg); in add_src()
49 return _mesa_set_search(invariants, dest->reg.reg); in dest_is_invariant()
H A Dnir_inline_helpers.h49 if (!src->is_ssa && src->reg.indirect) in _nir_visit_src()
50 return cb(src->reg.indirect, state); in _nir_visit_src()
64 if (!dest->is_ssa && dest->reg.indirect) in _nir_visit_dest_indirect()
65 return state->cb(dest->reg.indirect, state->state); in _nir_visit_dest_indirect()
/third_party/mesa3d/src/gallium/drivers/lima/ir/
H A Dlima_nir_duplicate_intrinsic.c48 dupl->src[0].reg = itr->src[0].reg; in lima_nir_duplicate_intrinsic()
81 dupl->src[0].reg = itr->src[0].reg; in lima_nir_duplicate_intrinsic()

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