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/third_party/vulkan-loader/scripts/
H A Dloader_genvk.py366 from reg import *
398 reg = Registry(gen, options) variable
407 reg.loadElementTree(tree)
411 reg.validateGroups()
415 reg.dumpReg(filehandle = open('regdump.txt', 'w', encoding='utf-8'))
419 pdb.run('reg.apiGen()')
422 reg.apiGen()
/third_party/node/deps/v8/src/regexp/
H A Dregexp-compiler.cc300 return reg() == that; in Mentions()
304 bool Trace::mentions_reg(int reg) { in mentions_reg() argument
307 if (action->Mentions(reg)) return true; in mentions_reg()
312 bool Trace::GetStoredPosition(int reg, int* cp_offset) { in GetStoredPosition() argument
316 if (action->Mentions(reg)) { in GetStoredPosition()
372 affected_registers->Set(action->reg(), zone); in FindAffectedRegisters()
373 if (action->reg() > max_register) max_register = action->reg(); in FindAffectedRegisters()
383 for (int reg = max_register; reg > in RestoreAffectedRegisters()
639 SetRegisterForLoop(int reg, int val, RegExpNode* on_success) SetRegisterForLoop() argument
648 IncrementRegister(int reg, RegExpNode* on_success) IncrementRegister() argument
655 StorePosition(int reg, bool is_capture, RegExpNode* on_success) StorePosition() argument
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/third_party/pcre2/pcre2/src/sljit/
H A DsljitNativeARM_64.c617 sljit_s32 reg; in emit_op_imm() local
632 reg = (sljit_s32)((flags & ARG2_IMM) ? arg1 : arg2); in emit_op_imm()
663 return push_inst(compiler, ((op == SLJIT_ADD ? ADDI : SUBI) ^ inv_bits) | RD(dst) | RN(reg)); in emit_op_imm()
667 return push_inst(compiler, (ADDI ^ inv_bits) | RD(dst) | RN(reg) | ((sljit_ins)imm << 10)); in emit_op_imm()
672 return push_inst(compiler, (SUBI ^ inv_bits) | RD(dst) | RN(reg) | ((sljit_ins)nimm << 10)); in emit_op_imm()
676 return push_inst(compiler, (ADDI ^ inv_bits) | RD(dst) | RN(reg) | (((sljit_ins)imm >> 12) << 10) | (1 << 22)); in emit_op_imm()
680 return push_inst(compiler, (SUBI ^ inv_bits) | RD(dst) | RN(reg) | (((sljit_ins)nimm >> 12) << 10) | (1 << 22)); in emit_op_imm()
683 FAIL_IF(push_inst(compiler, (ADDI ^ inv_bits) | RD(dst) | RN(reg) | (((sljit_ins)imm >> 12) << 10) | (1 << 22))); in emit_op_imm()
687 FAIL_IF(push_inst(compiler, (SUBI ^ inv_bits) | RD(dst) | RN(reg) | (((sljit_ins)nimm >> 12) << 10) | (1 << 22))); in emit_op_imm()
696 return push_inst(compiler, (ANDI ^ inv_bits) | RD(dst) | RN(reg) | inst_bit in emit_op_imm()
898 emit_op_mem(struct sljit_compiler *compiler, sljit_s32 flags, sljit_s32 reg, sljit_s32 arg, sljit_sw argw, sljit_s32 tmp_reg) emit_op_mem() argument
1596 sljit_get_register_index(sljit_s32 reg) sljit_get_register_index() argument
1602 sljit_get_float_register_index(sljit_s32 reg) sljit_get_float_register_index() argument
1622 emit_fop_mem(struct sljit_compiler *compiler, sljit_s32 flags, sljit_s32 reg, sljit_s32 arg, sljit_sw argw) emit_fop_mem() argument
2157 sljit_emit_mem(struct sljit_compiler *compiler, sljit_s32 type, sljit_s32 reg, sljit_s32 mem, sljit_sw memw) sljit_emit_mem() argument
2228 sljit_emit_mem_update(struct sljit_compiler *compiler, sljit_s32 type, sljit_s32 reg, sljit_s32 mem, sljit_sw memw) sljit_emit_mem_update() argument
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H A DsljitNativeARM_32.c409 static SLJIT_INLINE sljit_s32 emit_imm(struct sljit_compiler *compiler, sljit_s32 reg, sljit_sw imm) in emit_imm() argument
411 FAIL_IF(push_inst(compiler, MOVW | RD(reg) | ((imm << 4) & 0xf0000) | ((sljit_u32)imm & 0xfff))); in emit_imm()
412 return push_inst(compiler, MOVT | RD(reg) | ((imm >> 12) & 0xf0000) | (((sljit_u32)imm >> 16) & 0xfff)); in emit_imm()
570 static sljit_s32 load_immediate(struct sljit_compiler *compiler, sljit_s32 reg, sljit_uw imm);
571 static sljit_s32 emit_op_mem(struct sljit_compiler *compiler, sljit_s32 flags, sljit_s32 reg, sljit_s32 arg, sljit_sw argw, sljit_s32 tmp_reg);
1048 /* dst: reg
1049 src1: reg
1050 src2: reg or imm (if allowed)
1091 single register: str reg, [sp, #-4]! */ in sljit_emit_enter()
1376 single register: ldr reg, [s in emit_stack_frame_release()
1659 generate_int(struct sljit_compiler *compiler, sljit_s32 reg, sljit_uw imm, sljit_s32 positive) generate_int() argument
1770 load_immediate(struct sljit_compiler *compiler, sljit_s32 reg, sljit_uw imm) load_immediate() argument
1803 emit_op_mem(struct sljit_compiler *compiler, sljit_s32 flags, sljit_s32 reg, sljit_s32 arg, sljit_sw argw, sljit_s32 tmp_reg) emit_op_mem() argument
2319 sljit_get_register_index(sljit_s32 reg) sljit_get_register_index() argument
2325 sljit_get_float_register_index(sljit_s32 reg) sljit_get_float_register_index() argument
2349 emit_fop_mem(struct sljit_compiler *compiler, sljit_s32 flags, sljit_s32 reg, sljit_s32 arg, sljit_sw argw) emit_fop_mem() argument
3239 sljit_emit_mem_unaligned(struct sljit_compiler *compiler, sljit_s32 type, sljit_s32 reg, sljit_s32 mem, sljit_sw memw) sljit_emit_mem_unaligned() argument
3389 sljit_emit_mem(struct sljit_compiler *compiler, sljit_s32 type, sljit_s32 reg, sljit_s32 mem, sljit_sw memw) sljit_emit_mem() argument
3439 sljit_emit_mem_update(struct sljit_compiler *compiler, sljit_s32 type, sljit_s32 reg, sljit_s32 mem, sljit_sw memw) sljit_emit_mem_update() argument
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H A DsljitLir.c126 #define OFFS_REG(reg) (((reg) >> 8) & REG_MASK)
128 #define TO_OFFS_REG(reg) ((reg) << 8)
129 /* When reg cannot be unused. */
130 #define FAST_IS_REG(reg) ((reg) <= REG_MASK)
138 #define REG_PAIR_FIRST(reg) ((reg) & 0xff)
139 #define REG_PAIR_SECOND(reg) ((re
1519 check_sljit_get_register_index(sljit_s32 reg) check_sljit_get_register_index() argument
1528 check_sljit_get_float_register_index(sljit_s32 reg) check_sljit_get_float_register_index() argument
2025 check_sljit_emit_mem(struct sljit_compiler *compiler, sljit_s32 type, sljit_s32 reg, sljit_s32 mem, sljit_sw memw) check_sljit_emit_mem() argument
2110 check_sljit_emit_mem_update(struct sljit_compiler *compiler, sljit_s32 type, sljit_s32 reg, sljit_s32 mem, sljit_sw memw) check_sljit_emit_mem_update() argument
2347 sljit_emit_mem_unaligned(struct sljit_compiler *compiler, sljit_s32 type, sljit_s32 reg, sljit_s32 mem, sljit_sw memw) sljit_emit_mem_unaligned() argument
2582 sljit_emit_mem_update(struct sljit_compiler *compiler, sljit_s32 type, sljit_s32 reg, sljit_s32 mem, sljit_sw memw) sljit_emit_mem_update() argument
2872 sljit_get_register_index(sljit_s32 reg) sljit_get_register_index() argument
3048 sljit_emit_mem(struct sljit_compiler *compiler, sljit_s32 type, sljit_s32 reg, sljit_s32 mem, sljit_sw memw) sljit_emit_mem() argument
3059 sljit_emit_mem_update(struct sljit_compiler *compiler, sljit_s32 type, sljit_s32 reg, sljit_s32 mem, sljit_sw memw) sljit_emit_mem_update() argument
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H A DsljitNativePPC_32.c29 static sljit_s32 load_immediate(struct sljit_compiler *compiler, sljit_s32 reg, sljit_sw imm) in load_immediate() argument
32 return push_inst(compiler, ADDI | D(reg) | A(0) | IMM(imm)); in load_immediate()
35 return push_inst(compiler, ORI | S(TMP_ZERO) | A(reg) | IMM(imm)); in load_immediate()
37 FAIL_IF(push_inst(compiler, ADDIS | D(reg) | A(0) | IMM(imm >> 16))); in load_immediate()
38 return (imm & 0xffff) ? push_inst(compiler, ORI | S(reg) | A(reg) | IMM(imm)) : SLJIT_SUCCESS; in load_immediate()
322 static SLJIT_INLINE sljit_s32 emit_const(struct sljit_compiler *compiler, sljit_s32 reg, sljit_sw init_value) in emit_const() argument
324 FAIL_IF(push_inst(compiler, ADDIS | D(reg) | A(0) | IMM(init_value >> 16))); in emit_const()
325 return push_inst(compiler, ORI | S(reg) | A(reg) | IM in emit_const()
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/third_party/mesa3d/src/amd/compiler/
H A Daco_print_ir.cpp104 print_physReg(PhysReg reg, unsigned bytes, FILE* output, unsigned flags) in print_physReg() argument
106 if (reg == 124) { in print_physReg()
108 } else if (reg == 106) { in print_physReg()
110 } else if (reg == 253) { in print_physReg()
112 } else if (reg == 126) { in print_physReg()
115 bool is_vgpr = reg / 256; in print_physReg()
116 unsigned r = reg % 256; in print_physReg()
127 if (reg.byte() || bytes % 4) in print_physReg()
128 fprintf(output, "[%d:%d]", reg.byte() * 8, (reg in print_physReg()
133 print_constant(uint8_t reg, FILE* output) print_constant() argument
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H A Daco_validate.cpp748 PhysReg reg; member
952 PhysReg reg = assignments[tmp.id()].reg; in validate_instr_defs() local
954 if (regs[reg.reg_b + j]) in validate_instr_defs()
956 ra_fail(program, loc, assignments[regs[reg.reg_b + j]].defloc, in validate_instr_defs()
958 tmp.id(), regs[reg.reg_b + j]); in validate_instr_defs()
959 regs[reg.reg_b + j] = tmp.id(); in validate_instr_defs()
965 for (unsigned j = reg.byte() & ~(written - 1); j < written; j++) { in validate_instr_defs()
966 unsigned written_reg = reg.reg() * in validate_instr_defs()
1094 PhysReg reg = assignments[id].reg; validate_ra() local
1112 PhysReg reg = assignments[tmp.id()].reg; validate_ra() local
1143 PhysReg reg = assignments[id].reg; validate_ra() local
1154 PhysReg reg = assignments[tmp.id()].reg; validate_ra() local
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/base/hiviewdfx/faultloggerd/interfaces/innerkits/unwinder/include/
H A Ddfx_regs_qut.h44 static inline bool IsQutReg(uint16_t reg, size_t& qutIdx) in IsQutReg() argument
48 if (qutRegs[i] == reg) { in IsQutReg()
/third_party/mesa3d/src/gallium/drivers/radeonsi/
H A Dsi_pm4.h63 void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val);
64 void si_pm4_set_reg_idx3(struct si_pm4_state *state, unsigned reg, uint32_t val);
/third_party/rust/crates/minimal-lexical/src/
H A Dfpu.rs49 in(reg) &cw, in set_cw()
73 in(reg) &mut cw, in set_precision()
/third_party/cmsis/CMSIS/Core/Include/
H A Dcore_ca.h2720 \param [in] reg Section attributes
2724 __STATIC_INLINE int MMU_GetSectionDescriptor(uint32_t *descriptor, mmu_region_attributes_Type reg) in MMU_GetSectionDescriptor() argument
2728 MMU_MemorySection(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t); in MMU_GetSectionDescriptor()
2729 MMU_XNSection(descriptor,reg.xn_t); in MMU_GetSectionDescriptor()
2730 MMU_DomainSection(descriptor, reg.domain); in MMU_GetSectionDescriptor()
2731 MMU_PSection(descriptor, reg.e_t); in MMU_GetSectionDescriptor()
2732 MMU_APSection(descriptor, reg.user_t, reg in MMU_GetSectionDescriptor()
2751 MMU_GetPageDescriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg) MMU_GetPageDescriptor() argument
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/third_party/mesa3d/src/gallium/drivers/svga/
H A Dsvga_tgsi_vgpu10.c304 unsigned out_index; /**< the real position output reg */
305 unsigned tmp_index; /**< the fake/temp position output reg */
306 unsigned so_index; /**< the non-adjusted position output reg */
337 unsigned color_tmp_index; /**< fake/temp color output reg */
341 unsigned face_input_index; /**< real fragment shader face reg (bool) */
342 unsigned face_tmp_index; /**< temp face reg converted to -1 / +1 */
347 unsigned fragcoord_input_index; /**< real fragment position input reg */
348 unsigned fragcoord_tmp_index; /**< 1/w modified position temp reg */
353 unsigned sample_pos_tmp_index; /**< which temp reg has the sample pos */
464 /* For all shaders: const reg inde
1269 emit_dst_register(struct svga_shader_emitter_v10 *emit, const struct tgsi_full_dst_register *reg) emit_dst_register() argument
1551 emit_src_register(struct svga_shader_emitter_v10 *emit, const struct tgsi_full_src_register *reg) emit_src_register() argument
2337 struct tgsi_full_src_register reg; make_src_reg() local
2357 struct tgsi_full_src_register reg; make_src_scalar_reg() local
2409 struct tgsi_full_dst_register reg; make_dst_reg() local
2443 negate_src(const struct tgsi_full_src_register *reg) negate_src() argument
2454 absolute_src(const struct tgsi_full_src_register *reg) absolute_src() argument
2464 get_swizzle(const struct tgsi_full_src_register *reg, enum tgsi_swizzle term) get_swizzle() argument
2486 swizzle_src(const struct tgsi_full_src_register *reg, enum tgsi_swizzle swizzleX, enum tgsi_swizzle swizzleY, enum tgsi_swizzle swizzleZ, enum tgsi_swizzle swizzleW) swizzle_src() argument
2505 scalar_src(const struct tgsi_full_src_register *reg, enum tgsi_swizzle swizzle) scalar_src() argument
2522 writemask_dst(const struct tgsi_full_dst_register *reg, unsigned mask) writemask_dst() argument
2534 same_swizzle_terms(const struct tgsi_full_src_register *reg) same_swizzle_terms() argument
2622 struct tgsi_full_src_register reg; make_immediate_reg_4() local
2670 struct tgsi_full_src_register reg; make_immediate_reg() local
2751 struct tgsi_full_src_register reg; make_immediate_reg_double() local
5591 unsigned total_temps, reg, i; emit_temporaries_declaration() local
9280 check_double_src(struct svga_shader_emitter_v10 *emit, const struct tgsi_full_src_register *reg) check_double_src() argument
10051 const struct tgsi_full_dst_register *reg = &inst->Dst[regIndex]; emit_memory_register() local
10060 const struct tgsi_full_src_register *reg = &inst->Src[regIndex]; emit_memory_register() local
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/third_party/node/deps/v8/src/compiler/
H A Dlinkage.cc24 inline LinkageLocation regloc(Register reg, MachineType type) { in regloc() argument
25 return LinkageLocation::ForRegister(reg.code(), type); in regloc()
28 inline LinkageLocation regloc(DoubleRegister reg, MachineType type) { in regloc() argument
29 return LinkageLocation::ForRegister(reg.code(), type); in regloc()
485 Register reg = descriptor.GetRegisterParameter(i); in GetStubCallDescriptor() local
487 locations.AddParam(regloc(reg, type)); in GetStubCallDescriptor()
563 Register reg = descriptor.GetRegisterParameter(i); in GetBytecodeDispatchCallDescriptor() local
565 locations.AddParam(regloc(reg, type)); in GetBytecodeDispatchCallDescriptor()
617 inline bool IsTaggedReg(const LinkageLocation& loc, Register reg) { in IsTaggedReg() argument
618 return loc.IsRegister() && loc.AsRegister() == reg in IsTaggedReg()
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/third_party/node/deps/v8/src/interpreter/
H A Dbytecode-array-builder.h127 BytecodeArrayBuilder& LoadAccumulatorWithRegister(Register reg);
128 BytecodeArrayBuilder& StoreAccumulatorInRegister(Register reg);
366 BytecodeArrayBuilder& BinaryOperation(Token::Value binop, Register reg,
399 BytecodeArrayBuilder& CompareOperation(Token::Value op, Register reg,
401 BytecodeArrayBuilder& CompareReference(Register reg);
552 uint32_t GetInputRegisterOperand(Register reg);
553 uint32_t GetOutputRegisterOperand(Register reg);
559 void OutputLdarRaw(Register reg);
560 void OutputStarRaw(Register reg);
601 bool RegisterIsValid(Register reg) cons
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/third_party/mesa3d/src/gallium/drivers/r600/sfn/
H A Dsfn_virtualvalues.h263 void set_value(PRegister reg) { m_value = reg;} in set_value() argument
279 void set_value(int i, PRegister reg) { in set_value() argument
280 assert(reg->sel() == m_sel); in set_value()
281 m_swz[i] = reg->chan(); in set_value()
282 m_values[i]->set_value(reg); in set_value()
399 LocalArrayValue(PRegister reg, LocalArray& array);
400 LocalArrayValue(PRegister reg, PVirtualValue index, LocalArray &array);
/third_party/mesa3d/src/gallium/drivers/etnaviv/
H A Detnaviv_disasm.c344 printf("t%u", dst->reg); in print_dst()
393 src->reg += 128; in print_src()
396 printf("%u", src->reg); in print_src()
424 printf("a%u", operands->dst->reg); in print_opc_mov()
543 .reg = instr->dst_reg, in print_instr()
558 .reg = instr->src0_reg, in print_instr()
568 .reg = instr->src1_reg, in print_instr()
578 .reg = instr->src2_reg, in print_instr()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
H A DAArch64PBQPRegAlloc.cpp36 bool isFPReg(unsigned reg) { in isFPReg() argument
37 return AArch64::FPR32RegClass.contains(reg) || in isFPReg()
38 AArch64::FPR64RegClass.contains(reg) || in isFPReg()
39 AArch64::FPR128RegClass.contains(reg); in isFPReg()
43 bool isOdd(unsigned reg) { in isOdd() argument
44 switch (reg) { in isOdd()
166 LLVM_DEBUG(dbgs() << "Rd is a physical reg:" in addIntraChainConstraint()
168 LLVM_DEBUG(dbgs() << "Ra is a physical reg:" in addIntraChainConstraint()
216 // Get the maximum cost (excluding unallocatable reg) for same parity in addIntraChainConstraint()
293 // Get the maximum cost (excluding unallocatable reg) fo in addInterChainConstraint()
319 regJustKilledBefore(const LiveIntervals &LIs, unsigned reg, const MachineInstr &MI) regJustKilledBefore() argument
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/third_party/wpa_supplicant/wpa_supplicant-2.9/src/p2p/
H A Dp2p_utils.c259 const struct p2p_reg_class *reg = &channels->reg_class[i]; in p2p_channels_includes() local
260 if (reg->reg_class != reg_class) in p2p_channels_includes()
262 for (j = 0; j < reg->channels; j++) { in p2p_channels_includes()
263 if (reg->channel[j] == channel) in p2p_channels_includes()
276 const struct p2p_reg_class *reg = &channels->reg_class[i]; in p2p_channels_includes_freq() local
277 for (j = 0; j < reg->channels; j++) { in p2p_channels_includes_freq()
278 if (p2p_channel_to_freq(reg->reg_class, in p2p_channels_includes_freq()
279 reg->channel[j]) == (int) freq) in p2p_channels_includes_freq()
/third_party/wpa_supplicant/wpa_supplicant-2.9_standard/src/p2p/
H A Dp2p_utils.c262 const struct p2p_reg_class *reg = &channels->reg_class[i]; in p2p_channels_includes() local
263 if (reg->reg_class != reg_class) in p2p_channels_includes()
265 for (j = 0; j < reg->channels; j++) { in p2p_channels_includes()
266 if (reg->channel[j] == channel) in p2p_channels_includes()
279 const struct p2p_reg_class *reg = &channels->reg_class[i]; in p2p_channels_includes_freq() local
280 for (j = 0; j < reg->channels; j++) { in p2p_channels_includes_freq()
281 if (p2p_channel_to_freq(reg->reg_class, in p2p_channels_includes_freq()
282 reg->channel[j]) == (int) freq) in p2p_channels_includes_freq()
/third_party/mesa3d/src/gallium/drivers/lima/ir/pp/
H A Dcodegen.c114 f->reg.dest = index >> 2; in ppir_codegen_encode_varying()
115 f->reg.mask = dest->write_mask << (index & 0x3); in ppir_codegen_encode_varying()
119 f->reg.source_type = 2; in ppir_codegen_encode_varying()
120 f->reg.perspective = 1; in ppir_codegen_encode_varying()
122 f->reg.source_type = 1; in ppir_codegen_encode_varying()
125 f->reg.perspective = 0; in ppir_codegen_encode_varying()
128 f->reg.perspective = 2; in ppir_codegen_encode_varying()
131 f->reg.perspective = 3; in ppir_codegen_encode_varying()
137 f->reg.source = index >> 2; in ppir_codegen_encode_varying()
138 f->reg in ppir_codegen_encode_varying()
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/third_party/mesa3d/src/amd/vulkan/
H A Dradv_perfcounter.c450 uint32_t reg = pool->counters[i].regs[j]; in radv_pc_init_query_pool() local
451 if (!reg || G_REG_CONSTANT(reg)) in radv_pc_init_query_pool()
456 if (pool->pc_regs[k] == reg) in radv_pc_init_query_pool()
518 unsigned reg = regs->counter0_lo; in radv_pc_emit_block_instance_read() local
524 reg = regs->counters[idx]; in radv_pc_emit_block_instance_read()
529 radeon_emit(cs, reg >> 2); in radv_pc_emit_block_instance_read()
536 reg += reg_delta; in radv_pc_emit_block_instance_read()
762 radv_pc_sum_reg(uint32_t reg, const uint64_t *data) in radv_pc_sum_reg() argument
764 unsigned instances = G_REG_INSTANCES(reg); in radv_pc_sum_reg()
779 radv_pc_max_reg(uint32_t reg, const uint64_t *data) radv_pc_max_reg() argument
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/third_party/node/deps/v8/src/diagnostics/x64/
H A Ddisasm-x64.cc286 const char* NameOfYMMRegister(int reg);
427 const char* NameOfCPURegister(int reg) const { in NameOfCPURegister()
428 return converter_.NameOfCPURegister(reg); in NameOfCPURegister()
431 const char* NameOfByteCPURegister(int reg) const { in NameOfByteCPURegister()
432 return converter_.NameOfByteCPURegister(reg); in NameOfByteCPURegister()
435 const char* NameOfXMMRegister(int reg) const { in NameOfXMMRegister()
436 return converter_.NameOfXMMRegister(reg); in NameOfXMMRegister()
439 const char* NameOfAVXRegister(int reg) const { in NameOfAVXRegister()
441 return NameOfYMMRegister(reg); in NameOfAVXRegister()
443 return converter_.NameOfXMMRegister(reg); in NameOfAVXRegister()
2097 int reg = (opcode - 0xC8) | (rex_r() ? 8 : 0); TwoByteOpcodeInstruction() local
2593 int reg = (*data & 0x7) | (rex_b() ? 8 : 0); InstructionDecode() local
2624 int reg = (opcode & 0x7) | (rex_b() ? 8 : 0); InstructionDecode() local
2823 NameOfYMMRegister(int reg) NameOfYMMRegister() argument
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/third_party/mesa3d/src/nouveau/codegen/
H A Dnv50_ir_emit_gm107.cpp243 emitField(16, 3, insn->getSrc(insn->predSrc)->rep()->reg.data.id); in emitPred()
263 val->reg.data.id : 255); in emitGPR()
269 int id = val ? val->reg.data.id : -1; in emitSYS()
278 case SV_TID : id = 0x21 + val->reg.data.sv.index; break; in emitSYS()
279 case SV_CTAID : id = 0x25 + val->reg.data.sv.index; break; in emitSYS()
285 case SV_CLOCK : id = 0x50 + val->reg.data.sv.index; break; in emitSYS()
298 emitField(pos, 3, val ? val->reg.data.id : 7); in emitPRED()
306 assert(!(v->reg.data.offset & ((1 << shr) - 1))); in emitADDR()
309 emitField(off, len, v->reg.data.offset >> shr); in emitADDR()
319 assert(!(s->reg in emitCBUF()
2572 int reg = entry->reg; gm107_interpApply() local
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/third_party/node/deps/v8/src/codegen/x64/
H A Dassembler-x64.h244 // Does not check the "reg" part of the Operand.
245 bool AddressUsesRegister(Register reg) const;
379 // Distance between the address of the imm64 in the 'movq reg, imm64'
650 void testb(Register reg, Operand op) { testb(op, reg); } in testb() argument
652 void testw(Register reg, Operand op) { testw(op, reg); } in testw() argument
664 void xchgb(Register reg, Operand op);
665 void xchgw(Register reg, Operand op);
672 void negb(Register reg);
978 sse2_instr(XMMRegister reg, byte imm8, byte prefix, byte escape, byte opcode, int extension) sse2_instr() argument
2246 emit_operand(Register reg, Operand adr) emit_operand() argument
2256 emit_modrm(Register reg, Register rm_reg) emit_modrm() argument
2474 emit_test(Register reg, Operand op, int size) emit_test() argument
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