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/third_party/openGLES/xml/
H A Dreadme.tex89 \code{genheaders.py}, and \code{reg.py} will be necessary if you want to
115 \subsection{Registry Processing Script - \code{reg.py}}
117 Actual XML registry processing is done in \code{reg.py}, which contains
/third_party/skia/third_party/externals/tint/src/writer/hlsl/
H A Dgenerator_impl.cc107 : reg(r), binding_point(bp) {} in RegisterAndSpace()
109 const char reg; member
114 s << " : register(" << rs.reg << rs.binding_point.binding->value << ", space" in operator <<()
/third_party/skia/third_party/externals/angle2/src/libANGLE/
H A DProgram.cpp3788 for (int reg = 0; reg < regs; reg++) in linkAttributes()
3790 const int regLocation = attribute.location + reg; in linkAttributes()
/third_party/node/deps/v8/src/codegen/mips64/
H A Dmacro-assembler-mips64.cc1297 // Load consequent 32-bit word pair in 64-bit reg. and put first word in low in CallRecordWriteStub()
4638 void TurboAssembler::Drop(int count, Condition cond, Register reg, in CallRecordWriteStub() argument
4647 Branch(&skip, NegateCondition(cond), reg, op); in CallRecordWriteStub()
5421 FPURegister reg = FPURegister::from_code(2 * i); in CallRecordWriteStub() local
5422 Sdc1(reg, MemOperand(sp, i * kDoubleSize)); in CallRecordWriteStub()
5457 FPURegister reg = FPURegister::from_code(2 * i); in CallRecordWriteStub() local
5458 Ldc1(reg, MemOperand(t8, i * kDoubleSize)); in CallRecordWriteStub()
/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/
H A DIceTargetLoweringX8664.cpp822 // Print in the form "Offset(%reg)", omitting Offset when it is 0. in emitVariable()
3476 // signature matches the native POPCNT instruction and fills a 64-bit reg in lowerIntrinsic()
4017 // mov <reg>, eax in expandAtomicRMWAsCmpxchg()
4018 // op <reg>, [desired_adj] in expandAtomicRMWAsCmpxchg()
4019 // lock cmpxchg [ptr], <reg> in expandAtomicRMWAsCmpxchg()
4927 /// store operand. The basic idea is that given a memory operand [reg], we
4930 /// cmp reg, <lb>
4932 /// cmp reg, <ub>
4940 /// suffice. However, we consider [reg+offset] to be OK because the offset is
4947 /// cmp reg,
7088 Variable *reg = getPhysicalRegister(RegNum, IceType_v4f32); _push_reg() local
7102 Variable *reg = getPhysicalRegister(RegNum, IceType_v4f32); _pop_reg() local
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/third_party/icu/icu4c/source/common/
H A Ducurr.cpp391 static UCurrRegistryKey reg(const UChar* _iso, const char* _id, UErrorCode* status) in reg() function
466 return CReg::reg(isoCode, id, status); in ucurr_register()
/third_party/mesa3d/src/imagination/vulkan/pds/
H A Dpvr_pds.c1349 vertex_element->reg in pvr_pds_vertex_shader()
1462 vertex_element->reg in pvr_pds_vertex_shader()
/third_party/node/deps/icu-small/source/common/
H A Ducurr.cpp394 static UCurrRegistryKey reg(const char16_t* _iso, const char* _id, UErrorCode* status) in reg() function
469 return CReg::reg(isoCode, id, status); in ucurr_register()
/third_party/skia/third_party/externals/icu/source/common/
H A Ducurr.cpp391 static UCurrRegistryKey reg(const UChar* _iso, const char* _id, UErrorCode* status) in reg() function
466 return CReg::reg(isoCode, id, status); in ucurr_register()
/third_party/vixl/src/aarch64/
H A Dmacro-assembler-sve-aarch64.cc920 explicit IndexOperand(const Register& reg) : Operand(reg) {} in Index() argument
H A Dmacro-assembler-aarch64.h1171 void B(Label* label, BranchType type, Register reg = NoReg, int bit = -1);
8691 bool IsAvailable(const CPURegister& reg) const;
8731 Register AcquireSameSizeAs(const Register& reg) { in AcquireSameSizeAs() argument
8732 return AcquireRegisterOfSize(reg.GetSizeInBits()); in AcquireSameSizeAs()
8735 VRegister AcquireSameSizeAs(const VRegister& reg) { in AcquireSameSizeAs() argument
8736 return AcquireVRegisterOfSize(reg.GetSizeInBits()); in AcquireSameSizeAs()
8753 void Release(const CPURegister& reg);
/third_party/mesa3d/src/broadcom/compiler/
H A Dv3d_compiler.h891 * limiting ourselves to the part of the physical reg space.
893 * On V3D 3.x, 2x or 4x divide the physical reg space by 2x or 4x. On
895 * physical reg space in half.
1132 struct qreg vir_follow_movs(struct v3d_compile *c, struct qreg reg);
/third_party/vixl/src/aarch32/
H A Dmacro-assembler-aarch32.h544 bool AliasesAvailableScratchRegister([[maybe_unused]] Register reg) { in MacroAssembler() argument
546 return GetScratchRegisterList()->Includes(reg); in MacroAssembler()
551 bool AliasesAvailableScratchRegister([[maybe_unused]] RegisterOrAPSR_nzcv reg) { in MacroAssembler() argument
553 if (reg.IsAPSR_nzcv()) return false; in MacroAssembler()
554 return GetScratchRegisterList()->Includes(reg.AsRegister()); in MacroAssembler()
559 bool AliasesAvailableScratchRegister([[maybe_unused]] VRegister reg) { in MacroAssembler() argument
561 return GetScratchVRegisterList()->IncludesAliasOf(reg); in MacroAssembler()
991 void PushRegister(CPURegister reg); in MacroAssembler()
992 void PreparePrintfArgument(CPURegister reg, in MacroAssembler()
13410 bool IsAvailable(const Register& reg) cons in MacroAssembler()
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/third_party/mesa3d/src/amd/vulkan/
H A Dradv_cmd_buffer.c2442 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset; in radv_load_ds_clear_metadata() local
2448 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2); in radv_load_ds_clear_metadata()
2456 radeon_emit(cs, reg >> 2); in radv_load_ds_clear_metadata()
2634 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c; in radv_load_color_clear_metadata() local
2640 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2); in radv_load_color_clear_metadata()
2648 radeon_emit(cs, reg >> 2); in radv_load_color_clear_metadata()
8439 unsigned reg = R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4; in radv_emit_dispatch_packets() local
8446 radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2); in radv_emit_dispatch_packets()
8449 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs, reg, info->va, true); in radv_emit_dispatch_packets()
/third_party/mesa3d/src/amd/compiler/
H A Daco_instruction_selection.cpp8971 /* src2 is ignored for writelane. RA assigns the same reg for dst */
11374 PhysReg color_start(exports_start.reg() + color_index * 4);
11588 unsigned reg = ctx->args->ac.args[i].offset;
11591 if (file == AC_ARG_SGPR && reg % MIN2(4, util_next_power_of_two(size))) {
11595 startpgm->definitions[arg++] = Definition(elems[j].id(), PhysReg{reg + j}, s1);
11602 startpgm->definitions[arg].setFixed(PhysReg{file == AC_ARG_SGPR ? reg : reg + 256});
12205 unsigned reg = args->ac.args[arg.arg_index].offset;
12207 return Operand(PhysReg(file == AC_ARG_SGPR ? reg : reg
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/third_party/ffmpeg/libavcodec/x86/
H A Dvp9itxfm.asm1158 %macro %%SUMSUB_BA_STORE 5 ; reg, from_mem, to_mem, scratch, scratch_stride
1514 %macro VP9_STORE_YMM_DC_4X 6 ; reg, tmp1, tmp2, tmp3, tmp4, zero
3099 %macro VP9_STORE_YMM_DC_2X2 6 ; reg, tmp1, tmp2, tmp3, tmp4, zero
H A Dh264_deblock_10bit.asm63 ; in: %2=tc reg
/third_party/node/deps/v8/src/codegen/mips/
H A Dassembler-mips.cc131 int ToNumber(Register reg) { in ToNumber() argument
132 DCHECK(reg.is_valid()); in ToNumber()
167 return kNumbers[reg.code()]; in ToNumber()
533 return label_constant == 0; // Emitted label const in reg-exp engine. in IsEmittedConstant()
2176 // 'lui' has zero reg. for rs field. in aui()
/foundation/arkui/napi/native_engine/impl/ark/
H A Dark_native_engine.cpp1358 const std::regex reg("@(ohos|system)\\.(\\S+)"); in GetOhmurl()
1361 bool ret = std::regex_match(path, reg); in GetOhmurl()
/third_party/backends/backend/
H A Dplustek-pp_dac.c1798 static void dacP98003GainOffsetToDAC( pScanData ps, Byte ch, Byte reg, Byte d ) in dacP98003GainOffsetToDAC() argument
1807 IODataToRegister( ps, ps->RegADCAddress, reg ); in dacP98003GainOffsetToDAC()
/third_party/skia/third_party/externals/abseil-cpp/absl/container/internal/
H A Dlayout_test.cc1392 std::initializer_list<Region> reg) { in ExpectPoisoned()
1394 for (const Region& r : reg) { in ExpectPoisoned()
1391 ExpectPoisoned(const unsigned char (&buf)[N], std::initializer_list<Region> reg) ExpectPoisoned() argument
/third_party/node/deps/v8/src/codegen/arm/
H A Dassembler-arm.cc1685 void Assembler::movw(Register reg, uint32_t immediate, Condition cond) { in movw() argument
1687 emit(cond | 0x30 * B20 | reg.code() * B12 | EncodeMovwImmediate(immediate)); in movw()
1690 void Assembler::movt(Register reg, uint32_t immediate, Condition cond) { in movt() argument
1692 emit(cond | 0x34 * B20 | reg.code() * B12 | EncodeMovwImmediate(immediate)); in movt()
/third_party/vixl/test/aarch64/
H A Dtest-trace-aarch64.cc3063 LogicVRegister reg(simulator.ReadVRegister(r));
3074 reg.SetUint(kFormatVnD, lane, base | mantissas);
3078 LogicPRegister reg(simulator.ReadPRegister(r));
3081 reg.SetActive(kFormatVnB, bit, ((bit + 1) % (r + 2)) != 0);
3087 reg.SetActiveMask(chunk, static_cast<uint16_t>(0));
/third_party/ffmpeg/libavcodec/arm/
H A Dsimple_idct_arm.S47 @@ save stack for reg needed (take all of them),
/third_party/backends/backend/genesys/
H A Dlow.cpp64 case AsicType::GL845: // since only a few reg bits differs we handle both together in create_cmd_set()
1453 dev->initial_regs = dev->reg; in sanei_genesys_asic_init()

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