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/third_party/mesa3d/src/gallium/drivers/r300/
H A Dr300_emit.c521 unsigned reg, i, distx, disty, dist; in r300_get_mspos() local
549 reg = R300_NIBBLES(p[0], p[1], p[2], p[3], p[4], p[5], disty, distx); in r300_get_mspos()
561 reg = R300_NIBBLES(p[6], p[7], p[8], p[9], p[10], p[11], dist, 0); in r300_get_mspos()
563 return reg; in r300_get_mspos()
/third_party/node/deps/v8/src/codegen/riscv64/
H A Dmacro-assembler-riscv64.cc1295 // Load consequent 32-bit word pair in 64-bit reg. and put first word in low
1664 #define TEST_AND_PUSH_REG(reg) \ in MultiPush()
1665 if (regs.has(reg)) { \ in MultiPush()
1667 Sd(reg, MemOperand(sp, stack_offset)); \ in MultiPush()
1668 regs.clear(reg); \ in MultiPush()
1707 #define TEST_AND_POP_REG(reg) \ in MultiPop()
1708 if (regs.has(reg)) { \ in MultiPop()
1709 Ld(reg, MemOperand(sp, stack_offset)); \ in MultiPop()
1711 regs.clear(reg); \ in MultiPop()
3502 void TurboAssembler::Drop(int count, Condition cond, Register reg, in Drop() argument
4411 FPURegister reg = FPURegister::from_code(i); EnterExitFrame() local
4452 FPURegister reg = FPURegister::from_code(i); LeaveExitFrame() local
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H A Dregister-riscv64.h26 // t6 : call reg.
172 int ToNumber(Register reg);
205 // number of Double regs (64-bit regs, or FPU-reg-pairs).
209 // Find low reg of a Double-reg pair, which is the reg itself. in low()
214 // Find high reg of a Doubel-reg pair, which is reg + 1. in high()
H A Dconstants-riscv64.h101 static const char* Name(int reg);
107 int reg; member
123 static const char* Name(int reg);
141 static const char* Name(int reg);
/third_party/wpa_supplicant/wpa_supplicant-2.9/wpa_supplicant/
H A Dp2p_supplicant.c3344 static void wpas_p2p_add_chan(struct p2p_reg_class *reg, u8 chan) in wpas_p2p_add_chan() argument
3346 reg->channel[reg->channels] = chan; in wpas_p2p_add_chan()
3347 reg->channels++; in wpas_p2p_add_chan()
3621 struct p2p_reg_class *reg = NULL, *cli_reg = NULL; in wpas_p2p_setup_channels() local
3635 if (reg == NULL) { in wpas_p2p_setup_channels()
3638 reg = &chan->reg_class[cla]; in wpas_p2p_setup_channels()
3640 reg->reg_class = o->op_class; in wpas_p2p_setup_channels()
3642 reg->channel[reg in wpas_p2p_setup_channels()
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/third_party/elfutils/src/
H A Dreadelf.c6310 snprintf (name, REGNAMESZ, "reg%u", loc->regno); in register_info()
12200 for (int reg = regloc->regno; reg < regloc->regno + regloc->count; ++reg) in handle_core_register()
12205 register_info (ebl, reg, regloc, name, &bits, &type); in handle_core_register()
12374 for (int reg = reglocs[i].regno; in handle_core_registers()
12375 reg < reglocs[i].regno + reglocs[i].count; in handle_core_registers()
12376 ++reg) in handle_core_registers()
12378 assert (reg < maxnreg); in handle_core_registers()
12379 if (reg > maxre in handle_core_registers()
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/third_party/node/deps/v8/src/compiler/backend/mips64/
H A Dcode-generator-mips64.cc582 Register reg = i.InputRegister(0); in AssembleArchInstruction() local
585 reg == kJavaScriptCallCodeStartRegister); in AssembleArchInstruction()
586 __ daddiu(reg, reg, Code::kHeaderSize - kHeapObjectTag); in AssembleArchInstruction()
587 __ Call(reg); in AssembleArchInstruction()
633 Register reg = i.InputRegister(0); in AssembleArchInstruction() local
636 reg == kJavaScriptCallCodeStartRegister); in AssembleArchInstruction()
637 __ daddiu(reg, reg, Code::kHeaderSize - kHeapObjectTag); in AssembleArchInstruction()
638 __ Jump(reg); in AssembleArchInstruction()
646 Register reg = i.InputRegister(0); AssembleArchInstruction() local
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/third_party/vixl/src/aarch64/
H A Ddisasm-aarch64.cc6115 const CPURegister &reg) { in Disassembler()
6117 VIXL_ASSERT(reg.IsValid()); in Disassembler()
6120 if (reg.IsRegister()) { in Disassembler()
6121 reg_char = reg.Is64Bits() ? 'x' : 'w'; in Disassembler()
6123 VIXL_ASSERT(reg.IsVRegister()); in Disassembler()
6124 switch (reg.GetSizeInBits()) { in Disassembler()
6138 VIXL_ASSERT(reg.Is128Bits()); in Disassembler()
6143 if (reg.IsVRegister() || !(reg.Aliases(sp) || reg in Disassembler()
6114 AppendRegisterNameToOutput(const Instruction *instr, const CPURegister &reg) Disassembler() argument
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H A Ddisasm-aarch64.h74 const CPURegister& reg);
/third_party/ffmpeg/libavcodec/x86/
H A Dflacdsp.asm181 ;%3 = last xmm reg used
/third_party/libunwind/libunwind/include/
H A Ddwarf.h260 dwarf_reg_only_state_t reg; member
306 dwarf_reg_state_t rs_initial; /* reg-state after CIE instructions */
307 dwarf_reg_state_t rs_current; /* current reg-state */
/third_party/node/deps/v8/src/codegen/mips64/
H A Dregister-mips64.h113 int ToNumber(Register reg);
151 // number of Double regs (64-bit regs, or FPU-reg-pairs).
155 // Find low reg of a Double-reg pair, which is the reg itself. in low()
156 DCHECK_EQ(code() % 2, 0); // Specified Double reg must be even. in low()
161 // Find high reg of a Doubel-reg pair, which is reg + 1. in high()
162 DCHECK_EQ(code() % 2, 0); // Specified Double reg mus in high()
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/third_party/node/deps/v8/src/codegen/mips/
H A Dregister-mips.h113 int ToNumber(Register reg);
137 // Find low reg of a Double-reg pair, which is the reg itself. in low()
138 DCHECK_EQ(code() % 2, 0); // Specified Double reg must be even. in low()
142 // Find high reg of a Doubel-reg pair, which is reg + 1. in high()
143 DCHECK_EQ(code() % 2, 0); // Specified Double reg must be even. in high()
/third_party/mesa3d/src/panfrost/midgard/
H A Dmidgard.h243 /* These are applied to the resulting value that's going to be stored in the dest reg.
739 /* Source/dest reg */
740 unsigned reg : 5; member
752 /* Arg reg, meaning changes according to each opcode */
/third_party/mesa3d/src/gallium/auxiliary/gallivm/
H A Dlp_bld_tgsi.h737 const struct tgsi_full_src_register *reg,
/third_party/skia/third_party/externals/swiftshader/src/Renderer/
H A DRenderer.hpp137 unsigned int reg[MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS]; // Offset used when reading from registers, in components member
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/Disassembler/
H A DX86DisassemblerDecoder.h459 /// All possible values of the reg field in the ModR/M byte.
620 // The reg field always encodes a register
621 Reg reg; member
/third_party/rust/crates/rustix/src/backend/linux_raw/io/
H A Derrno.rs15 use crate::backend::reg::{RetNumber, RetReg};
/third_party/node/deps/v8/src/compiler/backend/mips/
H A Dcode-generator-mips.cc619 Register reg = i.InputRegister(0); in AssembleArchInstruction() local
622 reg == kJavaScriptCallCodeStartRegister); in AssembleArchInstruction()
623 __ Call(reg, reg, Code::kHeaderSize - kHeapObjectTag); in AssembleArchInstruction()
667 Register reg = i.InputRegister(0); in AssembleArchInstruction() local
670 reg == kJavaScriptCallCodeStartRegister); in AssembleArchInstruction()
671 __ Addu(reg, reg, Code::kHeaderSize - kHeapObjectTag); in AssembleArchInstruction()
672 __ Jump(reg); in AssembleArchInstruction()
680 Register reg in AssembleArchInstruction() local
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/third_party/icu/ohos_icu4j/src/main/tests/ohos/global/icu/dev/test/util/
H A DULocaleTest.java463 * @param reg an object that supplies the registration and
467 Subobject sub, Registrar reg) { in checkService()
475 if (reg != null) { in checkService()
477 Object key = reg.register(req, obj); in checkService()
487 if (!reg.unregister(key)) { in checkService()
466 checkService(String requestedLocale, ServiceFacade svc, Subobject sub, Registrar reg) checkService() argument
/third_party/mesa3d/src/amd/addrlib/src/r800/
H A Dsiaddrlib.cpp2277 GB_ADDR_CONFIG reg; in DecodeGbRegs() local
2280 reg.val = pRegValue->gbAddrConfig; in DecodeGbRegs()
2282 switch (reg.f.pipe_interleave_size) in DecodeGbRegs()
2296 switch (reg.f.row_size) in DecodeGbRegs()
/third_party/node/deps/v8/src/codegen/arm64/
H A Dassembler-arm64.h76 inline Operand(Register reg, Shift shift = LSL,
82 inline Operand(Register reg, Extend extend, unsigned shift_amount = 0);
114 inline Register reg() const;
2457 inline const Register& AppropriateZeroRegFor(const CPURegister& reg) const;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
H A DMachineVerifier.cpp1341 report("G_BRJT src operand 2 must be a scalar reg type", MI); in verifyPreISelGenericInstruction()
1451 report("src operand 1 must be a scalar reg type", MI); in verifyPreISelGenericInstruction()
1703 report("Use-reg is not IsDebug in a DBG_VALUE", MO, MONum); in visitMachineOperand()
1798 report("No matching super-reg register class.", MO, MONum); in visitMachineOperand()
2375 assert(Reg == LI.reg && "Invalid reg to interval mapping"); in verifyLiveIntervals()
2702 unsigned Reg = LI.reg; in verifyLiveInterval()
2719 report_context(SR, LI.reg, SR.LaneMask); in verifyLiveInterval()
2722 verifyLiveRange(SR, LI.reg, SR.LaneMask); in verifyLiveInterval()
/third_party/skia/src/core/
H A DSkVM.h109 int reg; member
115 Operand(GP64 r) : reg (r), kind(REG ) {} in Operand()
116 Operand(Xmm r) : reg (r), kind(REG ) {} in Operand()
117 Operand(Ymm r) : reg (r), kind(REG ) {} in Operand()
/third_party/wpa_supplicant/wpa_supplicant-2.9_standard/wpa_supplicant/
H A Dp2p_supplicant.c4143 static void wpas_p2p_add_chan(struct p2p_reg_class *reg, u8 chan) in wpas_p2p_add_chan() argument
4145 reg->channel[reg->channels] = chan; in wpas_p2p_add_chan()
4146 reg->channels++; in wpas_p2p_add_chan()
4533 struct p2p_reg_class *reg = NULL, *cli_reg = NULL; local
4563 if (reg == NULL) {
4568 reg = &chan->reg_class[cla];
4570 reg->reg_class = o->op_class;
4572 if (reg->channels == P2P_MAX_REG_CLASS_CHANNELS)
4574 reg
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