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Searched refs:num_states (Results 26 - 50 of 102) sorted by relevance

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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn314/
H A Ddcn314_fpu.c150 .num_states = 5,
217 for (closest_clk_lvl = 0, j = dcn3_14_soc.num_states - 1; j >= 0; j--) { in dcn314_update_bw_bounding_box_fpu()
225 closest_clk_lvl = dcn3_14_soc.num_states - 1; in dcn314_update_bw_bounding_box_fpu()
259 dcn3_14_soc.num_states = clk_table->num_entries; in dcn314_update_bw_bounding_box_fpu()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddcn20_fpu.c289 .num_states = 5,
400 .num_states = 5,
511 .num_states = 5,
762 .num_states = 8
1843 unsigned int num_states) in dcn20_update_bounding_box()
1851 if (num_states == 0) in dcn20_update_bounding_box()
1867 for (i = 0; i < num_states; i++) { in dcn20_update_bounding_box()
1898 bb->num_states = num_calculated_states; in dcn20_update_bounding_box()
1902 bb->clock_limits[num_calculated_states].state = bb->num_states; in dcn20_update_bounding_box()
1913 for (i = 0; i < bb->num_states; in dcn20_cap_soc_clocks()
1839 dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb, struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states) dcn20_update_bounding_box() argument
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H A Ddcn20_fpu.h61 unsigned int num_states);
H A Ddisplay_mode_vba_20v2.c1320 mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states].dispclk_mhz, in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2671 for (k = 0; k <= mode_lib->vba.soc.num_states; k++) in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3548 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20v2_ModeSupportAndSystemConfigurationFull()
3630 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20v2_ModeSupportAndSystemConfigurationFull()
3981 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20v2_ModeSupportAndSystemConfigurationFull()
3983 mode_lib->vba.MaxDispclk[mode_lib->vba.soc.num_states], in dml20v2_ModeSupportAndSystemConfigurationFull()
4000 && i == mode_lib->vba.soc.num_states) in dml20v2_ModeSupportAndSystemConfigurationFull()
4007 && i == mode_lib->vba.soc.num_states) in dml20v2_ModeSupportAndSystemConfigurationFull()
4084 if (i != mode_lib->vba.soc.num_states) { in dml20v2_ModeSupportAndSystemConfigurationFull()
4116 for (i = 0; i <= mode_lib->vba.soc.num_states; in dml20v2_ModeSupportAndSystemConfigurationFull()
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H A Ddisplay_mode_vba_20.c1260 mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states].dispclk_mhz, in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2598 for (k = 0; k <= mode_lib->vba.soc.num_states; k++) in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3441 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20_ModeSupportAndSystemConfigurationFull()
3523 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20_ModeSupportAndSystemConfigurationFull()
3874 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20_ModeSupportAndSystemConfigurationFull()
3889 && i == mode_lib->vba.soc.num_states) in dml20_ModeSupportAndSystemConfigurationFull()
3896 && i == mode_lib->vba.soc.num_states) in dml20_ModeSupportAndSystemConfigurationFull()
3970 if (i != mode_lib->vba.soc.num_states) { in dml20_ModeSupportAndSystemConfigurationFull()
4002 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20_ModeSupportAndSystemConfigurationFull()
4019 for (i = 0; i <= mode_lib->vba.soc.num_states; in dml20_ModeSupportAndSystemConfigurationFull()
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_socbb.h78 uint32_t num_states; member
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_socbb.h78 uint32_t num_states; member
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_resource.c299 .num_states = 5,
410 .num_states = 5,
2715 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++)
2720 if (vlevel > context->bw_ctx.dml.soc.num_states)
2867 if (vlevel > context->bw_ctx.dml.soc.num_states)
2938 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =
3177 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
3426 for (i = 0; i < bb->num_states; i++) {
3461 for (i = bb->num_states - 1; i > 1; i--) {
3482 bb->num_states
3486 dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb, struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states) global() argument
3737 unsigned int num_states = 0; global() local
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H A Ddcn20_resource.h102 struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states);
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn21/
H A Ddcn21_resource.c304 .num_states = 8
1035 ASSERT(vlevel < dml->soc.num_states); in calculate_wm_set_for_vlevel()
1214 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); in dcn21_validate_bandwidth_fp()
1420 for (closest_clk_lvl = 0, j = dcn2_1_soc.num_states - 1; j >= 0; j--) { in update_bw_bounding_box()
1444 dcn2_1_soc.num_states = clk_table->num_entries; in update_bw_bounding_box()
1446 dcn2_1_soc.clock_limits[dcn2_1_soc.num_states] = dcn2_1_soc.clock_limits[dcn2_1_soc.num_states - 1]; in update_bw_bounding_box()
1447 dcn2_1_soc.clock_limits[dcn2_1_soc.num_states].state = dcn2_1_soc.num_states; in update_bw_bounding_box()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_resource.c1896 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++) in dcn20_validate_apply_pipe_split_flags()
1901 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn20_validate_apply_pipe_split_flags()
2050 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn20_fast_validate_bw()
2123 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = in dcn20_fast_validate_bw()
2344 unsigned int num_states = 0; in init_soc_bounding_box() local
2351 (&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states); in init_soc_bounding_box()
2366 if (clock_limits_available && uclk_states_available && num_states) { in init_soc_bounding_box()
2368 dcn20_update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states); in init_soc_bounding_box()
2566 if (loaded_bb->num_states == 1) { in dcn20_resource_construct()
2574 } else if (loaded_bb->num_states > in dcn20_resource_construct()
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/
H A Ddm_pp_smu.h229 unsigned int *clock_values_in_khz, unsigned int *num_states);
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/
H A Ddm_pp_smu.h229 unsigned int *clock_values_in_khz, unsigned int *num_states);
/third_party/musl/porting/liteos_m_iccarm/kernel/src/regex/
H A Dtre.h168 int num_states; member
/third_party/musl/porting/liteos_m/kernel/src/regex/
H A Dtre.h167 int num_states; member
/third_party/musl/porting/uniproton/kernel/src/regex/
H A Dtre.h167 int num_states; member
/third_party/musl/src/regex/
H A Dtre.h166 int num_states; member
/third_party/mesa3d/src/gallium/tools/trace/
H A Ddump_state.py307 def bind_sampler_states(self, shader, start, num_states, states):
312 def bind_vertex_sampler_states(self, num_states, states):
316 def bind_geometry_sampler_states(self, num_states, states):
320 def bind_fragment_sampler_states(self, num_states, states):
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dml/dcn30/
H A Ddisplay_mode_vba_30.c2059 v->soc.clock_limits[mode_lib->soc.num_states - 1].dispclk_mhz, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3955 for (i = 0; i < v->soc.num_states; i++) { in dml30_ModeSupportAndSystemConfigurationFull()
3964 if ((v->PlaneRequiredDISPCLKWithoutODMCombine >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states - 1] in dml30_ModeSupportAndSystemConfigurationFull()
3965 && v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states - 1])) { in dml30_ModeSupportAndSystemConfigurationFull()
3970 if ((v->PlaneRequiredDISPCLKWithODMCombine2To1 >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states - 1] in dml30_ModeSupportAndSystemConfigurationFull()
3971 && v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states - 1])) { in dml30_ModeSupportAndSystemConfigurationFull()
3976 if ((v->PlaneRequiredDISPCLKWithODMCombine4To1 >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states - 1] in dml30_ModeSupportAndSystemConfigurationFull()
3977 && v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states - 1])) { in dml30_ModeSupportAndSystemConfigurationFull()
4085 if (!(v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1] && v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states in dml30_ModeSupportAndSystemConfigurationFull()
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn30/
H A Ddisplay_mode_vba_30.c1990 v->soc.clock_limits[mode_lib->soc.num_states - 1].dispclk_mhz, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3854 for (i = 0; i < v->soc.num_states; i++) { in dml30_ModeSupportAndSystemConfigurationFull()
3863 if ((v->PlaneRequiredDISPCLKWithoutODMCombine >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states - 1] in dml30_ModeSupportAndSystemConfigurationFull()
3864 && v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states - 1])) { in dml30_ModeSupportAndSystemConfigurationFull()
3869 if ((v->PlaneRequiredDISPCLKWithODMCombine2To1 >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states - 1] in dml30_ModeSupportAndSystemConfigurationFull()
3870 && v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states - 1])) { in dml30_ModeSupportAndSystemConfigurationFull()
3875 if ((v->PlaneRequiredDISPCLKWithODMCombine4To1 >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states - 1] in dml30_ModeSupportAndSystemConfigurationFull()
3876 && v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states - 1])) { in dml30_ModeSupportAndSystemConfigurationFull()
3984 if (!(v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1] && v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states in dml30_ModeSupportAndSystemConfigurationFull()
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddisplay_mode_vba_32.c112 mode_lib->vba.MaxDppclk[v->soc.num_states - 1])); in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1654 start_state = v->soc.num_states - 1; in mode_support_configuration()
1658 for (i = v->soc.num_states - 1; i >= start_state; i--) { in mode_support_configuration()
1705 || i == v->soc.num_states - 1) in mode_support_configuration()
1710 || i == v->soc.num_states - 1 in mode_support_configuration()
1712 && (!mode_lib->vba.FCLKChangeRequirementFinal || i == v->soc.num_states - 1 in mode_support_configuration()
1741 start_state = v->soc.num_states - 1; in dml32_ModeSupportAndSystemConfigurationFull()
2033 for (i = start_state; i < v->soc.num_states; i++) { in dml32_ModeSupportAndSystemConfigurationFull()
2048 mode_lib->vba.MaxDispclk[v->soc.num_states - 1], in dml32_ModeSupportAndSystemConfigurationFull()
2071 mode_lib->vba.MaxDispclk[v->soc.num_states in dml32_ModeSupportAndSystemConfigurationFull()
[all...]
/third_party/mesa3d/src/virtio/virtio-gpu/
H A Dvirgl_protocol.h404 #define VIRGL_BIND_SAMPLER_STATES(num_states) ((num_states) + 2)
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddisplay_mode_vba_20v2.c1320 mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states].dispclk_mhz, in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2671 for (k = 0; k <= mode_lib->vba.soc.num_states; k++) in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3514 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20v2_ModeSupportAndSystemConfigurationFull()
3596 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20v2_ModeSupportAndSystemConfigurationFull()
3947 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20v2_ModeSupportAndSystemConfigurationFull()
3949 mode_lib->vba.MaxDispclk[mode_lib->vba.soc.num_states], in dml20v2_ModeSupportAndSystemConfigurationFull()
3966 && i == mode_lib->vba.soc.num_states) in dml20v2_ModeSupportAndSystemConfigurationFull()
3973 && i == mode_lib->vba.soc.num_states) in dml20v2_ModeSupportAndSystemConfigurationFull()
4050 if (i != mode_lib->vba.soc.num_states) { in dml20v2_ModeSupportAndSystemConfigurationFull()
4082 for (i = 0; i <= mode_lib->vba.soc.num_states; in dml20v2_ModeSupportAndSystemConfigurationFull()
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H A Ddisplay_mode_vba_20.c1260 mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states].dispclk_mhz, in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2598 for (k = 0; k <= mode_lib->vba.soc.num_states; k++) in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3441 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20_ModeSupportAndSystemConfigurationFull()
3523 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20_ModeSupportAndSystemConfigurationFull()
3874 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20_ModeSupportAndSystemConfigurationFull()
3889 && i == mode_lib->vba.soc.num_states) in dml20_ModeSupportAndSystemConfigurationFull()
3896 && i == mode_lib->vba.soc.num_states) in dml20_ModeSupportAndSystemConfigurationFull()
3970 if (i != mode_lib->vba.soc.num_states) { in dml20_ModeSupportAndSystemConfigurationFull()
4002 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20_ModeSupportAndSystemConfigurationFull()
4019 for (i = 0; i <= mode_lib->vba.soc.num_states; in dml20_ModeSupportAndSystemConfigurationFull()
[all...]
/third_party/mesa3d/src/gallium/drivers/iris/
H A Diris_resource.h206 unsigned num_states; member

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