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Searched refs:isUse (Results 26 - 50 of 113) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
H A DExpandPostRAPseudos.cpp80 (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) && in LowerSubregToReg()
H A DLiveRangeShrink.cpp144 if (MO.isUse()) in runOnMachineFunction()
H A DMachineCopyPropagation.cpp456 MIUse.isUse() && TRI->regsOverlap(Use.getReg(), MIUse.getReg())) in hasImplicitOverlap()
756 if (!MODef.isReg() || MODef.isUse()) in propagateDefs()
H A DLivePhysRegs.cpp95 assert(O->isUse()); in stepForward()
H A DMachineLICM.cpp1053 if (MO.isUse()) { in IsLoopInvariantInst()
1074 if (!MO.isUse()) in IsLoopInvariantInst()
1140 if (!MO.isReg() || !MO.isUse()) in HasHighOperandLatency()
H A DTargetInstrInfo.cpp627 assert(MI.getOperand(OpIdx).isUse() && "Folding load into def!"); in foldMemoryOperand()
934 if (MO.isUse()) { in isReallyTriviallyReMaterializableGeneric()
955 if (MO.isUse()) in isReallyTriviallyReMaterializableGeneric()
H A DMachinePipeliner.cpp795 } else if (MOI->isUse()) { in updatePhiDependences()
1556 if (MO.isReg() && MO.isUse()) { in computeLiveOuts()
2495 } else if (MO.isUse() && Writes && stageScheduled(*I) == StageInst1) { in orderDependence()
2504 } else if (MO.isUse() && Writes && stageScheduled(*I) > StageInst1) { in orderDependence()
2512 } else if (MO.isUse() && Writes && stageScheduled(*I) < StageInst1) { in orderDependence()
2517 } else if (MO.isUse() && stageScheduled(*I) == StageInst1 && in orderDependence()
2770 if (MO.isReg() && MO.isUse() && MO.getReg() == OverlapReg) { in fixupRegisterOverlaps()
H A DBranchFolding.cpp1853 if (MO.isUse()) { in findHoistingInsertPosAndDeps()
1886 if (!MO.isReg() || MO.isUse()) in findHoistingInsertPosAndDeps()
1919 if (MO.isUse()) { in findHoistingInsertPosAndDeps()
2037 if (!MO.isReg() || !MO.isUse() || !MO.isKill()) in HoistCommonCodeInSuccs()
H A DInlineSpiller.cpp558 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) in reMaterializeFor()
623 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) { in reMaterializeFor()
851 if (MO->isUse()) in foldMemoryOperand()
1042 if (MO.isUse()) { in spillAroundUses()
H A DDetectDeadLanes.cpp467 if (!MO.isUse()) in isUndefInput()
H A DExecutionDomainFix.cpp244 if (MO.isUse())
H A DImplicitNullChecks.cpp646 if (MO.isUse()) { in insertFaultingInstr()
H A DVirtRegMap.cpp542 if (MO.isUse()) { in rewrite()
H A DScheduleDAGInstrs.cpp303 SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output; in addPhysRegDeps()
861 if (!MO.isReg() || !MO.isUse()) in buildSchedGraph()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
H A DThumb2ITBlockPass.cpp93 if (MO.isUse()) in TrackDefUses()
H A DA15SDOptimizer.cpp191 if ((!MO.isReg()) || (!MO.isUse())) in eraseInstrWithNoUses()
403 if (!MO.isReg() || !MO.isUse()) in getReadDPRs()
H A DThumb2SizeReduction.cpp301 if (!MO.isReg() || MO.isUndef() || MO.isUse()) in canAddPseudoFlagDep()
975 if (!MO.isReg() || MO.isUndef() || MO.isUse()) in UpdateCPSRDef()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
H A DMachineOperand.h368 bool isUse() const { in isUse() function
458 return !isUndef() && !isInternalRead() && (isUse() || getSubReg()); in readsReg()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
H A DMipsOptimizePICCall.cpp130 if (!MO.isReg() || !MO.isUse() || !Register::isVirtualRegister(MO.getReg())) in getCallTargetRegOpnd()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
H A DAArch64CollectLOH.cpp535 assert(Op.isReg() && Op.isUse() && "Expected reg use"); in runOnMachineFunction()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/
H A DARCOptAddrMode.cpp407 if (!O.isReg() || !O.isUse()) in canHoistLoadStoreTo()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
H A DHexagonGenMux.cpp371 if (!Op.isReg() || !Op.isUse()) in genMuxInBlock()
H A DHexagonExpandCondsets.cpp321 if (!Op.isReg() || !Op.isUse() || Op.getReg() != Reg || in updateKillFlags()
1285 if (Op.isReg() && Op.isUse()) in runOnMachineFunction()
H A DHexagonVLIWPacketizer.cpp582 if (MO.isReg() && MO.isUse() && DefRegsSet.count(MO.getReg())) in getPostIncrementOperand()
804 if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == DepReg) in canPromoteToNewValueStore()
948 if (Op.isReg() && Op.getReg() && Op.isUse() && in getPredicatedRegister()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
H A DPPCBranchCoalescing.cpp348 && !(Op1.isUse() && MRI->isConstantPhysReg(Op1.getReg()))) { in identicalOperands()

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