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Searched refs:isReg (Results 76 - 100 of 337) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
H A DSIPreAllocateWWMRegs.cpp91 if (!MO.isReg()) in processDef()
125 if (!MO.isReg()) in rewriteRegs()
H A DSIFixSGPRCopies.cpp157 if (!MI.getOperand(i).isReg() || in hasVectorOperands()
440 if ((MO.isReg() && ((MO.isDef() && MO.getReg() != Reg) || !MO.isDef())) ||
441 (!MO.isImm() && !MO.isReg()) || (MO.isImm() && Imm)) {
708 if ((Src0.isReg() && TRI->isSGPRReg(*MRI, Src0.getReg()) &&
710 (Src1.isReg() && TRI->isSGPRReg(*MRI, Src1.getReg()) &&
723 if (Def.isReg() &&
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/MCTargetDesc/
H A DARCInstPrinter.cpp143 if (Op.isReg()) { in printOperand()
161 assert(base.isReg() && "Base should be register."); in printMemOperandRI()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/
H A DAVRAsmPrinter.cpp98 assert(RegOp.isReg() && "Operand must be a register when you're" in PrintAsmOperand()
145 assert(MO.isReg() && "Unexpected inline asm memory operand"); in PrintAsmMemoryOperand()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/MCTargetDesc/
H A DBPFMCCodeEmitter.cpp90 if (MO.isReg()) in getMachineOpValue()
163 assert(Op1.isReg() && "First operand is not register."); in getMemoryOpValue()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
H A DLiveVariables.h218 if (MO.isReg() && MO.isKill() && MO.getReg() == reg) { in removeVirtualRegisterKilled()
254 if (MO.isReg() && MO.isDef() && MO.getReg() == reg) { in removeVirtualRegisterDead()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
H A DAggressiveAntiDepBreaker.cpp232 if (!MO.isReg() || !MO.isImplicit())
252 if (!MO.isReg()) continue;
367 if (!MO.isReg() || !MO.isDef()) continue;
377 if (!MO.isReg() || !MO.isDef()) continue;
420 if (!MO.isReg() || !MO.isDef()) continue;
473 if (!MO.isReg() || !MO.isUse()) continue;
508 if (!MO.isReg()) continue;
H A DTwoAddressInstructionPass.cpp231 if (!MO.isReg()) in sink3AddrInstruction()
300 if (!MO.isReg()) in sink3AddrInstruction()
505 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg) in isTwoAddrUse()
911 if (!MO.isReg()) in rescheduleMIBelowKill()
955 if (!MO.isReg()) in rescheduleMIBelowKill()
1093 if (!MO.isReg()) in rescheduleKillAboveMI()
1130 if (!MO.isReg()) in rescheduleKillAboveMI()
1218 if (OtherOpIdx == BaseOpIdx || !MI->getOperand(OtherOpIdx).isReg() || in tryInstructionCommute()
1400 if (MO.isReg() && Register::isVirtualRegister(MO.getReg())) { in tryInstructionTransform()
1428 if (MO.isReg()) in tryInstructionTransform()
[all...]
H A DCriticalAntiDepBreaker.cpp189 if (!MO.isReg()) continue; in PrescanInstruction()
284 if (!MO.isReg()) continue; in ScanInstruction()
315 if (!MO.isReg()) continue; in ScanInstruction()
377 if (!CheckOper.isReg() || !CheckOper.isDef() || in isNewRegClobberedByRefs()
625 if (!MO.isReg()) continue; in BreakAntiDependencies()
H A DLiveRangeEdit.cpp113 if (!MO.isReg() || !MO.getReg() || !MO.readsReg()) in allUsesAvailableAt()
292 if (VRM && MI->getOperand(0).isReg() && MI->getOperand(0).isDef() && in eliminateDeadDef()
309 if (!MOI->isReg()) in eliminateDeadDef()
352 if (MO.isReg() && Register::isPhysicalRegister(MO.getReg())) in eliminateDeadDef()
H A DBreakFalseDeps.cpp131 if (!CurrMO.isReg() || CurrMO.isDef() || CurrMO.isUndef() || in pickBestRegisterForUndef()
203 if (!MO.isReg() || !MO.getReg()) in processDefs()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/
H A DBPFMIPeephole.cpp87 if (!opnd.isReg()) in isCopyFrom32Def()
112 if (!opnd.isReg()) in isPhiFrom32Def()
467 if (!opnd.isReg()) { in eliminateTruncSeq()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/
H A DMachineLocation.h46 bool isReg() const { return IsRegister; } in isReg() function
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCChecker.cpp93 if (MCI.getOperand(i).isReg()) in init()
183 if (MCI.getOperand(i).isReg()) { in init()
417 assert(Op.isReg()); in checkNewValues()
499 assert(Operand.isReg() && "Def is not a register"); in checkRegistersReadOnly()
517 if (Operand.isReg() && Operand.getReg() == Register) in registerUsed()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
H A DAArch64CollectLOH.cpp474 if (!MO.isReg() || !MO.isDef()) in handleNormalInst()
485 if (!MO.isReg() || !MO.readsReg()) in handleNormalInst()
534 assert(Def.isReg() && Def.isDef() && "Expected reg def"); in runOnMachineFunction()
535 assert(Op.isReg() && Op.isUse() && "Expected reg use"); in runOnMachineFunction()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
H A DPPCBranchCoalescing.cpp344 if (Op1.isReg() && in identicalOperands()
359 if (Op1.isReg() && Op2.isReg() && in identicalOperands()
461 if (Use.isReg() && Register::isVirtualRegister(Use.getReg())) { in canMoveToEnd()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
H A DDelaySlotFiller.cpp253 if (!MO.isReg()) in delayHasHazard()
303 assert(Reg.isReg() && "CALL first operand is not a register."); in insertCallDefsUses()
310 assert(Operand1.isReg() && "CALLrr second operand is not a register."); in insertCallDefsUses()
324 if (!MO.isReg()) in insertDefsUses()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/AsmParser/
H A DLanaiAsmParser.cpp155 assert(isReg() && "Invalid type access!");
190 bool isReg() const override { return Kind == REGISTER; }
1113 else if (Operands[0]->isToken() && Operands[1]->isReg() && in IsMemoryAssignmentError()
1114 Operands[2]->isImm() && Operands[3]->isImm() && Operands[4]->isReg()) in IsMemoryAssignmentError()
1117 Operands[2]->isReg() && Operands[3]->isImm() && in IsMemoryAssignmentError()
1118 Operands[4]->isImm() && Operands[5]->isReg()) in IsMemoryAssignmentError()
1132 return Modifies && Operands[PossibleBaseIdx]->isReg() && in IsMemoryAssignmentError()
1133 Operands[PossibleDestIdx]->isReg() && in IsMemoryAssignmentError()
1139 return static_cast<const LanaiOperand &>(op).isReg(); in IsRegister()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
H A DWebAssemblyRegStackify.cpp335 if (!MO.isReg() || MO.isUndef()) in isSafeToMove()
392 if (MO.isReg() && MO.isDef() && MO.getReg() == Reg) in isSafeToMove()
437 if (!MO.isReg()) in oneUseDominatesOtherUses()
712 if (MO.isReg() && MO.getReg() == Reg) in isOnStack()
807 if (!Op.isReg()) in runOnMachineFunction()
916 if (!MO.isReg()) in runOnMachineFunction()
H A DWebAssemblyInstrInfo.cpp197 bool IsBrOnExn = Cond[1].isReg() && MRI.getRegClass(Cond[1].getReg()) == in insertBranch()
227 if (Cond[1].isReg() && in reverseBranchCondition()
/base/telephony/call_manager/services/call_earthquake_alarm/src/
H A Dcall_earthquake_alarm_subscriber.cpp130 bool DataShareSwitchState::RegisterListenSettingsKey(std::string key, bool isReg, in RegisterListenSettingsKey() argument
142 if (isReg) { in RegisterListenSettingsKey()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
H A DThumb2ITBlockPass.cpp88 if (!MO.isReg()) in TrackDefUses()
115 if (!MO.isReg() || MO.isDef() || !MO.isKill()) in ClearKillFlags()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/MCTargetDesc/
H A DMSP430MCCodeEmitter.cpp105 if (MO.isReg()) in getMachineOpValue()
124 assert(MO1.isReg() && "Register operand expected"); in getMemOpValue()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
H A DMipsSEFrameLowering.cpp171 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI()); in expandLoadCCond()
186 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI()); in expandStoreCCond()
204 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI()); in expandLoadACC()
229 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI()); in expandStoreACC()
305 if (I->getNumOperands() == 4 && I->getOperand(3).isReg() in expandBuildPairF64()
348 if ((Op1.isReg() && Op1.isUndef()) || (Op2.isReg() && Op2.isUndef())) { in expandExtractElementF64()
370 if (I->getNumOperands() == 4 && I->getOperand(3).isReg() in expandExtractElementF64()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/
H A DInstructionSelectorImpl.h95 if (!MO.isReg()) { in executeMatchTable()
199 if (!MO.isReg()) in executeMatchTable()
204 if (!MO.isReg()) { in executeMatchTable()
486 if (!MO.isReg()) { in executeMatchTable()
528 if (!MO.isReg() || in executeMatchTable()
557 if (MO.isReg()) { in executeMatchTable()
576 if (!MO.isReg() || in executeMatchTable()
620 if (MO.isReg()) { in executeMatchTable()

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