Home
last modified time | relevance | path

Searched refs:isReg (Results 301 - 325 of 327) sorted by relevance

1...<<11121314

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp405 !MI.getOperand(VDstIn_Idx).isReg() || in getInstruction()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/
H A DBTFDebug.cpp989 for (; MI->getOperand(NumDefs).isReg() && MI->getOperand(NumDefs).isDef(); in beginInstruction()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/Disassembler/
H A DHexagonDisassembler.cpp460 assert(MCO.isReg() && "New value consumers must be registers"); in getSingleInstruction()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCCodeEmitter.cpp783 if (MO.isReg()) {
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
H A DWebAssemblyCFGStackify.cpp716 if (!MO.isReg() || Register::isPhysicalRegister(MO.getReg())) in unstackifyVRegsUsedInSplitBB()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGISel.cpp1658 if (!OPI->isReg() || !OPI->isDef()) in MIIsInTerminatorSequence()
1673 if (!OPI2->isReg() || (!Register::isPhysicalRegister(OPI->getReg()) && in MIIsInTerminatorSequence()
H A DFastISel.cpp171 if (!MO.isReg()) in findSinkableLocalRegDef()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/
H A DAVRExpandPseudoInsts.cpp878 if (MO.isReg() && MO.getReg() != 0 && !MO.isDef() && in scavengeGPR8()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/AsmParser/
H A DPPCAsmParser.cpp407 bool isReg() const override { return false; }
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCCodeEmitter.cpp1187 if (!MO.isReg()) in determineREXPrefix()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
H A DX86InstructionSelector.cpp476 assert(I.getOperand(0).isReg() && "unsupported opperand."); in X86SelectAddress()
H A DX86FastISel.cpp3958 if (!MO.isReg() || MO.isDef() || MO.getReg() != AM.IndexReg) in tryToFoldLoadIntoMI()
H A DX86ISelLowering.cpp[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp3524 MI.getOperand(1).isReg() ? RegInfo.getRegClass(MI.getOperand(1).getReg()) in emitST_F16_PSEUDO()
3576 MI.getOperand(1).isReg() ? RegInfo.getRegClass(MI.getOperand(1).getReg()) in emitLD_F16_PSEUDO()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp1022 bool isReg() const override {
3926 if (Inst.getOperand(i).isReg() && in validateInstruction()
3940 if (Inst.getOperand(i).isReg() && in validateInstruction()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructionSelector.cpp212 if (MO.isReg()) { in getSubOperand64()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/AsmParser/
H A DHexagonAsmParser.cpp263 bool isReg() const override { return Kind == Register; }
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
H A DHexagonFrameLowering.cpp305 if (MO.isReg()) { in needsStackFrame()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
H A DARMExpandPseudoInsts.cpp98 assert(MO.isReg() && MO.getReg()); in TransferImpOps()
H A DARMFastISel.cpp256 if (!MO.isReg() || !MO.isDef()) continue; in DefinesOptionalPredicate()
H A DARMISelLowering.cpp9986 if (!OI->isReg()) continue; in EmitSjLjDispatchBlock()
10900 if (op.isReg() && op.isUse()) { in AdjustInstrPostInstrSelection()
10928 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) { in AdjustInstrPostInstrSelection()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp1293 return MO.isReg() && MO.isUse() && SelectDests.count(MO.getReg()); in emitSelectPseudo()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/MC/MCParser/
H A DAsmParser.cpp5809 if (Operand.isReg() && !Operand.needAddressOf() && in parseMSInlineAsm()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp75 if (Op.isReg()) in earlyUseOperand()
6728 if (Base.isReg()) in forceReg()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp2070 if (Opnd.isReg()) { in selectLoad()

Completed in 152 milliseconds

1...<<11121314