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Searched refs:isReg (Results 26 - 50 of 328) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
H A DLivePhysRegs.cpp60 if (!MOP.isReg() || !MOP.readsReg()) in addUses()
84 if (O->isReg() && !O->isDebug()) { in stepForward()
106 if (Reg.second->isReg() && Reg.second->isDead()) in stepForward()
288 if (!MO->isReg() || !MO->isDef() || MO->isDebug()) in recomputeLivenessFlags()
305 if (!MO->isReg() || !MO->readsReg() || MO->isDebug()) in recomputeLivenessFlags()
H A DReachingDefAnalysis.cpp107 if (!MO.isReg() || !MO.getReg())
238 if (!MO.isReg() || !MO.isUse() || MO.getReg() != PhysReg)
287 if (MO.isReg() && MO.isDef() && MO.getReg() == PhysReg)
303 if (MO.isReg() && MO.isDef() && MO.getReg() == PhysReg)
317 if (MO.isReg() && MO.isUse() && MO.getReg() == PhysReg)
H A DMachineLICM.cpp460 if (!MO.isReg()) in ProcessMI()
562 if (!MO.isReg()) in HoistRegionPostRA()
590 if (!MO.isReg() || MO.isDef() || !MO.getReg()) in HoistRegionPostRA()
615 if (!MO.isReg() || !MO.getReg() || MO.isDef()) continue; in AddToLiveIns()
805 if (!MO.isDef() || !MO.isReg() || !MO.getReg()) in SinkIntoLoop()
888 if (!MO.isReg() || MO.isImplicit()) in calcRegisterCost()
959 if (MO.isReg()) { in isInvariantStore()
1045 if (!MO.isReg()) in IsLoopInvariantInst()
1097 if (!MO.isReg() || !MO.isDef()) in HasLoopPHIUse()
1140 if (!MO.isReg() || !M in HasHighOperandLatency()
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H A DMachineSink.cpp435 if (MO.isReg() && MO.getReg().isVirtual()) in ProcessDbgInst()
465 if (!MO.isReg() || !MO.isUse()) in isWorthBreakingCriticalEdge()
664 if (!MO.isReg()) continue; // Ignore non-register operands. in FindSuccToSinkTo()
770 if (!BaseOp->isReg()) in SinkingPreventsImplicitNullCheck()
780 return MBP.LHS.isReg() && MBP.RHS.isImm() && MBP.RHS.getImm() == 0 && in SinkingPreventsImplicitNullCheck()
915 if (!MO.isReg()) continue; in SinkInstruction()
988 if (!MO.isReg() || !MO.isDef() || !MO.getReg().isVirtual()) in SinkInstruction()
1022 if (MO.isReg() && MO.isUse()) in SinkInstruction()
1032 assert(MI.getOperand(1).isReg()); in SalvageUnsunkDebugUsersOfCopy()
1040 if (!MO.isReg() || !M in SalvageUnsunkDebugUsersOfCopy()
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H A DMachineVerifier.cpp888 if (!MO.isReg() || !MO.isImplicit()) in verifyInlineAsm()
935 if (!MO->isReg()) { in verifyPreISelGenericInstruction()
959 if (MO->isReg() && Register::isPhysicalRegister(MO->getReg())) in verifyPreISelGenericInstruction()
1042 if (!MO.isReg()) in verifyPreISelGenericInstruction()
1280 if (!SrcOp.isReg()) { in verifyPreISelGenericInstruction()
1302 if (!SrcOp.isReg()) { in verifyPreISelGenericInstruction()
1340 if (!IdxOp.isReg() || MRI->getType(IdxOp.getReg()).isPointer()) in verifyPreISelGenericInstruction()
1445 if (!DstOp.isReg() || !MRI->getType(DstOp.getReg()).isPointer()) { in verifyPreISelGenericInstruction()
1450 if (!AllocOp.isReg() || !MRI->getType(AllocOp.getReg()).isScalar()) { in verifyPreISelGenericInstruction()
1584 NumDefs = (MONum == 0 && MO->isReg()) in visitMachineOperand()
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H A DMachineInstrBundle.cpp64 if (MO.isReg() && MO.isInternalRead()) in runOnMachineFunction()
151 if (!MO.isReg()) in finalizeBundle()
287 if (!MO.isReg() || MO.getReg() != Reg) in AnalyzeVirtRegInBundle()
326 if (!MO.isReg()) in AnalyzePhysRegInBundle()
H A DMachineOperand.cpp100 assert(isReg() && "Wrong MachineOperand accessor"); in setIsDef()
117 assert(isReg() && "Wrong MachineOperand accessor"); in isRenamable()
135 assert(isReg() && "Wrong MachineOperand accessor"); in setIsRenamable()
144 if (!isReg() || !isOnRegUseList()) in removeRegFromUses()
155 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm"); in ChangeToImmediate()
164 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm"); in ChangeToFPImmediate()
174 assert((!isReg() || !isTied()) && in ChangeToES()
187 assert((!isReg() || !isTied()) && in ChangeToGA()
199 assert((!isReg() || !isTied()) && in ChangeToMCSymbol()
209 assert((!isReg() || !isTie in ChangeToFrameIndex()
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H A DRegAllocFast.cpp892 if (!MO.isReg()) continue; in handleThroughOperands()
907 if (!MO.isReg() || !MO.isDef()) continue; in handleThroughOperands()
922 if (!MO.isReg()) continue; in handleThroughOperands()
948 if (!MO.isReg()) continue; in handleThroughOperands()
963 if (!MO.isReg() || (MO.isDef() && !MO.isEarlyClobber())) continue; in handleThroughOperands()
1046 if (!MO.isReg()) continue; in allocateInstruction()
1097 if (!MO.isReg()) continue; in allocateInstruction()
1125 if (!MO.isReg() || !MO.isUse()) in allocateInstruction()
1141 if (!MO.isReg()) continue; in allocateInstruction()
1168 if (!MO.isReg() || !M in allocateInstruction()
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H A DExpandPostRAPseudos.cpp72 if (MO.isReg()) in TransferImplicitOperands()
78 assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) && in LowerSubregToReg()
80 (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) && in LowerSubregToReg()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp278 if (!BaseOp || !BaseOp->isReg()) in getMemOperandWithOffset()
314 if (!BaseOp->isReg()) in getMemOperandWithOffset()
327 if (SOffset && SOffset->isReg()) { in getMemOperandWithOffset()
358 if (!BaseOp->isReg()) in getMemOperandWithOffset()
373 if (!BaseOp->isReg()) in getMemOperandWithOffset()
393 if (!BaseOp->isReg()) in getMemOperandWithOffset()
407 if (!BaseOp1.isReg() || !BaseOp2.isReg()) in memOpsHaveSameBasePtr()
630 assert(DefOp.isReg() || DefOp.isImm()); in copyPhysReg()
632 if (DefOp.isReg()) { in copyPhysReg()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
H A DX86AvoidStoreForwardingBlocks.cpp319 if (!((Base.isReg() && Base.getReg() != X86::NoRegister) || Base.isFI())) in isRelevantAddressingMode()
325 if (!(Index.isReg() && Index.getReg() == X86::NoRegister)) in isRelevantAddressingMode()
327 if (!(Segment.isReg() && Segment.getReg() == X86::NoRegister)) in isRelevantAddressingMode()
407 if (LoadBase.isReg()) in buildCopy()
428 if (StoreBase.isReg()) in buildCopy()
431 assert(StoreSrcVReg.isReg() && "Expected virtual register"); in buildCopy()
504 if (LoadBase.isReg()) { in updateKillStatus()
514 if (StoreBase.isReg()) { in updateKillStatus()
621 if (LoadBase.isReg() != StoreBase.isReg()) in hasSameBaseOpValue()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/MC/
H A DMCInstrDesc.cpp56 if (MI.getOperand(i).isReg() && in hasDefOfPhysReg()
61 if (MI.getOperand(i).isReg() && in hasDefOfPhysReg()
H A DMCInstPrinter.cpp83 return Opnd.isReg() && Opnd.getReg() == C.Value; in matchAliasCondition()
86 return Opnd.isReg() && Opnd.getReg() == MI.getOperand(C.Value).getReg(); in matchAliasCondition()
89 return Opnd.isReg() && MRI.getRegClass(C.Value).contains(Opnd.getReg()); in matchAliasCondition()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/
H A DMCInst.h57 bool isReg() const { return Kind == kRegister; } in isReg() function in llvm::MCOperand
65 assert(isReg() && "This is not a register operand!"); in getReg()
71 assert(isReg() && "This is not a register operand!"); in setReg()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
H A DHexagonSplitDouble.cpp179 if (MI->getOperand(1).isReg()) in isFixedInstr()
184 if (MI->getOperand(0).isReg()) in isFixedInstr()
211 if (!Op.isReg()) in isFixedInstr()
259 if (&MO == &Op || !MO.isReg() || MO.getSubReg()) in partitionRegisters()
443 if (Op.isReg() && Part.count(Op.getReg())) in isProfitable()
500 assert(Cond[1].isReg() && "Unexpected Cond vector from analyzeBranch"); in collectIndRegsForLoop()
601 if (!Op.isReg()) { in createHalfInstr()
704 assert(Op0.isReg() && Op1.isImm()); in splitImmediate()
732 assert(Op0.isReg()); in splitCombine()
740 if (!Op1.isReg()) { in splitCombine()
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H A DHexagonGenMux.cpp172 if (!MO.isReg() || MO.isImplicit()) in getDefsUses()
210 bool IsReg1 = Src1.isReg(), IsReg2 = Src2.isReg(); in getMuxOpcode()
306 Register SR1 = Src1->isReg() ? Src1->getReg() : Register(); in genMuxInBlock()
307 Register SR2 = Src2->isReg() ? Src2->getReg() : Register(); in genMuxInBlock()
371 if (!Op.isReg() || !Op.isUse()) in genMuxInBlock()
H A DHexagonAsmPrinter.cpp131 if (!MO.isReg()) in PrintAsmOperand()
165 if (Base.isReg()) in PrintAsmMemoryOperand()
375 assert(Rt.isReg() && "Expected register and none was found"); in HexagonProcessInstruction()
386 assert(Rt.isReg() && "Expected register and none was found"); in HexagonProcessInstruction()
398 assert(Rt.isReg() && "Expected register and none was found"); in HexagonProcessInstruction()
410 assert(Rs.isReg() && "Expected register and none was found"); in HexagonProcessInstruction()
595 assert(Rt.isReg() && "Expected register and none was found"); in HexagonProcessInstruction()
607 assert(Inst.getOperand(0).isReg() && in HexagonProcessInstruction()
620 assert (Inst.getOperand(0).isReg() && in HexagonProcessInstruction()
H A DHexagonCopyToCombine.cpp134 assert(Op0.isReg() && Op1.isReg()); in isCombinableInstType()
147 assert(Op0.isReg()); in isCombinableInstType()
240 if (!Op.isReg() || Op.getReg() != RegNotKilled || !Op.isKill()) in removeKillInfo()
258 return MO.isReg() ? MO.getReg() : Register(); in UseReg()
409 if (!Op.isReg() || !Op.isUse() || !Op.getReg()) in findPotentialNewifiableTFRs()
442 if (Op.isReg()) { in findPotentialNewifiableTFRs()
608 bool IsHiReg = HiOperand.isReg(); in combine()
609 bool IsLoReg = LoOperand.isReg(); in combine()
H A DHexagonVectorPrint.cpp110 if (MI.getOperand(0).isReg() && MI.getOperand(0).isDef()) { in getInstrVecReg()
116 if (MI.mayStore() && MI.getNumOperands() >= 3 && MI.getOperand(2).isReg()) { in getInstrVecReg()
122 if (MI.mayStore() && MI.getNumOperands() >= 4 && MI.getOperand(3).isReg()) { in getInstrVecReg()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCCodeEmitter.cpp750 if (MO.isReg()) { in getMachineOpValue()
772 assert(MI.getOperand(OpNo).isReg()); in getMemEncoding()
788 assert(MI.getOperand(OpNo).isReg()); in getMemEncodingMMImm4()
802 assert(MI.getOperand(OpNo).isReg()); in getMemEncodingMMImm4Lsl1()
816 assert(MI.getOperand(OpNo).isReg()); in getMemEncodingMMImm4Lsl2()
830 assert(MI.getOperand(OpNo).isReg() && in getMemEncodingMMSPImm5Lsl2()
845 assert(MI.getOperand(OpNo).isReg() && in getMemEncodingMMGPImm7Lsl2()
860 assert(MI.getOperand(OpNo).isReg()); in getMemEncodingMMImm9()
874 assert(MI.getOperand(OpNo).isReg()); in getMemEncodingMMImm11()
898 assert(MI.getOperand(OpNo).isReg()); in getMemEncodingMMImm12()
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H A DMipsNaClELFStreamer.cpp62 assert(MI.getOperand(0).isReg()); in isIndirectJump()
69 return (MI.getNumOperands() > 0 && MI.getOperand(0).isReg() in isStackPointerFirstOperand()
92 assert(MI.getOperand(0).isReg()); in isCall()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
H A DInstructionSelector.cpp51 if (MO.isReg() && MO.getReg()) in isOperandImmEqual()
59 if (!Root.isReg()) in isBaseWithConstantOffset()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/MCA/
H A DInstrBuilder.cpp224 if (Op.isReg())
236 if (I == MCI.getNumOperands() || !Op.isReg()) {
311 if (!Op.isReg())
397 if (!Op.isReg())
432 if (!Op.isReg())
468 if (!Op.isReg())
638 if (!Op.isReg())
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiInstPrinter.cpp153 if (Op.isReg()) in printOperand()
215 assert(RegOp.isReg() && "Register operand expected"); in printMemoryBaseRegister()
259 assert(OffsetOp.isReg() && RegOp.isReg() && "Registers expected."); in printMemRrOperand()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/AsmParser/
H A DSystemZAsmParser.cpp219 bool isReg() const override {
222 bool isReg(RegisterKind RegKind) const { in isReg() function in __anon24823::SystemZOperand
346 bool isGR32() const { return isReg(GR32Reg); } in isGR32()
347 bool isGRH32() const { return isReg(GRH32Reg); } in isGRH32()
349 bool isGR64() const { return isReg(GR64Reg); } in isGR64()
350 bool isGR128() const { return isReg(GR128Reg); } in isGR128()
351 bool isADDR32() const { return isReg(ADDR32Reg); } in isADDR32()
352 bool isADDR64() const { return isReg(ADDR64Reg); } in isADDR64()
354 bool isFP32() const { return isReg(FP32Reg); } in isFP32()
355 bool isFP64() const { return isReg(FP64Re in isFP32()
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