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Searched refs:isReg (Results 226 - 250 of 337) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
H A DHexagonBitTracker.cpp169 if (MO.isReg()) in RegisterRefs()
196 if (!MO.isReg() || !MO.isDef())
271 if (!Op.isReg())
1043 if (!Op.isReg() || !Op.isDef())
1190 assert(MD.isReg() && MD.isDef());
H A DRDFDeadCode.cpp67 if (Op.isReg() && MRI.isReserved(Op.getReg())) in isLiveInstr()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
H A DCSEInfo.cpp340 if (MO.isReg()) { in addNodeIDMachineOperand()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
H A DAArch64CondBrTuning.cpp94 if (MO.isReg() && MO.isDead() && MO.getReg() == AArch64::NZCV) in convertToFlagSetting()
H A DAArch64FalkorHWPFFix.cpp669 else if (LI.OffsetOpnd->isReg()) in getTag()
747 if (MO.isReg() && MO.readsReg()) in runOnLoop()
H A DAArch64RegisterBankInfo.cpp620 if (!MO.isReg() || !MO.getReg()) in getInstrMapping()
841 if (MI.getOperand(Idx).isReg() && MI.getOperand(Idx).getReg()) { in getInstrMapping()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/Disassembler/
H A DLanaiDisassembler.cpp112 if (Instr.getOperand(2).isReg()) { in PostOperandDecodeAdjust()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/MCTargetDesc/
H A DSystemZInstPrinter.cpp44 if (MO.isReg()) { in printOperand()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.h129 bool isIndirect() { return Target != nullptr && Target->isReg(); } in isIndirect()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/MCTargetDesc/
H A DWebAssemblyInstPrinter.cpp212 if (Op.isReg()) {
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
H A DX86FixupBWInsts.cpp261 if (!MO.isReg()) in getSuperRegDestIfDead()
H A DX86WinAllocaExpander.cpp82 assert(MI->getOperand(0).isReg()); in getWinAllocaAmount()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
H A DMachinePipeliner.cpp770 if (!MOI->isReg()) in updatePhiDependences()
1556 if (MO.isReg() && MO.isUse()) { in computeLiveOuts()
1567 if (MO.isReg() && MO.isDef() && !MO.isDead()) { in computeLiveOuts()
2064 if (!BaseOp->isReg()) in computeDelta()
2475 if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg())) in orderDependence()
2619 if (!MO.isReg()) in isLoopCarriedDefOfUse()
2631 if (!DMO.isReg() || !DMO.isDef()) in isLoopCarriedDefOfUse()
2770 if (MO.isReg() && MO.isUse() && MO.getReg() == OverlapReg) { in fixupRegisterOverlaps()
H A DMachineTraceMetrics.cpp662 if (!MO.isReg())
710 if (!MO.isReg())
904 if (!MO.isReg())
H A DEarlyIfConversion.cpp261 if (!MO.isReg()) in InstrDependenciesAllowIfConv()
381 if (!MO.isReg()) in findInsertionPoint()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.h685 return MO.isReg() && RI.isVGPR(MRI, MO.getReg());}); in hasVGPRUses()
825 if (MO.isReg()) { in getOpSize()
1067 assert(O.isReg()); in getRegSubRegPair()
H A DR600ControlFlowFinalizer.cpp303 if (!MO.isReg()) in isCompatibleWithClause()
429 if (MO.isReg() && MO.isInternalRead()) in MakeALUClause()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
H A DThumb1FrameLowering.cpp642 if (MO.isReg() && (MO.isImplicit() || MO.isDef())) in emitPopSpecialFixUp()
757 if (MO.isReg() && (MO.isImplicit() || MO.isDef()) && in emitPopSpecialFixUp()
979 if (Op.isReg()) in restoreCalleeSavedRegisters()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCDuplexInfo.cpp634 if ((MIb.getNumOperands() > 1) && MIb.getOperand(1).isReg() && in isOrderedDuplexPair()
637 if ((MIb.getNumOperands() > 0) && MIb.getOperand(0).isReg() && in isOrderedDuplexPair()
665 if (Inst.getOperand(opNum).isReg()) { in addOps()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
H A DMipsAsmPrinter.cpp578 if (Subtarget->isGP64bit() && NumVals == 1 && MO.isReg()) { in PrintAsmOperand()
603 if (!MO.isReg()) in PrintAsmOperand()
630 assert(BaseMO.isReg() && in PrintAsmMemoryOperand()
H A DMipsDelaySlotFiller.cpp330 if (!MO.isReg() || !MO.isDef() || !(R = MO.getReg())) in addLiveInRegs()
419 if (MO.isReg() && MO.getReg()) { in update()
/foundation/communication/netmanager_base/services/netconnmanager/include/
H A Dnet_conn_service.h441 int32_t RegUnRegNetDetectionCallback(int32_t netId, const sptr<INetDetectionCallback> &callback, bool isReg);
457 int32_t RegUnRegNetDetectionCallbackAsync(int32_t netId, const sptr<INetDetectionCallback> &callback, bool isReg);
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
H A DPPCReduceCRLogicals.cpp67 if (MI.getOperand(i - 1).isReg()) { in updatePHIs()
233 assert(FirstTerminator->getOperand(0).isReg() && in splitMBB()
H A DPPCVSXSwapRemoval.cpp254 if (!MO.isReg()) in gatherVectorInstructions()
601 if (!MO.isReg()) in formWebs()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.cpp500 return (MI.getOperand(1).isReg() && MI.getOperand(1).getReg() == RISCV::X0); in isAsCheapAsAMove()
573 if (!LdSt.getOperand(1).isReg() || !LdSt.getOperand(2).isImm()) in getMemOperandWithOffsetWidth()

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