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Searched refs:isReg (Results 201 - 225 of 327) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
H A DX86InstrInfo.cpp197 MI.getOperand(Op + X86::AddrIndexReg).isReg() && in isFrameOperand()
600 if (MI.getOperand(1 + X86::AddrBaseReg).isReg() && in isReallyTriviallyReMaterializable()
602 MI.getOperand(1 + X86::AddrIndexReg).isReg() && in isReallyTriviallyReMaterializable()
621 MI.getOperand(1 + X86::AddrIndexReg).isReg() && in isReallyTriviallyReMaterializable()
623 !MI.getOperand(1 + X86::AddrDisp).isReg()) { in isReallyTriviallyReMaterializable()
625 if (!MI.getOperand(1 + X86::AddrBaseReg).isReg()) in isReallyTriviallyReMaterializable()
675 if (MO.isReg() && MO.isDef() && in hasLiveCondCodeDef()
912 if (MI.getOperand(2).isReg() && MI.getOperand(2).isUndef()) in convertToThreeAddress()
2132 if (!MI.getOperand(SrcOpIdx1).isReg() ||
2133 !MI.getOperand(SrcOpIdx2).isReg())
[all...]
H A DX86AsmPrinter.cpp502 if (MO.isReg()) { in PrintAsmOperand()
515 if (MO.isReg()) in PrintAsmOperand()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
H A DHexagonBitSimplify.cpp292 if (!Op.isReg() || !Op.isDef()) in getInstrDefs()
304 if (!Op.isReg() || !Op.isUse()) in getInstrUses()
1017 if (!Op.isReg() || !Op.isDef())
1259 assert(MI.getOperand(OpN).isReg());
1327 if (!Op.isReg())
1954 if (!MI->getOperand(0).isReg())
2141 if (!Op.isReg())
2724 if (!Op0.isReg() || !Op0.isDef())
3013 if (!Op.isReg())
3090 if (!Op.isReg()) {
[all...]
H A DHexagonBlockRanges.cpp321 if (!Op.isReg() || !Op.isUse() || Op.isUndef()) in computeInitialLiveRanges()
337 if (!Op.isReg() || !Op.isDef() || Op.isUndef()) in computeInitialLiveRanges()
H A DHexagonConstPropagation.cpp703 if (!MO.isReg() || !MO.isDef()) in visitNonBranch()
1930 if (MI.getNumOperands() == 0 || !MI.getOperand(0).isReg()) in evaluate()
2603 bool Reg1 = Src1.isReg(), Reg2 = Src2.isReg(); in evaluateHexCompare2()
2706 if (ValOp.isReg()) { in evaluateHexCondMove()
2803 if (!MO.isReg() || !MO.isUse() || MO.isImplicit()) in rewriteHexConstDefs()
2824 if (!MO.isReg() || !MO.isUse() || MO.isImplicit()) in rewriteHexConstDefs()
2842 if (!MO.isReg() || !MO.isDef()) in rewriteHexConstDefs()
3105 if (MO.isReg() && MO.isUse()) in rewriteHexConstUses()
H A DHexagonBitTracker.cpp169 if (MO.isReg()) in RegisterRefs()
196 if (!MO.isReg() || !MO.isDef())
271 if (!Op.isReg())
1043 if (!Op.isReg() || !Op.isDef())
1190 assert(MD.isReg() && MD.isDef());
H A DRDFDeadCode.cpp67 if (Op.isReg() && MRI.isReserved(Op.getReg())) in isLiveInstr()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
H A DSILoadStoreOptimizer.cpp166 if (!AddrOp->isReg()) in hasMergeableAddress()
584 if (Op.isReg()) { in addDefsUsesToList()
616 if (Use.isReg() && in addToListsIfDependent()
1660 if (!Op.isReg()) in extractConstOffset()
1683 if (!Base.isReg()) in processBaseWithConstOffset()
1693 if (!BaseLo.isReg() || !BaseHi.isReg()) in processBaseWithConstOffset()
H A DSIInsertWaitcnts.cpp469 if (!Op.isReg() || !TRI->isInAllocatableClass(Op.getReg()) || in getRegInterval()
577 if (Op.isReg() && !Op.isDef() && TRI->isVGPR(MRIA, Op.getReg())) { in updateByEvent()
624 if (DefMO.isReg() && DefMO.isDef() && in updateByEvent()
633 if (MO.isReg() && !MO.isDef() && TRI->isVGPR(MRIA, MO.getReg())) { in updateByEvent()
1397 Inst.getOperand(0).isReg() && in insertWaitcntInBlock()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
H A DARMLoadStoreOptimizer.cpp205 if (!MO.isReg()) in definesCPSR()
879 if (!MO.isReg() || !MO.isDef() || MO.isDead()) in MergeOpsUpdate()
944 if (!MO.isReg() || MO.getReg() != ImpDefReg) in MergeOpsUpdate()
962 if (!MO.isReg() || !MO.isKill()) in MergeOpsUpdate()
1593 if (!MI.getOperand(1).isReg())
1617 if (MI.getOperand(0).isReg() && MI.getOperand(0).isUndef())
2129 if (!MO.isReg())
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
H A DMachineRegisterInfo.cpp238 if (!MO->isReg()) { in verifyUseList()
351 if (Src->isReg()) { in moveOperands()
H A DRegisterCoalescer.cpp1223 if (!Op.isReg() || !Op.isDef() || Op.getReg() != Reg) in definesFullReg()
1346 if (MO.isReg()) { in reMaterializeTrivialDef()
1366 if (MO.isReg() && MO.isDef()) { in reMaterializeTrivialDef()
1584 if (MO.isReg() && MO.isUse()) in eliminateUndefCopy()
1647 if (MO.isReg() && MO.isDef() && MO.getReg() == DstReg) in eliminateUndefCopy()
2436 if (!MO.isReg() || MO.getReg() != Reg || !MO.isDef()) in computeWriteLanes()
2870 if (!MO.isReg() || MO.isDef() || MO.getReg() != Reg) in usesLanes()
2986 if (MO.isReg() && MO.isDef() && MO.getReg() == Reg) { in pruneValues()
3485 if (MI.isDebugValue() && MI.getOperand(0).isReg() && in buildVRegToDbgValueMap()
H A DInlineSpiller.cpp558 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) in reMaterializeFor()
623 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) { in reMaterializeFor()
844 if (!MO->isReg()) in foldMemoryOperand()
882 if (!MO.isReg() || !MO.isImplicit()) in foldMemoryOperand()
1520 if (MO.isReg() && MO.isImplicit() && MO.isDef() && !MO.isDead()) in hoistAllSpills()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
H A DAArch64A57FPLoadBalancing.cpp554 if (U.isReg() && U.isUse() && Substs.find(U.getReg()) != Substs.end()) { in colorChain()
687 if (MO.isReg()) { in maybeKillChain()
H A DAArch64CondBrTuning.cpp94 if (MO.isReg() && MO.isDead() && MO.getReg() == AArch64::NZCV) in convertToFlagSetting()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/AsmParser/
H A DAVRAsmParser.cpp179 bool isReg() const { return Kind == k_Register; } in isReg() function in __anon24570::AVROperand
717 if (Op.isReg()) { in validateTargetOperandClass()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/AsmParser/
H A DMSP430AsmParser.cpp157 bool isReg() const { return Kind == k_Reg; } in isReg() function in __anon24692::MSP430Operand
567 if (!Op.isReg()) in validateTargetOperandClass()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
H A DMips16InstrInfo.cpp356 if (MO.isReg() && MO.getReg() != 0 && !MO.isDef() && in loadImmediate()
372 if (MO.isReg() && MO.isDef()) { in loadImmediate()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp242 bool isReg() const override {
362 return isReg() || isImm(); in isRegOrImm()
1986 assert(R->isReg()); in ParseRegister()
2417 assert(R->isReg()); in parseReg()
2802 } else if (MO.isReg()) { in usesConstantBus()
2846 if (MO.isReg()) { in validateConstantBusLimitations()
2908 assert(Dst.isReg()); in validateEarlyClobberLimitations()
2916 if (Src.isReg()) { in validateEarlyClobberLimitations()
3080 if (!Src0.isReg()) in validateMovrels()
3273 if (Src.isReg() in validateLdsDirect()
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp1274 bool isReg() const override { return Kind == k_Register; }
3975 if (!PrevOp->isReg()) in tryParseShiftRegister()
6423 if (!Op3.isReg() || !Op4.isReg()) in tryConvertingToTwoOperandForm()
6438 (Op5.isReg() && Op5.getReg() == ARM::PC); in tryConvertingToTwoOperandForm()
6441 (Op5.isReg() && Op5.getReg() == ARM::SP)) && in tryConvertingToTwoOperandForm()
6466 if (!Transform && Op5.isReg() && Op3Reg == Op5.getReg() && in tryConvertingToTwoOperandForm()
6481 LastOp->isReg()) in tryConvertingToTwoOperandForm()
6519 static_cast<ARMOperand &>(*Operands[3]).isReg() && in shouldOmitCCOutOperand()
6520 static_cast<ARMOperand &>(*Operands[4]).isReg() in shouldOmitCCOutOperand()
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
H A DCSEInfo.cpp340 if (MO.isReg()) { in addNodeIDMachineOperand()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/Disassembler/
H A DLanaiDisassembler.cpp112 if (Instr.getOperand(2).isReg()) { in PostOperandDecodeAdjust()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/MCTargetDesc/
H A DSystemZInstPrinter.cpp44 if (MO.isReg()) { in printOperand()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.h129 bool isIndirect() { return Target != nullptr && Target->isReg(); } in isIndirect()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/MCTargetDesc/
H A DWebAssemblyInstPrinter.cpp212 if (Op.isReg()) {

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