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Searched refs:isReg (Results 126 - 150 of 325) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/AsmPrinter/
H A DDebugHandlerBase.cpp35 if (!Instruction.getOperand(0).isReg()) in extractFromMachineInstruction()
218 return MI->getOperand(0).isReg() && MI->getOperand(0).getReg(); in beginFunction()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
H A DTargetSchedule.cpp161 if (MO.isReg() && MO.isDef()) in findDefIdx()
177 if (MO.isReg() && MO.readsReg() && !MO.isDef()) in findUseIdx()
H A DScheduleDAGInstrs.cpp206 if (!MO.isReg() || MO.isDef()) continue; in addSchedBarrierDeps()
414 if (OtherMO.isReg() && OtherMO.isDef() && OtherMO.getReg() == Reg) in addVRegDefDeps()
844 if (!MO.isReg() || !MO.isDef()) in buildSchedGraph()
861 if (!MO.isReg() || !MO.isUse()) in buildSchedGraph()
1094 if (!MO.isReg() || !MO.readsReg()) in toggleKills()
1124 if (MO.isReg()) { in fixupKills()
H A DLiveVariables.cpp216 if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0) in FindLastPartialDef()
521 if (!MO.isReg() || MO.getReg() == 0) in runOnInstr()
692 if (MO.isReg() && MO.isKill()) { in removeVirtualRegistersKilled()
785 if (I->isReg() && Register::isVirtualRegister(I->getReg())) { in addNewBlock()
H A DMachineCombiner.cpp148 if (MO.isReg() && Register::isVirtualRegister(MO.getReg())) in getOperandDef()
179 if (!(MO.isReg() && Register::isVirtualRegister(MO.getReg()))) in getDepth()
234 if (!(MO.isReg() && Register::isVirtualRegister(MO.getReg()))) in getLatency()
H A DLiveRegUnits.cpp58 if (!MOP.isReg() || !MOP.readsReg()) in stepBackward()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/MCParser/
H A DMCTargetAsmParser.h455 assert(Op1.isReg() && Op2.isReg() && "Operands not all regs"); in regsEqual()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
H A DR600EmitClauseMarkers.cpp79 if (MO.isReg() && MO.getReg() == R600::ALU_LITERAL_X) in OccupiedDwords()
203 if (!MOI->isReg() || !MOI->isDef() || in canClauseLocalKillFitInClause()
H A DSIWholeQuadMode.cpp275 if (!Use.isReg() || !Use.isUse()) in markInstructionUses()
362 if (Inactive.isReg()) { in scanInstructions()
392 if (!MO.isReg()) in scanInstructions()
546 if (Op.isReg()) { in requiresCorrectState()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCTargetDesc.cpp88 assert(MI.getOperand(OI).isReg() && "expected register"); in getARMStoreDeprecationInfo()
106 assert(MI.getOperand(OI).isReg() && "expected register"); in getARMLoadDeprecationInfo()
H A DARMInstPrinter.cpp314 if (Op.isReg()) { in printOperand()
476 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
549 if (!MO1.isReg()) { // For label symbolic references.
656 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
680 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
1093 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
1115 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
1182 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
1235 if (!MO1.isReg()) { // For label symbolic references.
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/
H A DBPFMISimplifyPatchable.cpp248 if (!MI.getOperand(0).isReg() || !MI.getOperand(1).isReg()) in removeLD()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
H A DMipsOptimizePICCall.cpp130 if (!MO.isReg() || !MO.isUse() || !Register::isVirtualRegister(MO.getReg())) in getCallTargetRegOpnd()
172 if (MO.isReg() && MO.getReg() == Reg) { in eraseGPOpnd()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
H A DPPCPreEmitPeephole.cpp91 assert(BBI->getOperand(0).isReg() && in removeRedundantLIs()
126 assert(AfterBBI->getOperand(0).isReg() && in removeRedundantLIs()
H A DPPCInstrInfo.cpp162 if (!MO.isReg() || !MO.isDef() || MO.isImplicit()) in getInstrLatency()
1348 if (UseMI.getOperand(UseIdx).isReg() && in FoldImmediate()
1571 if (MO.isReg()) {
2138 assert(MI.getOperand(2).isReg() &&
2150 assert(MI.getOperand(2).isReg() && MI.getOperand(1).isReg() &&
2158 assert(MI.getOperand(2).isReg() && MI.getOperand(1).isReg() &&
2256 assert(MI.getOperand(OpNo).isReg() && "Operand must be a REG");
2336 if (!MI.getOperand(i).isReg())
[all...]
H A DPPCAsmPrinter.cpp255 if (!MI->getOperand(OpNo).isReg() || in PrintAsmOperand()
257 !MI->getOperand(OpNo+1).isReg()) in PrintAsmOperand()
268 if(!MI->getOperand(OpNo).isReg()) in PrintAsmOperand()
319 assert(MI->getOperand(OpNo).isReg()); in PrintAsmMemoryOperand()
325 assert(MI->getOperand(OpNo).isReg()); in PrintAsmMemoryOperand()
486 assert(MI->getOperand(0).isReg() && in EmitTlsCall()
490 assert(MI->getOperand(1).isReg() && in EmitTlsCall()
549 if (MO.isReg()) { in EmitInstruction()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
H A DX86RegisterBankInfo.cpp118 if (!MO.isReg()) in getInstrPartialMappingIdxs()
132 if (!MI.getOperand(Idx).isReg()) in getInstrValueMapping()
H A DX86SpeculativeLoadHardening.cpp548 if (!Op.isReg() || Op.getReg() != PS->InitialReg) in runOnMachineFunction()
1676 return Op.isReg() && LoadDepRegs.test(Op.getReg()); in tracePredStateThroughBlocksAndHarden()
1679 if (Def.isReg()) in tracePredStateThroughBlocksAndHarden()
1744 MI.getDesc().getNumDefs() == 1 && MI.getOperand(0).isReg() && in tracePredStateThroughBlocksAndHarden()
1762 if (Def.isReg()) in tracePredStateThroughBlocksAndHarden()
1987 assert(BaseMO.isReg() && in hardenLoadAddr()
2187 if ((BaseMO.isReg() && BaseMO.getReg() == DefReg) || in sinkPostLoadHardenedInst()
2188 (IndexMO.isReg() && IndexMO.getReg() == DefReg)) in sinkPostLoadHardenedInst()
2611 if (!MI.getOperand(0).isReg()) in hardenIndirectCallOrJumpInstr()
H A DX86MCInstLower.cpp294 assert(Inst.getOperand(0).isReg() && in SimplifyShortImmForm()
296 ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() && in SimplifyShortImmForm()
349 bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg(); in SimplifyShortMoveForm()
354 Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() && in SimplifyShortMoveForm()
355 Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() && in SimplifyShortMoveForm()
357 Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() && in SimplifyShortMoveForm()
358 Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() && in SimplifyShortMoveForm()
1467 assert(Op->isReg() && "Only support arguments in registers"); in LowerPATCHABLE_EVENT_CALL()
1565 assert(Op->isReg() in LowerPATCHABLE_TYPED_EVENT_CALL()
[all...]
H A DX86CmovConversion.cpp439 if (!MO.isReg() || !MO.isUse()) in checkForProfitableCmovCandidates()
459 if (!MO.isReg() || !MO.isDef()) in checkForProfitableCmovCandidates()
784 if (!MOp.isReg()) in convertCmovInstsToBranches()
H A DX86FloatingPoint.cpp316 assert(MO.isReg() && "Expected an FP register!"); in getFPReg()
451 if (MO.isReg() && MO.isDead()) in processBasicBlock()
984 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6) in handleCall()
1025 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6) in handleReturn()
1539 if (!MO.isReg()) in handleSpecialFP()
1608 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6) in handleSpecialFP()
1637 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6) in handleSpecialFP()
1703 if (!MO.isReg()) in setKillFlags()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
H A DAArch64AsmPrinter.cpp622 assert(MO.isReg() && "Should only get here with a register!"); in printAsmRegInClass()
649 if (MO.isReg()) in PrintAsmOperand()
664 if (MO.isReg()) { in PrintAsmOperand()
697 if (MO.isReg()) { in PrintAsmOperand()
732 assert(MO.isReg() && "unexpected inline asm memory operand"); in PrintAsmMemoryOperand()
747 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm()); in PrintDebugValueComment()
H A DAArch64InstructionSelector.cpp443 if (!MO.isReg()) { in unsupportedBinOp()
1485 I.getOperand(0).isReg() ? MRI.getType(I.getOperand(0).getReg()) : LLT{}; in select()
2975 assert(LaneIdxOp.isReg() && "Lane index operand was not a register?"); in selectExtractElt()
3244 assert(LHS.isReg() && RHS.isReg() && "Expected LHS and RHS to be registers!"); in emitADD()
3268 assert(LHS.isReg() && RHS.isReg() && "Expected LHS and RHS to be registers!"); in emitCMN()
3322 assert(LHS.isReg() && RHS.isReg() && "Expected LHS and RHS to be registers!"); in emitIntegerCompare()
3574 assert(LHS.isReg() in tryFoldIntegerCompare()
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
H A DRegisterBankInfo.cpp186 if (!MO.isReg()) in getInstrMappingImpl()
235 if (!MO.isReg()) in getInstrMappingImpl()
448 if (!MO.isReg()) { in applyDefaultMapping()
611 if (!MO.isReg()) { in verify()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
H A DSystemZElimCompare.cpp134 if (MI.getNumOperands() > 0 && MI.getOperand(0).isReg() && in resultTests()
149 if (MO.isReg()) { in getRegReferences()
632 Compare.getOperand(1).isReg() ? Compare.getOperand(1).getReg() : Register(); in fuseCompareOperations()

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