Home
last modified time | relevance | path

Searched refs:instr (Results 501 - 525 of 1218) sorted by relevance

1...<<21222324252627282930>>...49

/third_party/node/deps/v8/src/compiler/backend/arm64/
H A Dcode-generator-arm64.cc30 Arm64OperandConverter(CodeGenerator* gen, Instruction* instr) in Arm64OperandConverter() argument
31 : InstructionOperandConverter(gen, instr) {} in Arm64OperandConverter()
395 WasmOutOfLineTrap(CodeGenerator* gen, Instruction* instr) in WasmOutOfLineTrap() argument
396 : OutOfLineCode(gen), gen_(gen), instr_(instr) {} in WasmOutOfLineTrap()
440 WasmProtectedInstructionTrap(CodeGenerator* gen, int pc, Instruction* instr) in WasmProtectedInstructionTrap() argument
441 : WasmOutOfLineTrap(gen, instr), pc_(pc) {} in WasmProtectedInstructionTrap()
454 InstructionCode opcode, Instruction* instr, int pc) { in EmitOOLTrapIfNeeded()
457 zone->New<WasmProtectedInstructionTrap>(codegen, pc, instr); in EmitOOLTrapIfNeeded()
462 InstructionCode opcode, Instruction* instr, int pc) { in EmitOOLTrapIfNeeded()
469 void EmitFpOrNeonUnop(TurboAssembler* tasm, Fn fn, Instruction* instr, in EmitFpOrNeonUnop() argument
453 EmitOOLTrapIfNeeded(Zone* zone, CodeGenerator* codegen, InstructionCode opcode, Instruction* instr, int pc) EmitOOLTrapIfNeeded() argument
461 EmitOOLTrapIfNeeded(Zone* zone, CodeGenerator* codegen, InstructionCode opcode, Instruction* instr, int pc) EmitOOLTrapIfNeeded() argument
630 AssembleTailCallBeforeGap(Instruction* instr, int first_unused_slot_offset) AssembleTailCallBeforeGap() argument
636 AssembleTailCallAfterGap(Instruction* instr, int first_unused_slot_offset) AssembleTailCallAfterGap() argument
681 AssembleArchInstruction( Instruction* instr) AssembleArchInstruction() argument
1076 EmitFpOrNeonUnop(tasm(), &TurboAssembler::Frintm, instr, i, kFormatS, AssembleArchInstruction() local
1080 EmitFpOrNeonUnop(tasm(), &TurboAssembler::Frintm, instr, i, kFormatD, AssembleArchInstruction() local
1084 EmitFpOrNeonUnop(tasm(), &TurboAssembler::Frintp, instr, i, kFormatS, AssembleArchInstruction() local
1088 EmitFpOrNeonUnop(tasm(), &TurboAssembler::Frintp, instr, i, kFormatD, AssembleArchInstruction() local
1092 EmitFpOrNeonUnop(tasm(), &TurboAssembler::Frinta, instr, i, kFormatD, AssembleArchInstruction() local
1096 EmitFpOrNeonUnop(tasm(), &TurboAssembler::Frintz, instr, i, kFormatS, AssembleArchInstruction() local
1100 EmitFpOrNeonUnop(tasm(), &TurboAssembler::Frintz, instr, i, kFormatD, AssembleArchInstruction() local
1104 EmitFpOrNeonUnop(tasm(), &TurboAssembler::Frintn, instr, i, kFormatS, AssembleArchInstruction() local
1108 EmitFpOrNeonUnop(tasm(), &TurboAssembler::Frintn, instr, i, kFormatD, AssembleArchInstruction() local
1842 EmitOOLTrapIfNeeded(zone(), this, opcode, instr, __ pc_offset()); AssembleArchInstruction() local
1846 EmitOOLTrapIfNeeded(zone(), this, opcode, instr, __ pc_offset()); AssembleArchInstruction() local
1850 EmitOOLTrapIfNeeded(zone(), this, opcode, instr, __ pc_offset()); AssembleArchInstruction() local
1854 EmitOOLTrapIfNeeded(zone(), this, opcode, instr, __ pc_offset()); AssembleArchInstruction() local
1858 EmitOOLTrapIfNeeded(zone(), this, opcode, instr, __ pc_offset()); AssembleArchInstruction() local
1862 EmitOOLTrapIfNeeded(zone(), this, opcode, instr, __ pc_offset()); AssembleArchInstruction() local
1866 EmitOOLTrapIfNeeded(zone(), this, opcode, instr, __ pc_offset()); AssembleArchInstruction() local
1870 EmitOOLTrapIfNeeded(zone(), this, opcode, instr, __ pc_offset()); AssembleArchInstruction() local
1874 EmitOOLTrapIfNeeded(zone(), this, opcode, instr, __ pc_offset()); AssembleArchInstruction() local
1878 EmitOOLTrapIfNeeded(zone(), this, opcode, instr, __ pc_offset()); AssembleArchInstruction() local
1882 EmitOOLTrapIfNeeded(zone(), this, opcode, instr, __ pc_offset()); AssembleArchInstruction() local
1886 EmitOOLTrapIfNeeded(zone(), this, opcode, instr, __ pc_offset()); AssembleArchInstruction() local
1914 EmitOOLTrapIfNeeded(zone(), this, opcode, instr, __ pc_offset()); AssembleArchInstruction() local
1931 EmitOOLTrapIfNeeded(zone(), this, opcode, instr, __ pc_offset()); AssembleArchInstruction() local
1935 EmitOOLTrapIfNeeded(zone(), this, opcode, instr, __ pc_offset()); AssembleArchInstruction() local
1939 EmitOOLTrapIfNeeded(zone(), this, opcode, instr, __ pc_offset()); AssembleArchInstruction() local
1943 EmitOOLTrapIfNeeded(zone(), this, opcode, instr, __ pc_offset()); AssembleArchInstruction() local
1947 EmitOOLTrapIfNeeded(zone(), this, opcode, instr, __ pc_offset()); AssembleArchInstruction() local
1951 EmitOOLTrapIfNeeded(zone(), this, opcode, instr, __ pc_offset()); AssembleArchInstruction() local
[all...]
/third_party/vixl/src/aarch64/
H A Dsimulator-aarch64.h1363 BType GetBTypeFromInstruction(const Instruction* instr) const;
1414 const Instruction* instr) VIXL_OVERRIDE;
1416 #define DECLARE(A) virtual void Visit##A(const Instruction* instr);
1420 VIXL_NO_RETURN virtual void Visit##A(const Instruction* instr);
1424 void Simulate_PdT_PgZ_ZnT_ZmT(const Instruction* instr);
1425 void Simulate_PdT_Xn_Xm(const Instruction* instr);
1426 void Simulate_ZdB_Zn1B_Zn2B_imm(const Instruction* instr);
1427 void Simulate_ZdB_ZnB_ZmB(const Instruction* instr);
1428 void Simulate_ZdD_ZnD_ZmD_imm(const Instruction* instr);
1429 void Simulate_ZdH_PgM_ZnS(const Instruction* instr);
[all...]
/third_party/mesa3d/src/intel/compiler/
H A Dbrw_nir.c77 b->cursor = nir_before_instr(&intr->instr); in remap_tess_levels()
81 nir_instr_remove(&intr->instr); in remap_tess_levels()
113 nir_foreach_instr_safe(instr, block) { in remap_patch_urb_offsets()
114 if (instr->type != nir_instr_type_intrinsic) in remap_patch_urb_offsets()
117 nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr); in remap_patch_urb_offsets()
138 b->cursor = nir_before_instr(&intrin->instr); in remap_patch_urb_offsets()
153 nir_instr_rewrite_src(&intrin->instr, offset, in remap_patch_urb_offsets()
206 nir_foreach_instr_safe(instr, block) { in brw_nir_lower_vs_inputs()
207 if (instr->type != nir_instr_type_intrinsic) in brw_nir_lower_vs_inputs()
210 nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr); in brw_nir_lower_vs_inputs()
392 lower_barycentric_at_offset(nir_builder *b, nir_instr *instr, void *data) lower_barycentric_at_offset() argument
646 lower_bit_size_callback(const nir_instr *instr, UNUSED void *data) lower_bit_size_callback() argument
779 lower_xehp_tg4_offset_filter(const nir_instr *instr, UNUSED const void *data) lower_xehp_tg4_offset_filter() argument
[all...]
/third_party/node/deps/v8/src/compiler/backend/mips/
H A Dinstruction-scheduler-mips.cc15 const Instruction* instr) const { in GetTargetInstructionFlags()
16 switch (instr->arch_opcode()) { in GetTargetInstructionFlags()
1385 int InstructionScheduler::GetInstructionLatency(const Instruction* instr) { in GetInstructionLatency() argument
1388 switch (instr->arch_opcode()) { in GetInstructionLatency()
1411 static_cast<SaveFPRegsMode>(MiscField::decode(instr->opcode())); in GetInstructionLatency()
1416 static_cast<SaveFPRegsMode>(MiscField::decode(instr->opcode())); in GetInstructionLatency()
1426 return AssembleArchBinarySearchSwitchLatency((instr->InputCount() - 2) / in GetInstructionLatency()
1471 return AdduLatency(instr->InputAt(1)->IsRegister()); in GetInstructionLatency()
1473 return AndLatency(instr->InputAt(1)->IsRegister()); in GetInstructionLatency()
1475 return OrLatency(instr in GetInstructionLatency()
[all...]
/third_party/node/deps/v8/src/codegen/ppc/
H A Dassembler-ppc-inl.h316 Instr instr = instr_at(pc); in IsConstantPoolLoadStart() local
317 uint32_t opcode = instr & kOpcodeMask; in IsConstantPoolLoadStart()
318 if (GetRA(instr) != kConstantPoolRegister) return false; in IsConstantPoolLoadStart()
335 Instr instr = instr_at(pc); in IsConstantPoolLoadEnd() local
336 uint32_t opcode = instr & kOpcodeMask; in IsConstantPoolLoadEnd()
339 if (GetRA(instr) != kConstantPoolRegister) { in IsConstantPoolLoadEnd()
340 instr = instr_at(pc - kInstrSize); in IsConstantPoolLoadEnd()
341 opcode = instr & kOpcodeMask; in IsConstantPoolLoadEnd()
342 if ((opcode != ADDIS) || GetRA(instr) != kConstantPoolRegister) { in IsConstantPoolLoadEnd()
401 Instr instr in PatchConstantPoolAccessInstruction() local
[all...]
/kernel/linux/linux-5.10/arch/microblaze/kernel/
H A Dunwind.c59 * @instr : Microblaze instruction
63 static inline long get_frame_size(unsigned long instr) in get_frame_size() argument
65 return abs((s16)(instr & 0xFFFF)); in get_frame_size()
87 unsigned long instr; in find_frame_creation() local
93 instr = *pc; in find_frame_creation()
96 if ((instr & 0xFFFF0000) != 0x30210000) in find_frame_creation()
99 frame_size = get_frame_size(instr); in find_frame_creation()
/kernel/linux/linux-6.6/arch/microblaze/kernel/
H A Dunwind.c59 * @instr : Microblaze instruction
63 static inline long get_frame_size(unsigned long instr) in get_frame_size() argument
65 return abs((s16)(instr & 0xFFFF)); in get_frame_size()
87 unsigned long instr; in find_frame_creation() local
93 instr = *pc; in find_frame_creation()
96 if ((instr & 0xFFFF0000) != 0x30210000) in find_frame_creation()
99 frame_size = get_frame_size(instr); in find_frame_creation()
/kernel/linux/linux-5.10/drivers/media/pci/tw68/
H A Dtw68-risc.c187 } instr[8] = {
197 if (!(risc & 0x80000000) || !instr[p].name) {
202 risc, instr[p].name, (risc >> 27) & 1);
203 if (instr[p].has_data_type)
205 if (instr[p].has_byte_info)
208 if (instr[p].has_addr)
/kernel/linux/linux-6.6/drivers/media/pci/tw68/
H A Dtw68-risc.c188 } instr[8] = {
198 if (!(risc & 0x80000000) || !instr[p].name) {
203 risc, instr[p].name, (risc >> 27) & 1);
204 if (instr[p].has_data_type)
206 if (instr[p].has_byte_info)
209 if (instr[p].has_addr)
/third_party/mesa3d/src/compiler/nir/
H A Dnir_opt_dead_write_vars.c92 nir_instr_remove(&entry->intrin->instr); in update_unused_writes()
119 nir_foreach_instr_safe(instr, block) { in remove_dead_write_vars_local()
120 if (instr->type == nir_instr_type_call) { in remove_dead_write_vars_local()
130 if (instr->type != nir_instr_type_intrinsic) in remove_dead_write_vars_local()
133 nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr); in remove_dead_write_vars_local()
228 nir_instr_remove(instr); in remove_dead_write_vars_local()
H A Dnir_opt_offsets.c97 b->cursor = nir_before_instr(&alu->instr); in try_extract_const_addition()
130 b->cursor = nir_before_instr(&intrin->instr); in try_fold_load_store()
134 b->cursor = nir_before_instr(&intrin->instr); in try_fold_load_store()
141 nir_instr_rewrite_src(&intrin->instr, &intrin->src[offset_src_idx], nir_src_for_ssa(replace_src)); in try_fold_load_store()
170 b->cursor = nir_before_instr(&intrin->instr); in try_fold_shared2()
171 nir_instr_rewrite_src(&intrin->instr, off_src, nir_src_for_ssa(nir_imm_zero(b, 1, 32))); in try_fold_shared2()
180 process_instr(nir_builder *b, nir_instr *instr, void *s) in process_instr() argument
182 if (instr->type != nir_instr_type_intrinsic) in process_instr()
186 nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr); in process_instr()
H A Dnir_lower_fp16_conv.c48 lower_fp16_casts_filter(const nir_instr *instr, const void *data) in lower_fp16_casts_filter() argument
50 if (instr->type == nir_instr_type_alu) { in lower_fp16_casts_filter()
51 nir_alu_instr *alu = nir_instr_as_alu(instr); in lower_fp16_casts_filter()
60 } else if (instr->type == nir_instr_type_intrinsic) { in lower_fp16_casts_filter()
61 nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr); in lower_fp16_casts_filter()
192 lower_fp16_cast_impl(nir_builder *b, nir_instr *instr, void *data) in lower_fp16_cast_impl() argument
198 if (instr->type == nir_instr_type_alu) { in lower_fp16_cast_impl()
199 nir_alu_instr *alu = nir_instr_as_alu(instr); in lower_fp16_cast_impl()
213 nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr); in lower_fp16_cast_impl()
H A Dnir_lower_int_to_float.c52 b->cursor = nir_before_instr(&alu->instr); in lower_alu_instr()
145 nir_instr_remove(&alu->instr); in lower_alu_instr()
168 nir_foreach_instr_safe(instr, block) { in nir_lower_int_to_float_impl()
169 switch (instr->type) { in nir_lower_int_to_float_impl()
171 progress |= lower_alu_instr(&b, nir_instr_as_alu(instr)); in nir_lower_int_to_float_impl()
175 nir_load_const_instr *load = nir_instr_as_load_const(instr); in nir_lower_int_to_float_impl()
190 nir_foreach_ssa_def(instr, assert_ssa_def_is_not_int, (void *)int_types); in nir_lower_int_to_float_impl()
H A Dnir_lower_memory_model.c149 visit_instr(nir_instr *instr, uint32_t *cur_modes, unsigned vis_avail_sem) in visit_instr() argument
151 if (instr->type != nir_instr_type_intrinsic) in visit_instr()
153 nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr); in visit_instr()
201 nir_foreach_instr(instr, block) in lower_make_visible()
202 progress |= visit_instr(instr, cur_modes, NIR_MEMORY_MAKE_VISIBLE); in lower_make_visible()
240 nir_foreach_instr_reverse(instr, block) in lower_make_available()
241 progress |= visit_instr(instr, cur_modes, NIR_MEMORY_MAKE_AVAILABLE); in lower_make_available()
/third_party/mesa3d/src/mesa/state_tracker/
H A Dst_nir_lower_tex_src_plane.c109 nir_foreach_instr(instr, block) { in lower_tex_src_plane_block()
110 if (instr->type != nir_instr_type_tex) in lower_tex_src_plane_block()
113 nir_tex_instr *tex = nir_instr_as_tex(instr); in lower_tex_src_plane_block()
142 b->cursor = nir_before_instr(&tex->instr); in lower_tex_src_plane_block()
150 nir_instr_rewrite_src(&tex->instr, in lower_tex_src_plane_block()
153 nir_instr_rewrite_src(&tex->instr, in lower_tex_src_plane_block()
/third_party/mesa3d/src/gallium/drivers/etnaviv/tests/
H A Dlower_ubo_tests.cpp76 nir_foreach_instr(instr, block) { in intrinsic()
77 if (instr->type != nir_instr_type_intrinsic) in intrinsic()
80 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr); in intrinsic()
94 nir_foreach_instr(instr, block) { in count_intrinsic()
95 if (instr->type != nir_instr_type_intrinsic) in count_intrinsic()
98 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr); in count_intrinsic()
/kernel/linux/linux-6.6/arch/arm/include/asm/
H A Dassembler.h257 #define ALT_SMP(instr...) \
258 9998: instr
262 * ALT_SMP( W(instr) ... )
264 #define ALT_UP(instr...) \
268 9997: instr ;\
283 #define ALT_SMP(instr...)
284 #define ALT_UP(instr...) instr
469 .macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER() variable
472 \instr\()
485 .macro usracc, instr, reg, ptr, inc, cond, rept, abort global() variable
[all...]
/third_party/mesa3d/src/freedreno/ir3/
H A Dir3_nir_lower_io_offsets.c191 nir_instr_remove(&intrinsic->instr); in scalarize_load()
215 b->cursor = nir_before_instr(&intrinsic->instr); in lower_offset_for_ssbo()
242 nir_ssa_dest_init(&new_intrinsic->instr, &new_intrinsic->dest, in lower_offset_for_ssbo()
263 nir_builder_instr_insert(b, &new_intrinsic->instr); in lower_offset_for_ssbo()
268 nir_instr_rewrite_src(&new_intrinsic->instr, target_src, in lower_offset_for_ssbo()
279 nir_instr_remove(&intrinsic->instr); in lower_offset_for_ssbo()
295 nir_foreach_instr_safe (instr, block) { in lower_io_offsets_block()
296 if (instr->type != nir_instr_type_intrinsic) in lower_io_offsets_block()
299 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr); in lower_io_offsets_block()
/third_party/mesa3d/src/intel/vulkan/
H A Danv_nir_lower_multiview.c154 is_load_view_index(const nir_instr *instr, const void *data) in is_load_view_index() argument
156 return instr->type == nir_instr_type_intrinsic && in is_load_view_index()
157 nir_instr_as_intrinsic(instr)->intrinsic == nir_intrinsic_load_view_index; in is_load_view_index()
162 nir_instr *instr, void *data) in replace_load_view_index_with_zero()
164 assert(is_load_view_index(instr, data)); in replace_load_view_index_with_zero()
221 nir_foreach_instr_safe(instr, block) { in anv_nir_lower_multiview()
222 if (instr->type != nir_instr_type_intrinsic) in anv_nir_lower_multiview()
225 nir_intrinsic_instr *load = nir_instr_as_intrinsic(instr); in anv_nir_lower_multiview()
243 nir_instr_remove(&load->instr); in anv_nir_lower_multiview()
161 replace_load_view_index_with_zero(struct nir_builder *b, nir_instr *instr, void *data) replace_load_view_index_with_zero() argument
H A Danv_nir_compute_push_layout.c50 nir_foreach_instr(instr, block) { in anv_nir_compute_push_layout()
51 if (instr->type != nir_instr_type_intrinsic) in anv_nir_compute_push_layout()
54 nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr); in anv_nir_compute_push_layout()
146 nir_foreach_instr_safe(instr, block) { in anv_nir_compute_push_layout()
147 if (instr->type != nir_instr_type_intrinsic) in anv_nir_compute_push_layout()
150 nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr); in anv_nir_compute_push_layout()
169 b->cursor = nir_before_instr(&intrin->instr); in anv_nir_compute_push_layout()
/kernel/linux/linux-5.10/arch/powerpc/kvm/
H A Dbook3s_hv_tm.c44 u32 instr = vcpu->arch.emul_inst; in kvmhv_p9_tm_emulation() local
60 switch (instr & PO_XOP_OPCODE_MASK) { in kvmhv_p9_tm_emulation()
98 if (instr & (1 << 11)) in kvmhv_p9_tm_emulation()
109 rs = (instr >> 21) & 0x1f; in kvmhv_p9_tm_emulation()
147 if (instr & (1 << 21)) { in kvmhv_p9_tm_emulation()
180 ra = (instr >> 16) & 0x1f; in kvmhv_p9_tm_emulation()
228 pr_warn_ratelimited("Unrecognized TM-related instruction %#x for emulation", instr); in kvmhv_p9_tm_emulation()
/kernel/linux/linux-5.10/arch/x86/um/
H A Dptrace_64.c193 unsigned short instr; in is_syscall() local
196 n = copy_from_user(&instr, (void __user *) addr, sizeof(instr)); in is_syscall()
204 n = access_process_vm(current, addr, &instr, sizeof(instr), in is_syscall()
206 if (n != sizeof(instr)) { in is_syscall()
213 return instr == 0x050f; in is_syscall()
/kernel/linux/linux-6.6/arch/x86/um/
H A Dptrace_64.c194 unsigned short instr; in is_syscall() local
197 n = copy_from_user(&instr, (void __user *) addr, sizeof(instr)); in is_syscall()
205 n = access_process_vm(current, addr, &instr, sizeof(instr), in is_syscall()
207 if (n != sizeof(instr)) { in is_syscall()
214 return instr == 0x050f; in is_syscall()
/third_party/mesa3d/src/amd/common/
H A Dac_nir_lower_global_access.c71 process_instr(nir_builder *b, nir_instr *instr, void *_) in process_instr() argument
73 if (instr->type != nir_instr_type_intrinsic) in process_instr()
76 nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr); in process_instr()
143 b->cursor = nir_before_instr(&intrin->instr); in process_instr()
155 nir_ssa_dest_init(&new_intrin->instr, &new_intrin->dest, intrin->dest.ssa.num_components, in process_instr()
174 nir_builder_instr_insert(b, &new_intrin->instr); in process_instr()
177 nir_instr_remove(&intrin->instr); in process_instr()
/third_party/node/deps/v8/src/compiler/backend/ia32/
H A Dinstruction-scheduler-ia32.cc17 const Instruction* instr) const { in GetTargetInstructionFlags()
18 switch (instr->arch_opcode()) { in GetTargetInstructionFlags()
337 return (instr->addressing_mode() == kMode_None) in GetTargetInstructionFlags()
343 return (instr->addressing_mode() == kMode_None) in GetTargetInstructionFlags()
370 return instr->HasOutput() ? kIsLoadOperation : kHasSideEffect; in GetTargetInstructionFlags()
405 int InstructionScheduler::GetInstructionLatency(const Instruction* instr) { in GetInstructionLatency() argument
408 switch (instr->arch_opcode()) { in GetInstructionLatency()

Completed in 19 milliseconds

1...<<21222324252627282930>>...49