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Searched refs:gpu (Results 51 - 75 of 169) sorted by relevance

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/kernel/linux/linux-6.6/drivers/gpu/drm/etnaviv/
H A Detnaviv_iommu.c89 static void etnaviv_iommuv1_restore(struct etnaviv_gpu *gpu, in etnaviv_iommuv1_restore() argument
95 if (gpu->mmu_context) in etnaviv_iommuv1_restore()
96 etnaviv_iommu_context_put(gpu->mmu_context); in etnaviv_iommuv1_restore()
97 gpu->mmu_context = etnaviv_iommu_context_get(context); in etnaviv_iommuv1_restore()
100 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_RA, context->global->memory_base); in etnaviv_iommuv1_restore()
101 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_FE, context->global->memory_base); in etnaviv_iommuv1_restore()
102 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_TX, context->global->memory_base); in etnaviv_iommuv1_restore()
103 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PEZ, context->global->memory_base); in etnaviv_iommuv1_restore()
104 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PE, context->global->memory_base); in etnaviv_iommuv1_restore()
109 gpu_write(gpu, VIVS_MC_MMU_FE_PAGE_TABL in etnaviv_iommuv1_restore()
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H A Detnaviv_dump.c82 struct etnaviv_gpu *gpu) in etnaviv_core_dump_registers()
92 read_addr = gpu_fix_power_address(gpu, read_addr); in etnaviv_core_dump_registers()
94 reg->value = cpu_to_le32(gpu_read(gpu, read_addr)); in etnaviv_core_dump_registers()
120 struct etnaviv_gpu *gpu = submit->gpu; in etnaviv_core_dump() local
142 mmu_size + gpu->buffer.size + submit->cmdbuf.size; in etnaviv_core_dump()
166 dev_warn(gpu->dev, "failed to allocate devcoredump file\n"); in etnaviv_core_dump()
176 etnaviv_core_dump_registers(&iter, gpu); in etnaviv_core_dump()
178 etnaviv_core_dump_mem(&iter, ETDUMP_BUF_RING, gpu->buffer.vaddr, in etnaviv_core_dump()
179 gpu in etnaviv_core_dump()
81 etnaviv_core_dump_registers(struct core_dump_iterator *iter, struct etnaviv_gpu *gpu) etnaviv_core_dump_registers() argument
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H A Detnaviv_drv.h39 struct etnaviv_gpu *gpu[ETNA_MAX_PIPES]; member
72 u16 etnaviv_buffer_init(struct etnaviv_gpu *gpu);
73 u16 etnaviv_buffer_config_mmuv2(struct etnaviv_gpu *gpu, u32 mtlb_addr, u32 safe_addr);
74 u16 etnaviv_buffer_config_pta(struct etnaviv_gpu *gpu, unsigned short id);
75 void etnaviv_buffer_end(struct etnaviv_gpu *gpu);
76 void etnaviv_sync_point_queue(struct etnaviv_gpu *gpu, unsigned int event);
77 void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, u32 exec_state,
81 bool etnaviv_cmd_validate_one(struct etnaviv_gpu *gpu,
H A Detnaviv_cmd_parser.c16 struct etnaviv_gpu *gpu; member
93 dev_warn_once(state->gpu->dev, in etnaviv_warn_if_non_sensitive()
123 dev_warn_ratelimited(state->gpu->dev, in etnaviv_validate_load_state()
147 bool etnaviv_cmd_validate_one(struct etnaviv_gpu *gpu, u32 *stream, in etnaviv_cmd_validate_one() argument
156 state.gpu = gpu; in etnaviv_cmd_validate_one()
189 dev_err(gpu->dev, "%s: op %u not permitted at offset %tu\n", in etnaviv_cmd_validate_one()
200 dev_err(gpu->dev, "%s: commands overflow end of buffer: %tu > %u\n", in etnaviv_cmd_validate_one()
H A Detnaviv_perfmon.h26 int etnaviv_pm_query_dom(struct etnaviv_gpu *gpu,
29 int etnaviv_pm_query_sig(struct etnaviv_gpu *gpu,
35 void etnaviv_perfmon_process(struct etnaviv_gpu *gpu,
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/adreno/
H A Da6xx_gpu.h61 static inline bool a6xx_has_gbif(struct adreno_gpu *gpu) in a6xx_has_gbif() argument
63 if(adreno_is_a630(gpu)) in a6xx_has_gbif()
72 int a6xx_gmu_resume(struct a6xx_gpu *gpu);
73 int a6xx_gmu_stop(struct a6xx_gpu *gpu);
85 void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp);
86 unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu);
88 void a6xx_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
91 struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu);
H A Dadreno_device.c263 /* identify gpu: */ in adreno_info()
280 struct msm_gpu *gpu = NULL; in adreno_load_gpu() local
285 gpu = dev_to_gpu(&pdev->dev); in adreno_load_gpu()
287 if (!gpu) { in adreno_load_gpu()
292 adreno_gpu = to_adreno_gpu(gpu); in adreno_load_gpu()
306 * booting the gpu, go ahead and enable runpm: in adreno_load_gpu()
318 ret = msm_gpu_hw_init(gpu); in adreno_load_gpu()
322 DRM_DEV_ERROR(dev->dev, "gpu hw init failed: %d\n", ret); in adreno_load_gpu()
327 if (gpu->funcs->debugfs_init) { in adreno_load_gpu()
328 gpu in adreno_load_gpu()
393 struct msm_gpu *gpu; adreno_bind() local
429 struct msm_gpu *gpu = dev_to_gpu(dev); adreno_unbind() local
494 struct msm_gpu *gpu = dev_to_gpu(dev); adreno_resume() local
501 struct msm_gpu *gpu = dev_to_gpu(dev); adreno_suspend() local
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H A Da6xx_gmu.c21 struct msm_gpu *gpu = &adreno_gpu->base; in a6xx_gmu_fault() local
22 struct drm_device *dev = gpu->dev; in a6xx_gmu_fault()
29 del_timer(&gpu->hangcheck_timer); in a6xx_gmu_fault()
32 queue_work(priv->wq, &gpu->recover_work); in a6xx_gmu_fault()
80 /* This can be called from gpu state code so make sure GMU is valid */ in a6xx_gmu_sptprac_is_on()
96 /* This can be called from gpu state code so make sure GMU is valid */ in a6xx_gmu_gx_is_on()
107 void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp) in a6xx_gmu_set_freq() argument
109 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_gmu_set_freq()
139 dev_pm_opp_set_bw(&gpu->pdev->dev, opp); in a6xx_gmu_set_freq()
163 dev_pm_opp_set_bw(&gpu in a6xx_gmu_set_freq()
167 a6xx_gmu_get_freq(struct msm_gpu *gpu) a6xx_gmu_get_freq() argument
867 a6xx_gmu_set_initial_freq(struct msm_gpu *gpu, struct a6xx_gmu *gmu) a6xx_gmu_set_initial_freq() argument
881 a6xx_gmu_set_initial_bw(struct msm_gpu *gpu, struct a6xx_gmu *gmu) a6xx_gmu_set_initial_bw() argument
897 struct msm_gpu *gpu = &adreno_gpu->base; a6xx_gmu_resume() local
996 struct msm_gpu *gpu = &adreno_gpu->base; a6xx_bus_clear_pending_transactions() local
1081 struct msm_gpu *gpu = &a6xx_gpu->base.base; a6xx_gmu_stop() local
1287 struct msm_gpu *gpu = &adreno_gpu->base; a6xx_gmu_rpmh_votes_init() local
1337 struct msm_gpu *gpu = &adreno_gpu->base; a6xx_gmu_pwrlevels_probe() local
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/kernel/linux/linux-6.6/drivers/gpu/drm/msm/adreno/
H A Da6xx_gpu.h57 static inline bool a6xx_has_gbif(struct adreno_gpu *gpu) in a6xx_has_gbif() argument
59 if(adreno_is_a630(gpu)) in a6xx_has_gbif()
83 int a6xx_gmu_resume(struct a6xx_gpu *gpu);
84 int a6xx_gmu_stop(struct a6xx_gpu *gpu);
97 void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp,
99 unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu);
101 void a6xx_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
104 struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu);
108 void a6xx_gpu_sw_reset(struct msm_gpu *gpu, bool assert);
H A Da6xx_gmu.c23 struct msm_gpu *gpu = &adreno_gpu->base; in a6xx_gmu_fault() local
29 del_timer(&gpu->hangcheck_timer); in a6xx_gmu_fault()
32 kthread_queue_work(gpu->worker, &gpu->recover_work); in a6xx_gmu_fault()
80 /* This can be called from gpu state code so make sure GMU is valid */ in a6xx_gmu_sptprac_is_on()
96 /* This can be called from gpu state code so make sure GMU is valid */ in a6xx_gmu_gx_is_on()
107 void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp, in a6xx_gmu_set_freq() argument
110 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_gmu_set_freq()
142 dev_pm_opp_set_opp(&gpu->pdev->dev, opp); in a6xx_gmu_set_freq()
165 dev_pm_opp_set_opp(&gpu in a6xx_gmu_set_freq()
168 a6xx_gmu_get_freq(struct msm_gpu *gpu) a6xx_gmu_get_freq() argument
878 struct msm_gpu *gpu = &adreno_gpu->base; a6xx_gmu_force_off() local
914 a6xx_gmu_set_initial_freq(struct msm_gpu *gpu, struct a6xx_gmu *gmu) a6xx_gmu_set_initial_freq() argument
928 a6xx_gmu_set_initial_bw(struct msm_gpu *gpu, struct a6xx_gmu *gmu) a6xx_gmu_set_initial_bw() argument
944 struct msm_gpu *gpu = &adreno_gpu->base; a6xx_gmu_resume() local
1103 struct msm_gpu *gpu = &a6xx_gpu->base.base; a6xx_gmu_stop() local
1309 struct msm_gpu *gpu = &adreno_gpu->base; a6xx_gmu_rpmh_votes_init() local
1359 struct msm_gpu *gpu = &adreno_gpu->base; a6xx_gmu_pwrlevels_probe() local
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/kernel/linux/linux-5.10/drivers/gpu/drm/msm/
H A Dmsm_ringbuffer.c10 struct msm_ringbuffer *msm_ringbuffer_new(struct msm_gpu *gpu, int id, in msm_ringbuffer_new() argument
26 ring->gpu = gpu; in msm_ringbuffer_new()
29 ring->start = msm_gem_kernel_new(gpu->dev, MSM_GPU_RINGBUFFER_SZ, in msm_ringbuffer_new()
30 check_apriv(gpu, MSM_BO_WC | MSM_BO_GPU_READONLY), in msm_ringbuffer_new()
31 gpu->aspace, &ring->bo, &ring->iova); in msm_ringbuffer_new()
51 snprintf(name, sizeof(name), "gpu-ring-%d", ring->id); in msm_ringbuffer_new()
53 ring->fctx = msm_fence_context_alloc(gpu->dev, name); in msm_ringbuffer_new()
69 msm_gem_kernel_put(ring->bo, ring->gpu->aspace, false); in msm_ringbuffer_destroy()
H A Dmsm_perf.c9 * tail -f /sys/kernel/debug/dri/<minor>/gpu
12 * and any gpu specific performance counters that are supported.
61 struct msm_gpu *gpu = priv->gpu; in refill_buf() local
72 for (i = 0; i < gpu->num_perfcntrs; i++) { in refill_buf()
73 const struct msm_gpu_perfcntr *perfcntr = &gpu->perfcntrs[i]; in refill_buf()
90 ret = msm_gpu_perfcntr_sample(gpu, &activetime, &totaltime, in refill_buf()
155 struct msm_gpu *gpu = priv->gpu; in perf_open() local
160 if (perf->open || !gpu) { in perf_open()
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H A Dmsm_gpummu.c13 struct msm_gpu *gpu; member
50 gpu_write(gpummu->gpu, REG_A2XX_MH_MMU_INVALIDATE, in msm_gpummu_map()
65 gpu_write(gpummu->gpu, REG_A2XX_MH_MMU_INVALIDATE, in msm_gpummu_unmap()
88 struct msm_mmu *msm_gpummu_new(struct device *dev, struct msm_gpu *gpu) in msm_gpummu_new() argument
103 gpummu->gpu = gpu; in msm_gpummu_new()
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/
H A Dmsm_perf.c9 * tail -f /sys/kernel/debug/dri/<minor>/gpu
12 * and any gpu specific performance counters that are supported.
61 struct msm_gpu *gpu = priv->gpu; in refill_buf() local
72 for (i = 0; i < gpu->num_perfcntrs; i++) { in refill_buf()
73 const struct msm_gpu_perfcntr *perfcntr = &gpu->perfcntrs[i]; in refill_buf()
90 ret = msm_gpu_perfcntr_sample(gpu, &activetime, &totaltime, in refill_buf()
155 struct msm_gpu *gpu = priv->gpu; in perf_open() local
158 if (!gpu) in perf_open()
[all...]
H A Dmsm_submitqueue.c11 struct msm_gpu *gpu, int sysprof) in msm_file_private_set_sysprof()
23 pm_runtime_get_sync(&gpu->pdev->dev); in msm_file_private_set_sysprof()
26 refcount_inc(&gpu->sysprof_active); in msm_file_private_set_sysprof()
35 pm_runtime_put_autosuspend(&gpu->pdev->dev); in msm_file_private_set_sysprof()
38 refcount_dec(&gpu->sysprof_active); in msm_file_private_set_sysprof()
170 if (!priv->gpu) in msm_submitqueue_create()
173 ret = msm_gpu_convert_priority(priv->gpu, prio, &ring_nr, &sched_prio); in msm_submitqueue_create()
186 queue->entity = get_sched_entity(ctx, priv->gpu->rb[ring_nr], in msm_submitqueue_create()
222 if (!priv->gpu) in msm_submitqueue_init()
225 max_priority = (priv->gpu in msm_submitqueue_init()
10 msm_file_private_set_sysprof(struct msm_file_private *ctx, struct msm_gpu *gpu, int sysprof) msm_file_private_set_sysprof() argument
[all...]
H A Dmsm_gpummu.c13 struct msm_gpu *gpu; member
50 gpu_write(gpummu->gpu, REG_A2XX_MH_MMU_INVALIDATE, in msm_gpummu_map()
65 gpu_write(gpummu->gpu, REG_A2XX_MH_MMU_INVALIDATE, in msm_gpummu_unmap()
93 struct msm_mmu *msm_gpummu_new(struct device *dev, struct msm_gpu *gpu) in msm_gpummu_new() argument
108 gpummu->gpu = gpu; in msm_gpummu_new()
H A Dmsm_rd.c14 * caused the gpu crash/lockup.
57 RD_CMDSTREAM_ADDR, /* gpu addr of cmdstream */
175 struct msm_gpu *gpu = priv->gpu; in rd_open() local
181 if (!gpu) in rd_open()
184 mutex_lock(&gpu->lock); in rd_open()
197 /* the parsing tools need to know gpu-id to know which in rd_open()
202 gpu->funcs->get_param(gpu, NULL, MSM_PARAM_GPU_ID, &val, &zero); in rd_open()
207 gpu in rd_open()
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/kernel/linux/linux-5.10/drivers/gpu/drm/etnaviv/
H A Detnaviv_drv.h37 struct etnaviv_gpu *gpu[ETNA_MAX_PIPES]; member
72 u16 etnaviv_buffer_init(struct etnaviv_gpu *gpu);
73 u16 etnaviv_buffer_config_mmuv2(struct etnaviv_gpu *gpu, u32 mtlb_addr, u32 safe_addr);
74 u16 etnaviv_buffer_config_pta(struct etnaviv_gpu *gpu, unsigned short id);
75 void etnaviv_buffer_end(struct etnaviv_gpu *gpu);
76 void etnaviv_sync_point_queue(struct etnaviv_gpu *gpu, unsigned int event);
77 void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, u32 exec_state,
81 bool etnaviv_cmd_validate_one(struct etnaviv_gpu *gpu,
H A Detnaviv_dump.c82 struct etnaviv_gpu *gpu) in etnaviv_core_dump_registers()
89 reg->value = gpu_read(gpu, etnaviv_dump_registers[i]); in etnaviv_core_dump_registers()
115 struct etnaviv_gpu *gpu = submit->gpu; in etnaviv_core_dump() local
137 mmu_size + gpu->buffer.size + submit->cmdbuf.size; in etnaviv_core_dump()
161 dev_warn(gpu->dev, "failed to allocate devcoredump file\n"); in etnaviv_core_dump()
171 etnaviv_core_dump_registers(&iter, gpu); in etnaviv_core_dump()
173 etnaviv_core_dump_mem(&iter, ETDUMP_BUF_RING, gpu->buffer.vaddr, in etnaviv_core_dump()
174 gpu->buffer.size, in etnaviv_core_dump()
175 etnaviv_cmdbuf_get_va(&gpu in etnaviv_core_dump()
81 etnaviv_core_dump_registers(struct core_dump_iterator *iter, struct etnaviv_gpu *gpu) etnaviv_core_dump_registers() argument
[all...]
H A Detnaviv_cmd_parser.c16 struct etnaviv_gpu *gpu; member
93 dev_warn_once(state->gpu->dev, in etnaviv_warn_if_non_sensitive()
123 dev_warn_ratelimited(state->gpu->dev, in etnaviv_validate_load_state()
147 bool etnaviv_cmd_validate_one(struct etnaviv_gpu *gpu, u32 *stream, in etnaviv_cmd_validate_one() argument
156 state.gpu = gpu; in etnaviv_cmd_validate_one()
189 dev_err(gpu->dev, "%s: op %u not permitted at offset %tu\n", in etnaviv_cmd_validate_one()
200 dev_err(gpu->dev, "%s: commands overflow end of buffer: %tu > %u\n", in etnaviv_cmd_validate_one()
H A Detnaviv_perfmon.h26 int etnaviv_pm_query_dom(struct etnaviv_gpu *gpu,
29 int etnaviv_pm_query_sig(struct etnaviv_gpu *gpu,
35 void etnaviv_perfmon_process(struct etnaviv_gpu *gpu,
H A Detnaviv_gem_submit.c32 struct etnaviv_gpu *gpu, size_t nr_bos, size_t nr_pmrs) in submit_create()
49 submit->gpu = gpu; in submit_create()
377 pm_runtime_put_autosuspend(submit->gpu->dev); in submit_cleanup()
404 wake_up_all(&submit->gpu->fence_event); in submit_cleanup()
410 mutex_lock(&submit->gpu->fence_lock); in submit_cleanup()
411 idr_remove(&submit->gpu->fence_idr, submit->out_fence_id); in submit_cleanup()
412 mutex_unlock(&submit->gpu->fence_lock); in submit_cleanup()
434 struct etnaviv_gpu *gpu; in etnaviv_ioctl_gem_submit() local
444 gpu in etnaviv_ioctl_gem_submit()
31 submit_create(struct drm_device *dev, struct etnaviv_gpu *gpu, size_t nr_bos, size_t nr_pmrs) submit_create() argument
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/loongson/
H A Dlsdc_gfxpll.c46 unsigned sel_out_gpu : 1; /* 42 gpu output clk enable */
83 unsigned int *gpu) in loongson_gfxpll_get_rates()
113 if (gpu) in loongson_gfxpll_get_rates()
114 *gpu = gpu_mhz; in loongson_gfxpll_get_rates()
122 unsigned int dc, gmc, gpu; in loongson_gfxpll_print() local
134 this->funcs->get_rates(this, &dc, &gmc, &gpu); in loongson_gfxpll_print()
136 drm_printf(p, "dc: %uMHz, gmc: %uMHz, gpu: %uMHz\n", dc, gmc, gpu); in loongson_gfxpll_print()
80 loongson_gfxpll_get_rates(struct loongson_gfxpll * const this, unsigned int *dc, unsigned int *gmc, unsigned int *gpu) loongson_gfxpll_get_rates() argument
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/
H A Di915_gpu_error.h251 i915_gpu_coredump_get(struct i915_gpu_coredump *gpu) in i915_gpu_coredump_get() argument
253 kref_get(&gpu->ref); in i915_gpu_coredump_get()
254 return gpu; in i915_gpu_coredump_get()
262 static inline void i915_gpu_coredump_put(struct i915_gpu_coredump *gpu) in i915_gpu_coredump_put() argument
264 if (gpu) in i915_gpu_coredump_put()
265 kref_put(&gpu->ref, __i915_gpu_coredump_free); in i915_gpu_coredump_put()
328 static inline void i915_gpu_coredump_put(struct i915_gpu_coredump *gpu) in i915_gpu_coredump_put() argument
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/
H A Di915_sysfs.c167 struct i915_gpu_coredump *gpu; in error_state_read() local
177 gpu = i915_first_error_state(i915); in error_state_read()
178 if (IS_ERR(gpu)) { in error_state_read()
179 ret = PTR_ERR(gpu); in error_state_read()
180 } else if (gpu) { in error_state_read()
181 ret = i915_gpu_coredump_copy_to_buffer(gpu, buf, off, count); in error_state_read()
182 i915_gpu_coredump_put(gpu); in error_state_read()

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