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/kernel/linux/linux-6.6/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
H A Ducode_loader.c17 #include <defs.h>
/third_party/mesa3d/src/gallium/drivers/vc4/
H A Dvc4_opt_dead_code.c125 c->defs[inst->dst.index] = NULL; in qir_opt_dead_code()
H A Dvc4_qir_lower_uniforms.c175 c->defs[mov->dst.index] = mov; in qir_lower_uniforms()
/third_party/python/Include/
H A Dceval.h17 PyObject *const *defs, int defc,
/kernel/linux/linux-5.10/arch/mips/pci/
H A Dpcie-octeon.c17 #include <asm/octeon/cvmx-npei-defs.h>
18 #include <asm/octeon/cvmx-pciercx-defs.h>
19 #include <asm/octeon/cvmx-pescx-defs.h>
20 #include <asm/octeon/cvmx-pexp-defs.h>
21 #include <asm/octeon/cvmx-pemx-defs.h>
22 #include <asm/octeon/cvmx-dpi-defs.h>
23 #include <asm/octeon/cvmx-sli-defs.h>
24 #include <asm/octeon/cvmx-sriox-defs.h>
H A Dpci-octeon.c20 #include <asm/octeon/cvmx-npi-defs.h>
21 #include <asm/octeon/cvmx-pci-defs.h>
/kernel/linux/linux-6.6/arch/mips/pci/
H A Dpcie-octeon.c17 #include <asm/octeon/cvmx-npei-defs.h>
18 #include <asm/octeon/cvmx-pciercx-defs.h>
19 #include <asm/octeon/cvmx-pescx-defs.h>
20 #include <asm/octeon/cvmx-pexp-defs.h>
21 #include <asm/octeon/cvmx-pemx-defs.h>
22 #include <asm/octeon/cvmx-dpi-defs.h>
23 #include <asm/octeon/cvmx-sli-defs.h>
24 #include <asm/octeon/cvmx-sriox-defs.h>
H A Dpci-octeon.c20 #include <asm/octeon/cvmx-npi-defs.h>
21 #include <asm/octeon/cvmx-pci-defs.h>
/third_party/mesa3d/src/broadcom/compiler/
H A Dvir.c344 c->defs = reralloc(c, c->defs, struct qinst *, in vir_get_temp()
346 memset(&c->defs[old_size], 0, in vir_get_temp()
347 sizeof(c->defs[0]) * (c->defs_array_size - old_size)); in vir_get_temp()
453 c->defs[inst->dst.index] = inst; in vir_emit_def()
464 c->defs[inst->dst.index] = NULL; in vir_emit_nondef()
1927 c->defs[qinst->dst.index] = NULL; in vir_remove_instruction()
1944 c->defs[reg.index] && in vir_follow_movs()
1945 (c->defs[reg.index]->op == QOP_MOV || in vir_follow_movs()
1946 c->defs[re in vir_follow_movs()
[all...]
H A Dnir_to_vir.c774 is_ldunif_signal(&c->defs[result.index]->qpu.sig) && in ntq_store_dest()
775 last_inst != c->defs[result.index]; in ntq_store_dest()
778 (last_inst == c->defs[result.index] || is_reused_uniform)); in ntq_store_dest()
807 is_ld_signal(&c->defs[last_inst->dst.index]->qpu.sig))) { in ntq_store_dest()
809 last_inst = c->defs[result.index]; in ntq_store_dest()
813 c->defs[last_inst->dst.index] = NULL; in ntq_store_dest()
843 * (for SSA defs) or finding them in the list of registers awaiting a TMU flush
1511 vir_set_pack(c->defs[result.index], V3D_QPU_PACK_L); in ntq_emit_alu()
1522 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_L); in ntq_emit_alu()
1730 vir_set_unpack(c->defs[resul in ntq_emit_alu()
[all...]
/third_party/mesa3d/src/gallium/tests/trivial/
H A Dcompute.c99 preprocess_prog(struct context *ctx, const char *src, const char *defs) in preprocess_prog() argument
117 defs ? defs : "", tmp); in preprocess_prog()
144 const char *src, const char *defs) in init_prog()
155 char *psrc = preprocess_prog(ctx, src, defs); in init_prog()
142 init_prog(struct context *ctx, unsigned local_sz, unsigned private_sz, unsigned input_sz, const char *src, const char *defs) init_prog() argument
/kernel/linux/linux-5.10/arch/mips/cavium-octeon/
H A Doct_ilm.c5 #include <asm/octeon/cvmx-ciu-defs.h>
/kernel/linux/linux-6.6/arch/mips/cavium-octeon/
H A Doct_ilm.c5 #include <asm/octeon/cvmx-ciu-defs.h>
/kernel/linux/linux-5.10/include/linux/
H A Dpage_ref.h8 #include <linux/tracepoint-defs.h>
/kernel/linux/linux-5.10/fs/sharefs/
H A Dsuper.c8 #include <linux/backing-dev-defs.h>
/kernel/linux/linux-5.10/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/
H A Ddma_local.h22 #include <defs.h> /* HRTCAT() */
/kernel/linux/linux-6.6/fs/sharefs/
H A Dsuper.c8 #include <linux/backing-dev-defs.h>
/kernel/linux/linux-6.6/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/
H A Ddma_local.h22 #include <defs.h> /* HRTCAT() */
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
H A DSIPreAllocateWWMRegs.cpp211 for (MachineOperand &DefOpnd : MI.defs()) { in runOnMachineFunction()
/third_party/selinux/libsepol/src/
H A DMakefile38 LD_SONAME_FLAGS=-soname,$(LIBSO),--version-script=$(LIBMAP),-z,defs
/third_party/mesa3d/src/compiler/nir/
H A Dnir_validate.c48 * equivalent to the uses and defs in nir_register, but built up by the
51 struct set *uses, *if_uses, *defs; member
197 /* As we walk SSA defs, we add every use to this set. We need to make sure in validate_ssa_src()
268 _mesa_set_add(reg_state->defs, dest); in validate_reg_dest()
1427 list_validate(&reg->defs); in prevalidate_reg_decl()
1433 reg_state->defs = _mesa_pointer_set_create(reg_state); in prevalidate_reg_decl()
1463 struct set_entry *entry = _mesa_set_search(reg_state->defs, src); in postvalidate_reg_decl()
1465 _mesa_set_remove(reg_state->defs, entry); in postvalidate_reg_decl()
1467 validate_assert(state, reg_state->defs->entries == 0); in postvalidate_reg_decl()
1613 * never actually hit the number of SSA defs becaus in validate_function_impl()
[all...]
/third_party/mesa3d/src/intel/vulkan/
H A Danv_nir_apply_pipeline_layout.c380 struct res_index_defs defs; in unpack_res_index() local
383 defs.desc_stride = nir_extract_u8(b, packed, nir_imm_int(b, 2)); in unpack_res_index()
384 defs.set_idx = nir_extract_u8(b, packed, nir_imm_int(b, 1)); in unpack_res_index()
385 defs.dyn_offset_base = nir_extract_u8(b, packed, nir_imm_int(b, 0)); in unpack_res_index()
387 defs.desc_offset_base = nir_channel(b, index, 1); in unpack_res_index()
388 defs.array_index = nir_umin(b, nir_channel(b, index, 2), in unpack_res_index()
391 return defs; in unpack_res_index()
/kernel/linux/linux-5.10/drivers/watchdog/
H A Docteon-wdt-main.c63 #include <asm/octeon/cvmx-ciu2-defs.h>
64 #include <asm/octeon/cvmx-rst-defs.h>
/kernel/linux/linux-6.6/drivers/watchdog/
H A Docteon-wdt-main.c64 #include <asm/octeon/cvmx-ciu2-defs.h>
65 #include <asm/octeon/cvmx-rst-defs.h>
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
H A DDetectDeadLanes.cpp287 const MachineOperand &Def = *MI.defs().begin(); in transferDefinedLanesStep()
347 "Should not have subregister defs in machine SSA phase"); in transferDefinedLanes()
413 "Should not have subregister defs in machine SSA phase"); in determineInitialDefinedLanes()
430 const MachineOperand &Def = *UseMI.defs().begin(); in determineInitialUsedLanes()
494 // First pass: Populate defs/uses of vregs with initial values in runOnce()
573 // register coalescer cannot deal with hidden dead defs. However without in runOnMachineFunction()

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