| /kernel/linux/linux-5.10/drivers/net/wireless/broadcom/brcm80211/brcmfmac/ |
| H A D | chip.h | 10 #define CORE_CC_REG(base, field) \
11 (base + offsetof(struct chipcregs, field))
22 * @rambase: RAM base address (only applicable for ARM CR4 chips).
45 * @base: base address of core register space.
50 u32 base; member
|
| /kernel/linux/linux-5.10/scripts/atomic/ |
| H A D | atomic-tbl.sh | 47 local base=""
55 for base in "${pfx}${name}${sfx}${order}" "${name}"; do
56 file="${ATOMICDIR}/fallbacks/${base}"
|
| /kernel/linux/linux-5.10/include/linux/ |
| H A D | of_fdt.h | 69 extern void early_init_dt_add_memory_arch(u64 base, u64 size);
70 extern int early_init_dt_mark_hotplug_memory_arch(u64 base, u64 size);
71 extern int early_init_dt_reserve_memory_arch(phys_addr_t base, phys_addr_t size,
|
| /kernel/linux/linux-5.10/scripts/ |
| H A D | objdiff | 59 base=${1##*/}
60 stripped=$dir/${base%.o}.stripped
61 dis=$dir/${base%.o}.dis
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/exynos/ |
| H A D | exynos_drm_gem.h | 14 #define to_exynos_gem(x) container_of(x, struct exynos_drm_gem, base)
21 * @base: a gem object.
39 struct drm_gem_object base; member
84 drm_gem_object_put(&exynos_gem->base); in exynos_drm_gem_put()
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/gem/ |
| H A D | i915_gem_fence.c | 75 obj->base.resv, NULL, true, in i915_gem_object_lock_fence()
76 i915_fence_timeout(to_i915(obj->base.dev)), in i915_gem_object_lock_fence()
80 dma_resv_add_excl_fence(obj->base.resv, &stub->dma); in i915_gem_object_lock_fence()
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/lima/ |
| H A D | lima_sched.h | 21 struct drm_sched_job base; member
40 struct drm_sched_entity base; member
50 struct drm_gpu_scheduler base; member
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/dma/ |
| H A D | base.c | 73 sclass->base = oclass[0]; in nvkm_dma_oclass_base_get()
86 oclass->base = nvkm_dma_sclass[index]; in nvkm_dma_oclass_fifo_get()
101 .base.sclass = nvkm_dma_oclass_base_get,
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/msm/edp/ |
| H A D | edp_bridge.c | 9 struct drm_bridge base; member
12 #define to_edp_bridge(x) container_of(x, struct edp_bridge, base)
97 bridge = &edp_bridge->base; in msm_edp_bridge_init()
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/gr/ |
| H A D | gp108.c | 43 const u64 base = lsfw->offset.img + lsfw->app_start_offset; in gp108_gr_acr_bld_write() local
44 const u64 code = base + lsfw->app_resident_code_offset; in gp108_gr_acr_bld_write()
45 const u64 data = base + lsfw->app_resident_data_offset; in gp108_gr_acr_bld_write()
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/ |
| H A D | nouveau_fence.h | 12 struct dma_fence base; member
87 struct nouveau_fence_chan base; member
92 struct nouveau_fence_priv base; member
|
| H A D | nvc0_fence.c | 83 fctx->base.emit32 = nvc0_fence_emit32; in nvc0_fence_context_new()
84 fctx->base.sync32 = nvc0_fence_sync32; in nvc0_fence_context_new()
95 priv->base.context_new = nvc0_fence_context_new; in nvc0_fence_create()
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/disp/ |
| H A D | rootnv04.c | 94 .base.oclass = NV04_DISP,
95 .base.minver = -1,
96 .base.maxver = -1,
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/fifo/ |
| H A D | gpfifotu102.c | 32 tu102_fifo_gpfifo_submit_token(struct nvkm_fifo_chan *base) in tu102_fifo_gpfifo_submit_token() argument
34 struct gk104_fifo_chan *chan = gk104_fifo_chan(base); in tu102_fifo_gpfifo_submit_token()
35 return (chan->runl << 16) | chan->base.chid; in tu102_fifo_gpfifo_submit_token()
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/vmwgfx/ |
| H A D | vmwgfx_fence.h | 59 struct dma_fence base; member
78 dma_fence_put(&fence->base); in vmw_fence_obj_unreference()
85 dma_fence_get(&fence->base); in vmw_fence_obj_reference()
|
| /kernel/linux/linux-5.10/drivers/mfd/ |
| H A D | bcm2835-pm.c | 43 pm->base = devm_ioremap_resource(dev, res); in bcm2835_pm_probe()
44 if (IS_ERR(pm->base)) in bcm2835_pm_probe()
45 return PTR_ERR(pm->base); in bcm2835_pm_probe()
|
| /kernel/linux/linux-6.6/drivers/clk/davinci/ |
| H A D | psc.h | 82 void __iomem *base);
87 void __iomem *base);
94 int (*psc_init)(struct device *dev, void __iomem *base);
|
| /kernel/linux/linux-6.6/drivers/firmware/efi/libstub/ |
| H A D | arm64.c | 103 unsigned long base = image_base; in efi_cache_sync_image() local
107 asm("dc " DCTYPE ", %0" :: "r"(base)); in efi_cache_sync_image()
108 base += lsize; in efi_cache_sync_image()
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_job.h | 40 container_of((sched_job), struct amdgpu_job, base)
48 struct drm_sched_job base; member
85 return to_amdgpu_ring(job->base.entity->rq->sched); in amdgpu_job_ring()
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/gpio/ |
| H A D | hw_gpio.h | 32 container_of((ptr), struct hw_gpio, base)
94 struct hw_gpio_pin base; member
110 container_of((hw_gpio_pin), struct hw_gpio, base)
|
| /kernel/linux/linux-6.6/kernel/locking/ |
| H A D | ww_rt_mutex.c | 14 struct rt_mutex *rtm = &lock->base; in ww_mutex_trylock()
42 struct rt_mutex *rtm = &lock->base; in __ww_rt_mutex_lock()
94 struct rt_mutex *rtm = &lock->base; in ww_mutex_unlock()
|
| /kernel/linux/linux-6.6/drivers/net/fjes/ |
| H A D | fjes_regs.h | 121 u8 *base = hw->base; \
122 writel((val), &base[(reg)]); \
|
| /kernel/linux/linux-6.6/drivers/net/wireless/broadcom/brcm80211/brcmfmac/ |
| H A D | chip.h | 10 #define CORE_CC_REG(base, field) \
11 (base + offsetof(struct chipcregs, field))
18 * @enum_base: base address of core enumeration space.
23 * @rambase: RAM base address (only applicable for ARM CR4 chips).
47 * @base: base address of core register space.
52 u32 base; member
|
| /kernel/linux/linux-6.6/drivers/net/ethernet/ti/icssg/ |
| H A D | icssg_stats.c | 23 u32 base = stats_base[slice]; in emac_update_hardware_stats() local
30 base + icssg_all_stats[i].offset, in emac_update_hardware_stats()
33 base + icssg_all_stats[i].offset, in emac_update_hardware_stats()
|
| /kernel/linux/linux-6.6/drivers/nvmem/ |
| H A D | sec-qfprom.c | 15 * @base: starting physical address for secure qfprom corrected address space.
19 phys_addr_t base; member
33 if (qcom_scm_io_readl(priv->base + (reg & ~3), &read_val)) { in sec_qfprom_reg_read()
68 priv->base = res->start; in sec_qfprom_probe()
|