Home
last modified time | relevance | path

Searched refs:base (Results 5276 - 5300 of 17150) sorted by relevance

1...<<211212213214215216217218219220>>...686

/third_party/node/deps/v8/src/debug/wasm/gdb-server/
H A Dgdb-server-thread.cc15 : Thread(v8::base::Thread::Options("GdbServerThread")), in GdbServerThread()
40 v8::base::MutexGuard guard(&mutex_); in CleanupThread()
104 v8::base::MutexGuard guard(&mutex_); in Stop()
/third_party/node/deps/v8/src/execution/
H A Dthread-local-top.cc38 stack_ = ::heap::base::Stack(nullptr); in Clear()
55 stack_ = ::heap::base::Stack(base::Stack::GetStackStart()); in Initialize()
/third_party/node/deps/v8/src/heap/
H A Dcode-object-registry.cc9 #include "src/base/logging.h"
15 base::MutexGuard guard(&code_object_registry_mutex_); in RegisterNewlyAllocatedCodeObject()
46 base::MutexGuard guard(&code_object_registry_mutex_); in Contains()
57 base::MutexGuard guard(&code_object_registry_mutex_); in GetCodeObjectStartFromInnerAddress()
/third_party/node/deps/v8/src/heap/cppgc/
H A Dincremental-marking-schedule.cc23 incremental_marking_start_time_ = v8::base::TimeTicks::Now(); in NotifyIncrementalMarkingStart()
45 v8::base::TimeTicks start_time) { in GetElapsedTimeInMs()
51 return (v8::base::TimeTicks::Now() - start_time).InMillisecondsF(); in GetElapsedTimeInMs()
/third_party/node/deps/v8/src/init/
H A Dstartup-data-util.cc12 #include "src/base/file-utils.h"
13 #include "src/base/logging.h"
14 #include "src/base/platform/platform.h"
15 #include "src/base/platform/wrappers.h"
48 FILE* file = base::Fopen(blob_file, "rb"); in Load()
61 base::Fclose(file); in Load()
82 base::RelativePath(directory_path, snapshot_name); in InitializeExternalStartupData()
/third_party/mesa3d/src/gallium/auxiliary/tgsi/
H A Dtgsi_vpos.c42 struct tgsi_transform_context base; member
93 transform.base.prolog = write_vpos_prolog; in tgsi_write_vpos()
97 return tgsi_transform_shader(tokens_in, new_len, &transform.base); in tgsi_write_vpos()
/third_party/mesa3d/src/gallium/winsys/i915/drm/
H A Di915_drm_fence.c84 idws->base.fence_reference = i915_drm_fence_reference; in i915_drm_winsys_init_fence_functions()
85 idws->base.fence_signalled = i915_drm_fence_signalled; in i915_drm_winsys_init_fence_functions()
86 idws->base.fence_finish = i915_drm_fence_finish; in i915_drm_winsys_init_fence_functions()
/third_party/skia/third_party/externals/spirv-tools/source/fuzz/
H A Dfuzzer_pass_split_blocks.cpp63 // The initial base instruction is the block label. in Apply()
64 uint32_t base = block->id(); in Apply() local
67 // base instruction. in Apply()
71 // only necessary to consider it as a base in case the first instruction in Apply()
76 // instruction as its own base, and clear the skip counts we have in Apply()
78 base = inst.result_id(); in Apply()
83 base, opcode, skip_count.count(opcode) ? skip_count.at(opcode) : 0)); in Apply()
/third_party/skia/third_party/externals/swiftshader/third_party/SPIRV-Tools/source/fuzz/
H A Dfuzzer_pass_split_blocks.cpp63 // The initial base instruction is the block label. in Apply()
64 uint32_t base = block->id(); in Apply() local
67 // base instruction. in Apply()
71 // only necessary to consider it as a base in case the first instruction in Apply()
76 // instruction as its own base, and clear the skip counts we have in Apply()
78 base = inst.result_id(); in Apply()
83 base, opcode, skip_count.count(opcode) ? skip_count.at(opcode) : 0)); in Apply()
/third_party/skia/third_party/externals/harfbuzz/src/
H A Dhb-number.cc65 bool whole_buffer, int base)
68 [base] (const char *p, char **end)
69 { return strtoul (p, end, base); });
/third_party/spirv-tools/source/fuzz/
H A Dfuzzer_pass_split_blocks.cpp63 // The initial base instruction is the block label. in Apply()
64 uint32_t base = block->id(); in Apply() local
67 // base instruction. in Apply()
71 // only necessary to consider it as a base in case the first instruction in Apply()
76 // instruction as its own base, and clear the skip counts we have in Apply()
78 base = inst.result_id(); in Apply()
83 base, opcode, skip_count.count(opcode) ? skip_count.at(opcode) : 0)); in Apply()
/kernel/linux/linux-5.10/drivers/fpga/
H A Ddfl-pci.c134 void __iomem *base; in cci_enumerate_feature_devs() local
164 base = cci_pci_ioremap_bar0(pcidev); in cci_enumerate_feature_devs()
165 if (!base) { in cci_enumerate_feature_devs()
175 if (dfl_feature_is_fme(base)) { in cci_enumerate_feature_devs()
185 v = readq(base + FME_HDR_CAP); in cci_enumerate_feature_devs()
191 v = readq(base + FME_HDR_PORT_OFST(i)); in cci_enumerate_feature_devs()
208 } else if (dfl_feature_is_port(base)) { in cci_enumerate_feature_devs()
/kernel/linux/linux-5.10/drivers/gpio/
H A Dgpio-pci-idio-16.c130 void __iomem *base; in idio_16_gpio_set() local
139 base = &idio16gpio->reg->out8_15; in idio_16_gpio_set()
141 base = &idio16gpio->reg->out0_7; in idio_16_gpio_set()
146 out_state = ioread8(base) | mask; in idio_16_gpio_set()
148 out_state = ioread8(base) & ~mask; in idio_16_gpio_set()
150 iowrite8(out_state, base); in idio_16_gpio_set()
327 idio16gpio->chip.base = -1; in idio_16_probe()
/kernel/linux/linux-5.10/drivers/auxdisplay/
H A Dimg-ascii-lcd.c36 * @base: the base address of the LCD registers
50 void __iomem *base; member
73 __raw_writeq(val, ctx->base); in boston_update()
76 __raw_writel(val, ctx->base); in boston_update()
78 __raw_writel(val, ctx->base + 4); in boston_update()
390 ctx->base = devm_platform_ioremap_resource(pdev, 0); in img_ascii_lcd_probe()
391 if (IS_ERR(ctx->base)) in img_ascii_lcd_probe()
392 return PTR_ERR(ctx->base); in img_ascii_lcd_probe()
/kernel/linux/linux-5.10/drivers/base/
H A Dplatform-msi.c109 static void platform_msi_free_descs(struct device *dev, int base, int nvec) in platform_msi_free_descs() argument
114 if (desc->platform.msi_index >= base && in platform_msi_free_descs()
115 desc->platform.msi_index < (base + nvec)) { in platform_msi_free_descs()
128 int i, base = 0; in platform_msi_alloc_descs_with_irq() local
133 base = desc->platform.msi_index + 1; in platform_msi_alloc_descs_with_irq()
142 desc->platform.msi_index = base + i; in platform_msi_alloc_descs_with_irq()
150 platform_msi_free_descs(dev, base, nvec); in platform_msi_alloc_descs_with_irq()
364 * @virq: The base irq from which to perform the free operation
389 * @virq: The base irq from which to perform the allocate operation
/kernel/linux/linux-5.10/arch/alpha/kernel/
H A Dpci-sysfs.c22 unsigned long base; in hose_mmap_page_range() local
25 base = sparse ? hose->sparse_mem_base : hose->dense_mem_base; in hose_mmap_page_range()
27 base = sparse ? hose->sparse_io_base : hose->dense_io_base; in hose_mmap_page_range()
29 vma->vm_pgoff += base >> PAGE_SHIFT; in hose_mmap_page_range()
274 unsigned long base; in has_sparse() local
276 base = (mmap_type == pci_mmap_mem) ? hose->sparse_mem_base : in has_sparse()
279 return base != 0; in has_sparse()
/kernel/linux/linux-5.10/arch/x86/crypto/
H A Dghash-clmulni-intel_glue.c149 .base = {
183 ahash_request_set_tfm(cryptd_req, &cryptd_tfm->base); in ghash_async_update()
201 ahash_request_set_tfm(cryptd_req, &cryptd_tfm->base); in ghash_async_final()
242 ahash_request_set_tfm(cryptd_req, &cryptd_tfm->base); in ghash_async_digest()
257 struct crypto_ahash *child = &ctx->cryptd_tfm->base; in ghash_async_setkey()
278 crypto_ahash_reqsize(&cryptd_tfm->base)); in ghash_async_init_tfm()
301 .base = {
/kernel/linux/linux-5.10/arch/arm/mach-cns3xxx/
H A Dcore.c260 void __iomem *base = ioremap(CNS3XXX_L2C_BASE, SZ_4K); in cns3xxx_l2x0_init() local
263 if (WARN_ON(!base)) in cns3xxx_l2x0_init()
275 val = readl(base + L310_TAG_LATENCY_CTRL); in cns3xxx_l2x0_init()
277 writel(val, base + L310_TAG_LATENCY_CTRL); in cns3xxx_l2x0_init()
288 val = readl(base + L310_DATA_LATENCY_CTRL); in cns3xxx_l2x0_init()
290 writel(val, base + L310_DATA_LATENCY_CTRL); in cns3xxx_l2x0_init()
293 l2x0_init(base, 0x00500000, 0xfe0f0fff); in cns3xxx_l2x0_init()
/kernel/linux/linux-5.10/drivers/clk/mmp/
H A Dclk-of-pxa1928.c187 int i, base, nr_resets; in pxa1928_clk_reset_init() local
194 base = 0; in pxa1928_clk_reset_init()
196 cells[base + i].clk_id = apbc_gate_clks[i].id; in pxa1928_clk_reset_init()
197 cells[base + i].reg = in pxa1928_clk_reset_init()
199 cells[base + i].flags = 0; in pxa1928_clk_reset_init()
200 cells[base + i].lock = apbc_gate_clks[i].lock; in pxa1928_clk_reset_init()
201 cells[base + i].bits = 0x4; in pxa1928_clk_reset_init()
/kernel/linux/linux-5.10/drivers/crypto/ccp/
H A Dccp-crypto-rsa.c25 return container_of(req, struct akcipher_request, base); in akcipher_request_cast()
89 ret = ccp_crypto_enqueue_request(&req->base, &rctx->cmd); in ccp_rsa_crypt()
205 struct ccp_ctx *ctx = crypto_tfm_ctx(&tfm->base); in ccp_rsa_exit_tfm()
218 .base = {
260 snprintf(alg->base.cra_name, CRYPTO_MAX_ALG_NAME, "%s", def->name); in ccp_register_rsa_alg()
261 snprintf(alg->base.cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s", in ccp_register_rsa_alg()
266 alg->base.cra_name, ret); in ccp_register_rsa_alg()
/kernel/linux/linux-5.10/drivers/clk/qcom/
H A Dclk-spmi-pmic-div.c26 u16 base; member
55 regmap_read(clkdiv->regmap, clkdiv->base + REG_EN_CTL, &val); in is_spmi_pmic_clkdiv_enabled()
68 ret = regmap_update_bits(clkdiv->regmap, clkdiv->base + REG_EN_CTL, in __spmi_pmic_clkdiv_set_enable_state()
85 regmap_read(clkdiv->regmap, clkdiv->base + REG_DIV_CTL1, &div_factor); in spmi_pmic_clkdiv_set_enable_state()
132 regmap_read(clkdiv->regmap, clkdiv->base + REG_DIV_CTL1, &div_factor); in clk_spmi_pmic_div_recalc_rate()
155 ret = regmap_update_bits(clkdiv->regmap, clkdiv->base + REG_DIV_CTL1, in clk_spmi_pmic_div_set_rate()
264 clkdiv[i].base = start + i * 0x100; in spmi_pmic_clkdiv_probe()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_color.c342 struct amdgpu_device *adev = drm_to_adev(crtc->base.state->dev); in amdgpu_dm_update_crtc_color_mgmt()
351 r = amdgpu_dm_verify_lut_sizes(&crtc->base); in amdgpu_dm_update_crtc_color_mgmt()
355 degamma_lut = __extract_blob_lut(crtc->base.degamma_lut, &degamma_size); in amdgpu_dm_update_crtc_color_mgmt()
356 regamma_lut = __extract_blob_lut(crtc->base.gamma_lut, &regamma_size); in amdgpu_dm_update_crtc_color_mgmt()
373 * Legacy regamma forces us to use the sRGB RGM as a base. in amdgpu_dm_update_crtc_color_mgmt()
375 * to use sRGB as a base as well, resulting in incorrect CRTC in amdgpu_dm_update_crtc_color_mgmt()
417 if (crtc->base.ctm) { in amdgpu_dm_update_crtc_color_mgmt()
418 ctm = (struct drm_color_ctm *)crtc->base.ctm->data; in amdgpu_dm_update_crtc_color_mgmt()
461 /* Get the correct base transfer function for implicit degamma. */ in amdgpu_dm_update_plane_color_mgmt()
473 degamma_lut = __extract_blob_lut(crtc->base in amdgpu_dm_update_plane_color_mgmt()
[all...]
/kernel/linux/linux-5.10/drivers/mtd/nand/raw/
H A Dnand_onfi.c37 struct nand_device *base = &chip->base; in nand_flash_detect_ext_param_page() local
101 nanddev_set_ecc_requirements(base, &requirements); in nand_flash_detect_ext_param_page()
146 struct nand_device *base = &chip->base; in nand_onfi_detect() local
157 memorg = nanddev_get_memorg(&chip->base); in nand_onfi_detect()
278 nanddev_set_ecc_requirements(base, &requirements); in nand_onfi_detect()
/kernel/linux/linux-6.6/arch/arm64/mm/
H A Dinit.c78 * mapping, round down the base of physical memory to a size that can
93 * memstart_addr, due to the fact that the base of the vmemmap region
171 /* User specifies base address explicitly. */ in reserve_crashkernel()
334 * Select a suitable value for the base of physical memory. in arm64_memblock_init()
382 u64 base = phys_initrd_start & PAGE_MASK; in arm64_memblock_init() local
383 u64 size = PAGE_ALIGN(phys_initrd_start + phys_initrd_size) - base; in arm64_memblock_init()
393 if (WARN(base < memblock_start_of_DRAM() || in arm64_memblock_init()
394 base + size > memblock_start_of_DRAM() + in arm64_memblock_init()
399 memblock_add(base, size); in arm64_memblock_init()
400 memblock_clear_nomap(base, siz in arm64_memblock_init()
[all...]
/kernel/linux/linux-5.10/tools/testing/selftests/x86/
H A Dentry_from_vm86.c192 unsigned long base; in do_umip_tests() member
196 struct table_desc gdt1 = { .base = 0x3c3c3c3c, .limit = 0x9999 }; in do_umip_tests()
197 struct table_desc gdt2 = { .base = 0x1a1a1a1a, .limit = 0xaeae }; in do_umip_tests()
198 struct table_desc idt1 = { .base = 0x7b7b7b7b, .limit = 0xf1f1 }; in do_umip_tests()
199 struct table_desc idt2 = { .base = 0x89898989, .limit = 0x1313 }; in do_umip_tests()
219 printf("[INFO]\tResult from SIDT: limit[0x%04x]base[0x%08lx]\n", in do_umip_tests()
220 idt1.limit, idt1.base); in do_umip_tests()
221 printf("[INFO]\tResult from SGDT: limit[0x%04x]base[0x%08lx]\n", in do_umip_tests()
222 gdt1.limit, gdt1.base); in do_umip_tests()

Completed in 20 milliseconds

1...<<211212213214215216217218219220>>...686