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/kernel/linux/linux-5.10/drivers/video/fbdev/omap2/omapfb/dss/
H A Dhdmi4_core.c33 return core->base + HDMI_CORE_AV; in hdmi_av_base()
38 void __iomem *base = core->base; in hdmi_core_ddc_init() local
41 REG_FLD_MOD(base, HDMI_CORE_AV_DPD, 0x7, 2, 0); in hdmi_core_ddc_init()
44 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 1) { in hdmi_core_ddc_init()
46 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xf, 3, 0); in hdmi_core_ddc_init()
48 if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS, in hdmi_core_ddc_init()
56 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xA, 3, 0); in hdmi_core_ddc_init()
59 if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS, in hdmi_core_ddc_init()
66 REG_FLD_MOD(base, HDMI_CORE_DDC_CM in hdmi_core_ddc_init()
81 void __iomem *base = core->base; hdmi_core_ddc_edid() local
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/vmwgfx/
H A Dvmwgfx_resource.c45 dma_resv_assert_held(res->backup->base.base.resv); in vmw_resource_mob_attach()
72 dma_resv_assert_held(backup->base.base.resv); in vmw_resource_mob_detach()
123 struct ttm_buffer_object *bo = &res->backup->base; in vmw_resource_release()
260 struct ttm_base_object *base; in vmw_user_resource_lookup_handle() local
264 base = ttm_base_object_lookup(tfile, handle); in vmw_user_resource_lookup_handle()
265 if (unlikely(base == NULL)) in vmw_user_resource_lookup_handle()
268 if (unlikely(ttm_base_object_type(base) != converter->object_type)) in vmw_user_resource_lookup_handle()
271 res = converter->base_obj_to_res(base); in vmw_user_resource_lookup_handle()
304 struct ttm_base_object *base; vmw_user_resource_noref_lookup_handle() local
[all...]
/kernel/linux/linux-5.10/drivers/spi/
H A Dspi-uniphier.c26 void __iomem *base; member
113 val = readl(priv->base + SSI_IE); in uniphier_spi_irq_enable()
115 writel(val, priv->base + SSI_IE); in uniphier_spi_irq_enable()
123 val = readl(priv->base + SSI_IE); in uniphier_spi_irq_disable()
125 writel(val, priv->base + SSI_IE); in uniphier_spi_irq_disable()
171 writel(val1, priv->base + SSI_CKS); in uniphier_spi_set_mode()
172 writel(val2, priv->base + SSI_FPS); in uniphier_spi_set_mode()
177 writel(val1, priv->base + SSI_TXWDS); in uniphier_spi_set_mode()
178 writel(val1, priv->base + SSI_RXWDS); in uniphier_spi_set_mode()
186 val = readl(priv->base in uniphier_spi_set_transfer_size()
[all...]
/kernel/linux/linux-6.6/drivers/spi/
H A Dspi-uniphier.c26 void __iomem *base; member
113 val = readl(priv->base + SSI_IE); in uniphier_spi_irq_enable()
115 writel(val, priv->base + SSI_IE); in uniphier_spi_irq_enable()
123 val = readl(priv->base + SSI_IE); in uniphier_spi_irq_disable()
125 writel(val, priv->base + SSI_IE); in uniphier_spi_irq_disable()
171 writel(val1, priv->base + SSI_CKS); in uniphier_spi_set_mode()
172 writel(val2, priv->base + SSI_FPS); in uniphier_spi_set_mode()
177 writel(val1, priv->base + SSI_TXWDS); in uniphier_spi_set_mode()
178 writel(val1, priv->base + SSI_RXWDS); in uniphier_spi_set_mode()
186 val = readl(priv->base in uniphier_spi_set_transfer_size()
[all...]
/kernel/linux/linux-6.6/drivers/video/fbdev/omap2/omapfb/dss/
H A Dhdmi4_core.c33 return core->base + HDMI_CORE_AV; in hdmi_av_base()
38 void __iomem *base = core->base; in hdmi_core_ddc_init() local
41 REG_FLD_MOD(base, HDMI_CORE_AV_DPD, 0x7, 2, 0); in hdmi_core_ddc_init()
44 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 1) { in hdmi_core_ddc_init()
46 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xf, 3, 0); in hdmi_core_ddc_init()
48 if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS, in hdmi_core_ddc_init()
56 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xA, 3, 0); in hdmi_core_ddc_init()
59 if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS, in hdmi_core_ddc_init()
66 REG_FLD_MOD(base, HDMI_CORE_DDC_CM in hdmi_core_ddc_init()
81 void __iomem *base = core->base; hdmi_core_ddc_edid() local
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/omapdrm/dss/
H A Dhdmi4_core.c32 return core->base + HDMI_CORE_AV; in hdmi_av_base()
37 void __iomem *base = core->base; in hdmi4_core_ddc_init() local
40 REG_FLD_MOD(base, HDMI_CORE_AV_DPD, 0x7, 2, 0); in hdmi4_core_ddc_init()
43 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 1) { in hdmi4_core_ddc_init()
45 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xf, 3, 0); in hdmi4_core_ddc_init()
47 if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS, in hdmi4_core_ddc_init()
55 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xA, 3, 0); in hdmi4_core_ddc_init()
58 if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS, in hdmi4_core_ddc_init()
65 REG_FLD_MOD(base, HDMI_CORE_DDC_CM in hdmi4_core_ddc_init()
80 void __iomem *base = core->base; hdmi4_core_ddc_read() local
[all...]
/kernel/linux/linux-6.6/drivers/i2c/busses/
H A Di2c-mpc.c85 void __iomem *base; member
117 writeb(x, i2c->base + MPC_I2C_CR); in writeccr()
132 writeb(0, i2c->base + MPC_I2C_SR); /* clear any status bits */ in mpc_i2c_fixup()
134 readb(i2c->base + MPC_I2C_DR); /* init xfer */ in mpc_i2c_fixup()
138 readb(i2c->base + MPC_I2C_DR); in mpc_i2c_fixup()
144 readb(i2c->base + MPC_I2C_DR); in mpc_i2c_fixup()
151 void __iomem *addr = i2c->base + MPC_I2C_SR; in i2c_mpc_wait_sr()
189 val = readb(i2c->base + MPC_I2C_SR); in mpc_i2c_fixup_A004447()
200 val = readb(i2c->base + MPC_I2C_DR); in mpc_i2c_fixup_A004447()
208 val = readb(i2c->base in mpc_i2c_fixup_A004447()
[all...]
/third_party/gn/src/gn/
H A Dohos_components_checker.cc12 #include "base/files/file_path.h"
13 #include "base/files/file_util.h"
14 #include "base/json/json_reader.h"
15 #include "base/values.h"
60 base::FilePath path(dir); in CreateScanOutDir()
61 base::CreateDirectory(path); in CreateScanOutDir()
70 base::FilePath path(dir); in RemoveScanOutDir()
71 base::DeleteFile(path, true); in RemoveScanOutDir()
75 static bool ReadBuildConfigFile(base::FilePath path, std::string &content) in ReadBuildConfigFile()
77 if (!base in ReadBuildConfigFile()
[all...]
H A Dqt_creator_writer.cc12 #include "base/files/file_path.h"
13 #include "base/files/file_util.h"
14 #include "base/strings/utf_string_conversions.h"
25 base::FilePath::CharType kProjectDirName[] =
27 base::FilePath::CharType kProjectName[] = FILE_PATH_LITERAL("all");
28 base::FilePath::CharType kMainProjectFileSuffix[] =
30 base::FilePath::CharType kSourcesFileSuffix[] = FILE_PATH_LITERAL(".files");
31 base::FilePath::CharType kIncludesFileSuffix[] = FILE_PATH_LITERAL(".includes");
32 base::FilePath::CharType kDefinesFileSuffix[] = FILE_PATH_LITERAL(".config");
40 base in RunAndWriteFile()
[all...]
/third_party/mesa3d/src/gallium/drivers/i915/
H A Di915_state.c1030 i915->base.create_blend_state = i915_create_blend_state; in i915_init_state_functions()
1031 i915->base.bind_blend_state = i915_bind_blend_state; in i915_init_state_functions()
1032 i915->base.delete_blend_state = i915_delete_blend_state; in i915_init_state_functions()
1034 i915->base.create_sampler_state = i915_create_sampler_state; in i915_init_state_functions()
1035 i915->base.bind_sampler_states = i915_bind_sampler_states; in i915_init_state_functions()
1036 i915->base.delete_sampler_state = i915_delete_sampler_state; in i915_init_state_functions()
1038 i915->base.create_depth_stencil_alpha_state = in i915_init_state_functions()
1040 i915->base.bind_depth_stencil_alpha_state = i915_bind_depth_stencil_state; in i915_init_state_functions()
1041 i915->base.delete_depth_stencil_alpha_state = in i915_init_state_functions()
1044 i915->base in i915_init_state_functions()
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/
H A Drv1_clk_mgr.c45 bool dispclk_increase = new_clocks->dispclk_khz > clk_mgr->base.clks.dispclk_khz; in rv1_determine_dppclk_threshold()
47 bool cur_dpp_div = clk_mgr->base.clks.dispclk_khz > clk_mgr->base.clks.dppclk_khz; in rv1_determine_dppclk_threshold()
77 if (clk_mgr->base.clks.dispclk_khz <= disp_clk_threshold) in rv1_determine_dppclk_threshold()
185 clk_mgr->base.clks.dispclk_khz = new_clocks->dispclk_khz; in ramp_up_dispclk_with_dpp()
186 clk_mgr->base.clks.dppclk_khz = new_clocks->dppclk_khz; in ramp_up_dispclk_with_dpp()
187 clk_mgr->base.clks.max_supported_dppclk_khz = new_clocks->max_supported_dppclk_khz; in ramp_up_dispclk_with_dpp()
324 clk_mgr->base.ctx = ctx; in rv1_clk_mgr_construct()
326 clk_mgr->base.funcs = &rv1_clk_funcs; in rv1_clk_mgr_construct()
334 clk_mgr->base in rv1_clk_mgr_construct()
[all...]
/kernel/linux/linux-5.10/drivers/phy/socionext/
H A Dphy-uniphier-pcie.c52 void __iomem *base; member
68 writel(data, priv->base + PCL_PHY_TEST_I); in uniphier_pciephy_testio_write()
69 readl(priv->base + PCL_PHY_TEST_O); in uniphier_pciephy_testio_write()
70 readl(priv->base + PCL_PHY_TEST_O); in uniphier_pciephy_testio_write()
82 val = readl(priv->base + PCL_PHY_TEST_O) & TESTO_DAT_MASK; in uniphier_pciephy_set_param()
97 readl(priv->base + PCL_PHY_TEST_O); in uniphier_pciephy_set_param()
104 val = readl(priv->base + PCL_PHY_RESET); in uniphier_pciephy_assert()
107 writel(val, priv->base + PCL_PHY_RESET); in uniphier_pciephy_assert()
114 val = readl(priv->base + PCL_PHY_RESET); in uniphier_pciephy_deassert()
116 writel(val, priv->base in uniphier_pciephy_deassert()
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/dispnv50/
H A Dheadc57d.c33 struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; in headc57d_or()
34 const int i = head->base.index; in headc57d_or()
68 struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; in headc57d_procamp()
69 const int i = head->base.index; in headc57d_procamp()
86 struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; in headc57d_olut_clr()
87 const int i = head->base.index; in headc57d_olut_clr()
100 struct nvif_push *push = nv50_disp(head->base in headc57d_olut_set()
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/
H A Ddce_clk_mgr.c150 * clk_mgr->base.dentist_vco_freq_khz) / target_div; in dce_get_dp_ref_freq_khz()
237 struct dmcu *dmcu = clk_mgr_dce->base.ctx->dc->res_pool->dmcu; in dce_set_clock()
242 clk_mgr_dce->base.dentist_vco_freq_khz / 64); in dce_set_clock()
274 struct dc_debug_options *debug = &clk_mgr_dce->base.ctx->dc->debug; in dce_clock_read_integrated_info()
275 struct dc_bios *bp = clk_mgr_dce->base.ctx->dc_bios; in dce_clock_read_integrated_info()
279 clk_mgr_dce->base.dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq; in dce_clock_read_integrated_info()
280 if (clk_mgr_dce->base.dentist_vco_freq_khz == 0) { in dce_clock_read_integrated_info()
281 clk_mgr_dce->base.dentist_vco_freq_khz = bp->fw_info.smu_gpu_pll_output_freq; in dce_clock_read_integrated_info()
282 if (clk_mgr_dce->base.dentist_vco_freq_khz == 0) in dce_clock_read_integrated_info()
283 clk_mgr_dce->base in dce_clock_read_integrated_info()
438 struct clk_mgr *base = &clk_mgr->base; dce_clk_mgr_construct() local
[all...]
/kernel/linux/linux-5.10/drivers/regulator/
H A Dstm32-vrefbuf.c31 void __iomem *base; member
53 val = readl_relaxed(priv->base + STM32_VREFBUF_CSR); in stm32_vrefbuf_enable()
55 writel_relaxed(val, priv->base + STM32_VREFBUF_CSR); in stm32_vrefbuf_enable()
63 ret = readl_poll_timeout(priv->base + STM32_VREFBUF_CSR, val, in stm32_vrefbuf_enable()
67 val = readl_relaxed(priv->base + STM32_VREFBUF_CSR); in stm32_vrefbuf_enable()
69 writel_relaxed(val, priv->base + STM32_VREFBUF_CSR); in stm32_vrefbuf_enable()
90 val = readl_relaxed(priv->base + STM32_VREFBUF_CSR); in stm32_vrefbuf_disable()
92 writel_relaxed(val, priv->base + STM32_VREFBUF_CSR); in stm32_vrefbuf_disable()
111 ret = readl_relaxed(priv->base + STM32_VREFBUF_CSR) & STM32_ENVR; in stm32_vrefbuf_is_enabled()
132 val = readl_relaxed(priv->base in stm32_vrefbuf_set_voltage_sel()
[all...]
/kernel/linux/linux-6.6/drivers/watchdog/
H A Dmarvell_gti_wdt.c76 void __iomem *base; member
91 priv->base + GTI_CWD_INT); in gti_wdt_interrupt()
103 priv->base + GTI_CWD_POKE(priv->wdt_timer_idx)); in gti_wdt_ping()
120 priv->base + GTI_CWD_INT); in gti_wdt_start()
124 priv->base + GTI_CWD_INT_ENA_SET); in gti_wdt_start()
127 regval = readq(priv->base + GTI_CWD_WDOG(priv->wdt_timer_idx)); in gti_wdt_start()
129 writeq(regval, priv->base + GTI_CWD_WDOG(priv->wdt_timer_idx)); in gti_wdt_start()
141 priv->base + GTI_CWD_INT_ENA_CLR); in gti_wdt_stop()
144 regval = readq(priv->base + GTI_CWD_WDOG(priv->wdt_timer_idx)); in gti_wdt_stop()
146 writeq(regval, priv->base in gti_wdt_stop()
[all...]
/kernel/linux/linux-6.6/drivers/pinctrl/visconti/
H A Dpinctrl-common.c25 void __iomem *base; member
64 val = readl(priv->base + pin->pudsel_offset); in visconti_pin_config_set()
67 writel(val, priv->base + pin->pudsel_offset); in visconti_pin_config_set()
72 val = readl(priv->base + pin->pude_offset); in visconti_pin_config_set()
75 writel(val, priv->base + pin->pude_offset); in visconti_pin_config_set()
106 val = readl(priv->base + pin->dsel_offset); in visconti_pin_config_set()
109 writel(val, priv->base + pin->dsel_offset); in visconti_pin_config_set()
236 val = readl(priv->base + mux->offset); in visconti_set_mux()
239 writel(val, priv->base + mux->offset); in visconti_set_mux()
261 val = readl(priv->base in visconti_gpio_request_enable()
[all...]
/kernel/linux/linux-6.6/drivers/regulator/
H A Dstm32-vrefbuf.c31 void __iomem *base; member
51 val = readl_relaxed(priv->base + STM32_VREFBUF_CSR); in stm32_vrefbuf_enable()
53 writel_relaxed(val, priv->base + STM32_VREFBUF_CSR); in stm32_vrefbuf_enable()
61 ret = readl_poll_timeout(priv->base + STM32_VREFBUF_CSR, val, in stm32_vrefbuf_enable()
65 val = readl_relaxed(priv->base + STM32_VREFBUF_CSR); in stm32_vrefbuf_enable()
67 writel_relaxed(val, priv->base + STM32_VREFBUF_CSR); in stm32_vrefbuf_enable()
86 val = readl_relaxed(priv->base + STM32_VREFBUF_CSR); in stm32_vrefbuf_disable()
88 writel_relaxed(val, priv->base + STM32_VREFBUF_CSR); in stm32_vrefbuf_disable()
105 ret = readl_relaxed(priv->base + STM32_VREFBUF_CSR) & STM32_ENVR; in stm32_vrefbuf_is_enabled()
124 val = readl_relaxed(priv->base in stm32_vrefbuf_set_voltage_sel()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/
H A Drv1_clk_mgr.c45 bool dispclk_increase = new_clocks->dispclk_khz > clk_mgr->base.clks.dispclk_khz; in rv1_determine_dppclk_threshold()
47 bool cur_dpp_div = clk_mgr->base.clks.dispclk_khz > clk_mgr->base.clks.dppclk_khz; in rv1_determine_dppclk_threshold()
77 if (clk_mgr->base.clks.dispclk_khz <= disp_clk_threshold) in rv1_determine_dppclk_threshold()
185 clk_mgr->base.clks.dispclk_khz = new_clocks->dispclk_khz; in ramp_up_dispclk_with_dpp()
186 clk_mgr->base.clks.dppclk_khz = new_clocks->dppclk_khz; in ramp_up_dispclk_with_dpp()
187 clk_mgr->base.clks.max_supported_dppclk_khz = new_clocks->max_supported_dppclk_khz; in ramp_up_dispclk_with_dpp()
324 clk_mgr->base.ctx = ctx; in rv1_clk_mgr_construct()
326 clk_mgr->base.funcs = &rv1_clk_funcs; in rv1_clk_mgr_construct()
334 clk_mgr->base in rv1_clk_mgr_construct()
[all...]
/kernel/linux/linux-6.6/drivers/crypto/amlogic/
H A Damlogic-gxl-core.c33 p = readl(mc->base + ((0x04 + flow) << 2)); in meson_irq_handler()
35 writel_relaxed(0xF, mc->base + ((0x4 + flow) << 2)); in meson_irq_handler()
52 .alg.skcipher.base = {
53 .base = {
81 .alg.skcipher.base = {
82 .base = {
125 mc_algs[i].alg.skcipher.base.base.cra_driver_name, in meson_debugfs_show()
126 mc_algs[i].alg.skcipher.base.base in meson_debugfs_show()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn314/
H A Ddcn314_dio_stream_encoder.c37 enc1->base.ctx->logger
50 enc1->base.ctx
107 cntl.engine_id = enc1->base.id; in enc314_stream_encoder_dvi_set_stream_attribute()
114 if (enc1->base.bp->funcs->encoder_control( in enc314_stream_encoder_dvi_set_stream_attribute()
115 enc1->base.bp, &cntl) != BP_RESULT_OK) in enc314_stream_encoder_dvi_set_stream_attribute()
148 cntl.engine_id = enc1->base.id; in enc314_stream_encoder_hdmi_set_stream_attribute()
154 if (enc1->base.bp->funcs->encoder_control( in enc314_stream_encoder_hdmi_set_stream_attribute()
155 enc1->base.bp, &cntl) != BP_RESULT_OK) in enc314_stream_encoder_hdmi_set_stream_attribute()
485 enc1->base.funcs = &dcn314_str_enc_funcs; in dcn314_dio_stream_encoder_construct()
486 enc1->base in dcn314_dio_stream_encoder_construct()
[all...]
/kernel/linux/linux-6.6/drivers/crypto/hisilicon/trng/
H A Dtrng.c51 void __iomem *base; member
79 writel(val, trng->base + SW_DRBG_SEED(seed_reg)); in hisi_trng_set_seed()
97 writel(0x0, trng->base + SW_DRBG_BLOCKS); in hisi_trng_seed()
101 trng->base + SW_DRBG_BLOCKS); in hisi_trng_seed()
102 writel(0x1, trng->base + SW_DRBG_INIT); in hisi_trng_seed()
104 ret = readl_relaxed_poll_timeout(trng->base + SW_DRBG_STATUS, in hisi_trng_seed()
130 ret = readl_relaxed_poll_timeout(trng->base + SW_DRBG_STATUS, in hisi_trng_generate()
138 data[i] = readl(trng->base + SW_DRBG_DATA(i)); in hisi_trng_generate()
148 writel(0x1, trng->base + SW_DRBG_GEN); in hisi_trng_generate()
193 ret = readl_poll_timeout(trng->base in hisi_trng_read()
[all...]
/kernel/linux/linux-6.6/arch/x86/crypto/
H A Daria_aesni_avx2_glue.c85 return aria_set_key(&tfm->base, key, keylen); in aria_avx2_set_key()
168 .base.cra_name = "__ecb(aria)",
169 .base.cra_driver_name = "__ecb-aria-avx2",
170 .base.cra_priority = 500,
171 .base.cra_flags = CRYPTO_ALG_INTERNAL,
172 .base.cra_blocksize = ARIA_BLOCK_SIZE,
173 .base.cra_ctxsize = sizeof(struct aria_ctx),
174 .base.cra_module = THIS_MODULE,
181 .base.cra_name = "__ctr(aria)",
182 .base
[all...]
/kernel/linux/linux-6.6/drivers/media/platform/qcom/camss/
H A Dcamss-csid-4-7.c225 writel_relaxed(val, csid->base + CAMSS_CSID_TG_VC_CFG); in csid_configure_stream()
230 writel_relaxed(val, csid->base + CAMSS_CSID_TG_DT_n_CGG_0(0)); in csid_configure_stream()
234 writel_relaxed(val, csid->base + CAMSS_CSID_TG_DT_n_CGG_1(0)); in csid_configure_stream()
238 writel_relaxed(val, csid->base + CAMSS_CSID_TG_DT_n_CGG_2(0)); in csid_configure_stream()
249 writel_relaxed(val, csid->base + CAMSS_CSID_CORE_CTRL_0); in csid_configure_stream()
254 writel_relaxed(val, csid->base + CAMSS_CSID_CORE_CTRL_1); in csid_configure_stream()
261 val = readl_relaxed(csid->base + CAMSS_CSID_CID_LUT_VC_n(vc)); in csid_configure_stream()
264 writel_relaxed(val, csid->base + CAMSS_CSID_CID_LUT_VC_n(vc)); in csid_configure_stream()
280 writel_relaxed(val, csid->base + CAMSS_CSID_CID_n_CFG(cid)); in csid_configure_stream()
284 writel_relaxed(val, csid->base in csid_configure_stream()
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/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/dispnv50/
H A Dheadc57d.c33 struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; in headc57d_or()
34 const int i = head->base.index; in headc57d_or()
68 struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; in headc57d_procamp()
69 const int i = head->base.index; in headc57d_procamp()
86 struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; in headc57d_olut_clr()
87 const int i = head->base.index; in headc57d_olut_clr()
100 struct nvif_push *push = nv50_disp(head->base in headc57d_olut_set()
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