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/third_party/elfutils/tests/
H A Drun-allregs.sh142 58: %fs.base (fs.base), address 64 bits
143 59: %gs.base (gs.base), address 64 bits
2792 58: %fs.base (fs.base), address 64 bits
2793 59: %gs.base (gs.base), address 64 bits
/third_party/ntfs-3g/ntfsprogs/
H A Dplaylog.c1104 u16 base; in expand_resident() local
1120 base = 24 + 2*attr->name_length; in expand_resident()
1121 resize = ((base + length - 1) | 7) in expand_resident()
1122 - ((base + oldlength - 1) | 7); in expand_resident()
1413 u16 base; in shrink_resident() local
1431 base = 24 + 2*attr->name_length; in shrink_resident()
1432 resize = ((base + length - 1) | 7) in shrink_resident()
1433 - ((base + oldlength - 1) | 7); in shrink_resident()
/third_party/node/deps/v8/src/compiler/backend/s390/
H A Dcode-generator-s390.cc2377 // Add directly to the base register in case the index register (rx) is in AssembleArchInstruction()
2388 Register base = i.InputRegister(0); in AssembleArchInstruction() local
2392 __ la(r1, MemOperand(base, index)); in AssembleArchInstruction()
2403 Register base = i.InputRegister(0); in AssembleArchInstruction() local
2408 __ la(r1, MemOperand(base, index)); in AssembleArchInstruction()
2428 Register base = i.InputRegister(0); in AssembleArchInstruction() local
2434 __ lay(r1, MemOperand(base, index)); in AssembleArchInstruction()
2541 Register base = i.InputRegister(0); in AssembleArchInstruction() local
2548 __ la(r1, MemOperand(base, index)); in AssembleArchInstruction()
/third_party/mesa3d/src/gallium/auxiliary/gallivm/
H A Dlp_bld_sample_soa.c4822 unsigned base, unsigned range) in lp_build_sample_array_init_soa()
4826 switch_info->base = base; in lp_build_sample_array_init_soa()
4839 range - base); in lp_build_sample_array_init_soa()
4911 unsigned base, unsigned range) in lp_build_image_op_switch_soa()
4915 switch_info->base = base; in lp_build_image_op_switch_soa()
4928 switch_info->merge_ref, range - base); in lp_build_image_op_switch_soa()
4818 lp_build_sample_array_init_soa(struct lp_build_sample_array_switch *switch_info, struct gallivm_state *gallivm, const struct lp_sampler_params *params, LLVMValueRef idx, unsigned base, unsigned range) lp_build_sample_array_init_soa() argument
4907 lp_build_image_op_switch_soa(struct lp_build_img_op_array_switch *switch_info, struct gallivm_state *gallivm, const struct lp_img_params *params, LLVMValueRef idx, unsigned base, unsigned range) lp_build_image_op_switch_soa() argument
/third_party/mesa3d/src/gallium/frontends/nine/
H A Dnine_state.c721 unsigned nr_samples = rt0->base.info.nr_samples; in update_framebuffer()
744 nr_samples = context->ds->base.info.nr_samples; in update_framebuffer()
752 rt->base.info.nr_samples == nr_samples) { in update_framebuffer()
766 context->ds->base.info.nr_samples == nr_samples) { in update_framebuffer()
1335 src = source->base.resource; in NineDevice9_ResolveZ()
1505 if (tex && tex->base.resource) { in nine_context_set_texture()
1510 type = tex->base.type; in nine_context_set_texture()
1512 res = tex->base.resource; in nine_context_set_texture()
/third_party/rust/crates/libc/src/
H A Dpsp.rs1647 pub base: SceKernelSysClock,
2008 pub base: UtilityDialogCommon,
2029 pub base: UtilityDialogCommon,
2045 pub base: UtilityDialogCommon,
2086 pub base: UtilityDialogCommon,
2323 pub base: UtilityDialogCommon,
2349 pub base: UtilityDialogCommon,
3150 pub fn sceKernelGetVTimerBase(uid: SceUid, base: *mut SceKernelSysClock) -> i32; in sceKernelGetVTimerBase()
/third_party/skia/third_party/externals/swiftshader/src/Reactor/
H A DReactor.cpp4373 RValue<Float4> MaskedLoad(RValue<Pointer<Float4>> base, RValue<Int4> mask, unsigned int alignment, bool zeroMaskedLanes /* = false */)
4375 return RValue<Float4>(Nucleus::createMaskedLoad(base.value(), Float::type(), mask.value(), alignment, zeroMaskedLanes));
4378 RValue<Int4> MaskedLoad(RValue<Pointer<Int4>> base, RValue<Int4> mask, unsigned int alignment, bool zeroMaskedLanes /* = false */)
4380 return RValue<Int4>(Nucleus::createMaskedLoad(base.value(), Int::type(), mask.value(), alignment, zeroMaskedLanes));
4383 void MaskedStore(RValue<Pointer<Float4>> base, RValue<Float4> val, RValue<Int4> mask, unsigned int alignment)
4385 Nucleus::createMaskedStore(base.value(), val.value(), mask.value(), alignment);
4388 void MaskedStore(RValue<Pointer<Int4>> base, RValue<Int4> val, RValue<Int4> mask, unsigned int alignment)
4390 Nucleus::createMaskedStore(base.value(), val.value(), mask.value(), alignment);
H A DReactor.hpp2532 [[deprecated]] RValue<Float4> MaskedLoad(RValue<Pointer<Float4>> base, RValue<Int4> mask, unsigned int alignment, bool zeroMaskedLanes = false);
2533 [[deprecated]] RValue<Int4> MaskedLoad(RValue<Pointer<Int4>> base, RValue<Int4> mask, unsigned int alignment, bool zeroMaskedLanes = false);
2534 [[deprecated]] void MaskedStore(RValue<Pointer<Float4>> base, RValue<Float4> val, RValue<Int4> mask, unsigned int alignment);
2535 [[deprecated]] void MaskedStore(RValue<Pointer<Int4>> base, RValue<Int4> val, RValue<Int4> mask, unsigned int alignment);
2537 RValue<Float4> Gather(RValue<Pointer<Float>> base, RValue<Int4> offsets, RValue<Int4> mask, unsigned int alignment, bool zeroMaskedLanes = false);
2538 RValue<Int4> Gather(RValue<Pointer<Int>> base, RValue<Int4> offsets, RValue<Int4> mask, unsigned int alignment, bool zeroMaskedLanes = false);
2539 void Scatter(RValue<Pointer<Float>> base, RValue<Float4> val, RValue<Int4> offsets, RValue<Int4> mask, unsigned int alignment);
2540 void Scatter(RValue<Pointer<Int>> base, RValue<Int4> val, RValue<Int4> offsets, RValue<Int4> mask, unsigned int alignment);
2650 // Type of base class
2662 // Hide base implementation
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/third_party/skia/third_party/externals/freetype/src/truetype/
H A Dttinterp.c138 FT_ASSERT( coderange->base ); in TT_Goto_CodeRange()
146 exec->code = coderange->base; in TT_Goto_CodeRange()
165 * base ::
166 * The new code base.
178 void* base, in TT_Set_CodeRange()
183 exec->codeRangeTable[range - 1].base = (FT_Byte*)base; in TT_Set_CodeRange()
210 exec->codeRangeTable[range - 1].base = NULL; in TT_Clear_CodeRange()
302 * The address of the buffer base pointer.
1660 if ( !range->base ) /* invali in Ins_Goto_CodeRange()
176 TT_Set_CodeRange( TT_ExecContext exec, FT_Int range, void* base, FT_Long length ) TT_Set_CodeRange() argument
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/third_party/mesa3d/src/compiler/spirv/
H A Dspirv_to_nir.c819 vtn_fail("Invalid base type"); in vtn_types_compatible()
1462 struct vtn_type *base = vtn_get_type(b, w[2]); in vtn_handle_type() local
1465 vtn_fail_if(base->base_type != vtn_base_type_scalar, in vtn_handle_type()
1471 val->type->type = glsl_vector_type(glsl_get_base_type(base->type), elems); in vtn_handle_type()
1474 ? 4 : glsl_get_bit_size(base->type) / 8; in vtn_handle_type()
1475 val->type->array_element = base; in vtn_handle_type()
1480 struct vtn_type *base = vtn_get_type(b, w[2]); in vtn_handle_type() local
1483 vtn_fail_if(base->base_type != vtn_base_type_vector, in vtn_handle_type()
1489 val->type->type = glsl_matrix_type(glsl_get_base_type(base->type), in vtn_handle_type()
1490 glsl_get_vector_elements(base in vtn_handle_type()
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/third_party/nghttp2/lib/
H A Dnghttp2_session.c1379 done to simplify code base, but ideally we should retain old in nghttp2_session_open_stream()
3644 session, frame, nv->name->base, nv->name->len, nv->value->base, in session_call_on_header()
3667 session, frame, nv->name->base, nv->name->len, nv->value->base, in session_call_on_invalid_header()
3955 nv.name->base, (int)nv.value->len, nv.value->base); in inflate_header_block()
3962 nv.name->base, (int)nv.value->len, nv.value->base); in inflate_header_block()
3973 nv.name->base, (in in inflate_header_block()
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/third_party/node/deps/nghttp2/lib/
H A Dnghttp2_session.c1374 done to simplify code base, but ideally we should retain old in nghttp2_session_open_stream()
3639 session, frame, nv->name->base, nv->name->len, nv->value->base, in session_call_on_header()
3662 session, frame, nv->name->base, nv->name->len, nv->value->base, in session_call_on_invalid_header()
3950 nv.name->base, (int)nv.value->len, nv.value->base); in inflate_header_block()
3957 nv.name->base, (int)nv.value->len, nv.value->base); in inflate_header_block()
3968 nv.name->base, (in in inflate_header_block()
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/third_party/node/deps/v8/src/codegen/arm64/
H A Dassembler-arm64.cc33 #include "src/base/bits.h"
34 #include "src/base/cpu.h"
35 #include "src/base/small-vector.h"
104 base::CPU cpu; in ProbeImpl()
133 int index = base::bits::CountTrailingZeros(list_); in PopLowestIndex()
434 DCHECK(m >= kInstrSize && base::bits::IsPowerOfTwo(m)); in Align()
1231 if (xdata_encoder_ && rt == x29 && rt2 == lr && dst.base().IsSP()) { in stp()
1251 Instr memop = op | Rt(rt) | Rt2(rt2) | RnSP(addr.base()) | in LoadStorePair()
1259 DCHECK_NE(rt, addr.base()); in LoadStorePair()
1260 DCHECK_NE(rt2, addr.base()); in LoadStorePair()
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/third_party/skia/third_party/externals/angle2/src/tests/gl_tests/
H A DTextureTest.cpp3759 // Copy from mip 1 of the source. In the GL backend this internally sets the base level to mip in TEST_P()
3768 // This test case changes the base level of a texture that's attached to a framebuffer, clears every
3770 // https://www.khronos.org/registry/webgl/sdk/tests/conformance2/rendering/framebuffer-texture-changing-base-level.html
3803 // Clear each level of the texture using an FBO. Change the base level to match the level used in TEST_P()
3839 // Test that changing the base level of a texture after redefining a level outside the mip-chain
3900 // Test that changing the base level of a texture multiple times preserves the data.
3926 for (uint32_t base = 0; base < kMipCount; ++base) in testPingPongBaseLevel()
3928 glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_BASE_LEVEL, base); in testPingPongBaseLevel()
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/third_party/python/Modules/
H A D_testcapimodule.c3628 PyObject *base = NULL; in make_exception_with_doc() local
3631 static char *kwlist[] = {"name", "doc", "base", "dict", NULL}; in make_exception_with_doc()
3635 &name, &doc, &base, &dict)) in make_exception_with_doc()
3638 return PyErr_NewExceptionWithDoc(name, doc, base, dict); in make_exception_with_doc()
5696 int base; in pynumber_tobase() local
5698 &obj, &base)) { in pynumber_tobase()
5701 return PyNumber_ToBase(obj, base); in pynumber_tobase()
7365 MethodDescriptorObject base; member
7373 op->base.vectorcall = NULL; in MethodDescriptor2_new()
7531 HeapCTypeObject base; member
7572 HeapCTypeObject base; global() member
7616 PyTypeObject *base = (PyTypeObject *)PyType_GetSlot(Py_TYPE(self), Py_tp_base); heapctypesubclasswithfinalizer_init() local
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/kernel/linux/linux-5.10/arch/mips/include/asm/octeon/
H A Dcvmx-pip-defs.h1692 uint64_t base:8; member
1698 uint64_t base:8;
1743 uint64_t base:8; member
1749 uint64_t base:8;
/kernel/linux/linux-5.10/drivers/base/power/
H A Ddomain.c3 * drivers/base/power/domain.c - Common code related to device power domains.
682 dev = gpd_data->base.dev; in genpd_dev_pm_qos_notifier()
1430 gpd_data->base.dev = dev; in genpd_alloc_dev_data()
1442 dev->power.subsys_data->domain_data = &gpd_data->base; in genpd_alloc_dev_data()
1547 list_add_tail(&gpd_data->base.list_node, &genpd->dev_list); in genpd_add_device()
/kernel/linux/linux-5.10/drivers/ata/
H A Dsata_nv.c2326 void __iomem *base; in nv_init_one() local
2369 base = host->iomap[NV_MMIO_BAR]; in nv_init_one()
2370 host->ports[0]->ioaddr.scr_addr = base + NV_PORT0_SCR_REG_OFFSET; in nv_init_one()
2371 host->ports[1]->ioaddr.scr_addr = base + NV_PORT1_SCR_REG_OFFSET; in nv_init_one()
/kernel/linux/linux-5.10/arch/powerpc/xmon/
H A Dxmon.c1799 unsigned long base; in prregs() local
1802 if (scanhex(&base)) { in prregs()
1806 regs = *(struct pt_regs *)base; in prregs()
1812 base); in prregs()
/kernel/linux/linux-6.6/arch/mips/include/asm/octeon/
H A Dcvmx-pip-defs.h1692 uint64_t base:8; member
1698 uint64_t base:8;
1743 uint64_t base:8; member
1749 uint64_t base:8;
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/
H A Di915_perf.c1634 const u32 base = stream->engine->mmio_base; in alloc_noa_wait() local
1635 #define CS_GPR(x) GEN8_RING_CS_GPR(base, x) in alloc_noa_wait()
1692 *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(base)); in alloc_noa_wait()
1710 *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(base)); in alloc_noa_wait()
/kernel/linux/linux-5.10/drivers/net/wireless/broadcom/b43legacy/
H A Dradio.c1868 u16 base; in b43legacy_radio_set_txpower_a() local
1879 base = b43legacy_get_txgain_base_band(txpower); in b43legacy_radio_set_txpower_a()
1880 base &= 0x000F; in b43legacy_radio_set_txpower_a()
1881 b43legacy_phy_write(dev, 0x0017, base | 0x0020); in b43legacy_radio_set_txpower_a()
/kernel/linux/linux-5.10/drivers/scsi/
H A Desp_scsi.c529 u32 base, end; in esp_dma_length_limit() local
543 base = dma_addr & ((1U << 24) - 1U); in esp_dma_length_limit()
544 end = base + dma_len; in esp_dma_length_limit()
547 dma_len = end - base; in esp_dma_length_limit()
/kernel/linux/linux-5.10/drivers/tty/
H A Dtty_io.c322 dev_t base = MKDEV(p->major, p->minor_start); in get_tty_driver() local
323 if (device < base || device >= base + p->num) in get_tty_driver()
325 *index = device - base; in get_tty_driver()
/kernel/linux/linux-6.6/drivers/net/dsa/ocelot/
H A Dfelix_vsc9959.c521 /* Addresses are relative to the PCI device's base address */
1628 static int vsc9959_qos_query_caps(struct tc_query_caps_base *base) in vsc9959_qos_query_caps() argument
1630 switch (base->type) { in vsc9959_qos_query_caps()
1632 struct tc_mqprio_caps *caps = base->caps; in vsc9959_qos_query_caps()
1639 struct tc_taprio_caps *caps = base->caps; in vsc9959_qos_query_caps()

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