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/kernel/linux/linux-5.10/drivers/infiniband/sw/rxe/
H A Drxe_verbs.c546 wr->wr.reg.access = reg_wr(ibwr)->access; in init_send_wr()
866 static struct ib_mr *rxe_get_dma_mr(struct ib_pd *ibpd, int access) in rxe_get_dma_mr() argument
878 rxe_mem_init_dma(pd, access, mr); in rxe_get_dma_mr()
887 int access, struct ib_udata *udata) in rxe_reg_user_mr()
905 access, udata, mr); in rxe_reg_user_mr()
883 rxe_reg_user_mr(struct ib_pd *ibpd, u64 start, u64 length, u64 iova, int access, struct ib_udata *udata) rxe_reg_user_mr() argument
/kernel/linux/linux-5.10/drivers/infiniband/hw/hns/
H A Dhns_roce_mr.c70 u32 pd, u64 iova, u64 size, u32 access) in alloc_mr_key()
88 mr->access = access; /* MR access permit */ in alloc_mr_key()
114 int access) in alloc_mr_pbl()
128 buf_attr.user_access = access; in alloc_mr_pbl()
388 mr->access = mr_access_flags; in hns_roce_rereg_user_mr()
69 alloc_mr_key(struct hns_roce_dev *hr_dev, struct hns_roce_mr *mr, u32 pd, u64 iova, u64 size, u32 access) alloc_mr_key() argument
112 alloc_mr_pbl(struct hns_roce_dev *hr_dev, struct hns_roce_mr *mr, size_t length, struct ib_udata *udata, u64 start, int access) alloc_mr_pbl() argument
/kernel/linux/linux-5.10/include/linux/
H A Dnfs_xdr.h459 u32 access; member
890 __u32 access; member
951 __u32 access; member
989 u32 access; member
997 u32 access; member
1733 int (*access) (struct inode *, struct nfs_access_entry *); member
/kernel/linux/linux-6.6/include/linux/
H A Dnfs_xdr.h462 u32 access; member
914 __u32 access; member
975 __u32 access; member
1013 u32 access; member
1021 u32 access; member
1760 int (*access) (struct inode *, struct nfs_access_entry *, const struct cred *); member
/kernel/linux/linux-6.6/drivers/char/tpm/
H A Dtpm_tis_core.c126 /* Before we attempt to access the TPM we must see that the valid bit is set.
138 u8 access; in wait_startup() local
140 rc = tpm_tis_read8(priv, TPM_ACCESS(l), &access); in wait_startup()
144 if (access & TPM_ACCESS_VALID) in wait_startup()
155 u8 access; in check_locality() local
157 rc = tpm_tis_read8(priv, TPM_ACCESS(l), &access); in check_locality()
161 if ((access & (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID in check_locality()
/third_party/alsa-lib/src/pcm/
H A Dpcm_ioplug.c292 /* access, format */ in snd_pcm_ioplug_hw_refine()
436 INTERNAL(snd_pcm_hw_params_get_access)(params, &io->data->access); in snd_pcm_ioplug_hw_params()
446 INTERNAL(snd_pcm_hw_params_get_access)(params, &io->data->access); in snd_pcm_ioplug_hw_params()
713 pcm->access != SND_PCM_ACCESS_RW_INTERLEAVED && in snd_pcm_ioplug_mmap_begin_capture()
714 pcm->access != SND_PCM_ACCESS_RW_NONINTERLEAVED) { in snd_pcm_ioplug_mmap_begin_capture()
737 pcm->access != SND_PCM_ACCESS_RW_INTERLEAVED && in snd_pcm_ioplug_mmap_commit()
738 pcm->access != SND_PCM_ACCESS_RW_NONINTERLEAVED) { in snd_pcm_ioplug_mmap_commit()
/third_party/mesa3d/src/gallium/frontends/lavapipe/
H A Dlvp_pipeline.c146 pipeline->access[nir->info.stage].images_read |= mask; in set_image_access()
148 pipeline->access[nir->info.stage].images_written |= mask; in set_image_access()
179 pipeline->access[nir->info.stage].buffers_written |= mask; in set_buffer_access()
793 memcpy(&pipeline->access, &p->access, sizeof(p->access)); in lvp_graphics_pipeline_init()
/third_party/vk-gl-cts/external/vulkancts/modules/vulkan/api/
H A DvktApiBufferViewAccessTests.cpp573 void populateSourceBuffer (const tcu::PixelBufferAccess& access, deUint32 bufferNdx);
634 void BufferViewAllFormatsTestInstance::populateSourceBuffer (const tcu::PixelBufferAccess& access, deUint32 bufferNdx) in populateSourceBuffer() argument
636 DE_ASSERT(access.getHeight() == 1); in populateSourceBuffer()
637 DE_ASSERT(access.getDepth() == 1); in populateSourceBuffer()
639 const deInt32 width = access.getWidth(); in populateSourceBuffer()
655 access.setPixel(tcu::IVec4(red, green, blue, 255), x, 0, 0); in populateSourceBuffer()
1162 de::MovePtr<tcu::TestCaseGroup> bufferViewTests (new tcu::TestCaseGroup(testCtx, "access")); in createBufferViewAccessTests()
/third_party/vk-gl-cts/external/vulkancts/modules_no_buildgn/vulkan/api/
H A DvktApiBufferViewAccessTests.cpp571 void populateSourceBuffer (const tcu::PixelBufferAccess& access, deUint32 bufferNdx);
624 void BufferViewAllFormatsTestInstance::populateSourceBuffer (const tcu::PixelBufferAccess& access, deUint32 bufferNdx) in populateSourceBuffer() argument
626 DE_ASSERT(access.getHeight() == 1); in populateSourceBuffer()
627 DE_ASSERT(access.getDepth() == 1); in populateSourceBuffer()
629 const deInt32 width = access.getWidth(); in populateSourceBuffer()
645 access.setPixel(tcu::IVec4(red, green, blue, 255), x, 0, 0); in populateSourceBuffer()
1110 de::MovePtr<tcu::TestCaseGroup> bufferViewTests (new tcu::TestCaseGroup(testCtx, "access", "BufferView Access Tests")); in createBufferViewAccessTests()
/base/hiviewdfx/hitrace/interfaces/native/innerkits/src/
H A Dhitrace_dump.cpp173 if (access((debugfsPath + "trace_marker").c_str(), F_OK) != -1) { in IsTraceMounted()
177 if (access((tracefsPath + "trace_marker").c_str(), F_OK) != -1) { in IsTraceMounted()
252 if (access((g_traceRootPath + filename).c_str(), W_OK) < 0) { in WriteStrToFile()
253 HILOG_ERROR(LOG_CORE, "WriteStrToFile: Failed to access %{public}s, errno(%{public}d).", in WriteStrToFile()
476 if (access(outputFile.c_str(), F_OK) != 0) { in CheckFileExist()
478 HILOG_INFO(LOG_CORE, "CheckFileExist access file:%{public}s failed, errno: %{public}d.", in CheckFileExist()
678 if (access(savedEventsFormatPath.c_str(), F_OK) != -1) { in WriteEventsFormat()
742 if (access(srcPath.c_str(), R_OK) != -1) { in WriteEventsFormat()
836 if (access(outPath.c_str(), F_OK) == 0) { in GenerateNewFile()
894 HILOG_INFO(LOG_CORE, "DumpTraceLoop access fil in DumpTraceLoop()
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/base/web/webview/interfaces/kits/napi/webviewcontroller/
H A Dwebview_controller.cpp209 bool access = false; in AccessForward() local
212 access = nweb_ptr->IsNavigateForwardAllowed(); in AccessForward()
216 return access; in AccessForward()
221 bool access = false; in AccessBackward() local
224 access = nweb_ptr->IsNavigatebackwardAllowed(); in AccessBackward()
226 return access; in AccessBackward()
231 bool access = false; in AccessStep() local
234 access = nweb_ptr->CanNavigateBackOrForward(step); in AccessStep()
236 return access; in AccessStep()
/foundation/bundlemanager/bundle_framework/services/bundlemgr/test/unittest/bms_bundle_installer_test/
H A Dbms_multiple_installer_test.cpp227 int bundleCodeExist = access(BUNDLE_CODE_DIR.c_str(), F_OK); in CheckFileExist()
230 int bundleDataExist = access(BUNDLE_DATA_DIR.c_str(), F_OK); in CheckFileExist()
236 int bundleCodeExist = access(BUNDLE_CODE_DIR.c_str(), F_OK); in CheckFileNonExist()
239 int bundleDataExist = access(BUNDLE_DATA_DIR.c_str(), F_OK); in CheckFileNonExist()
247 auto moduleDataExist = access((BUNDLE_DATA_DIR + "/" + BUNDLE_DATA_DIR_PAGENAME[i]).c_str(), F_OK); in CheckModuleFileExist()
250 int codeDirExist = access((BUNDLE_CODE_DIR).c_str(), F_OK); in CheckModuleFileExist()
256 int moduleCodeExist = access((BUNDLE_CODE_DIR + "/" + packageName).c_str(), F_OK); in CheckModuleFileNonExist()
257 int moduleDataExist = access((BUNDLE_DATA_DIR + "/" + packageName).c_str(), F_OK); in CheckModuleFileNonExist()
335 int ret = access(hapPath.c_str(), F_OK); in HWTEST_F()
/kernel/linux/linux-5.10/drivers/infiniband/hw/mlx5/
H A Dwr.c375 u32 key, int access) in set_reg_mkey_seg()
387 seg->flags = get_umr_flags(access) | mr->access_mode; in set_reg_mkey_seg()
791 unlikely(wr->access & IB_ACCESS_REMOTE_ATOMIC) || in set_pi_umr_wr()
814 set_sig_mkey_segment(*seg, wr->mr, wr->access, xlt_size, region_len, in set_pi_umr_wr()
866 bool atomic = wr->access & IB_ACCESS_REMOTE_ATOMIC; in set_reg_wr()
869 /* Matches access in mlx5_set_umr_free_mkey() */ in set_reg_wr()
870 if (!mlx5_ib_can_reconfig_with_umr(dev, 0, wr->access)) { in set_reg_wr()
873 "Fast update for MR access flags is not possible\n"); in set_reg_wr()
893 set_reg_mkey_seg(*seg, mr, wr->key, wr->access); in set_reg_wr()
1089 reg_pi_wr.access in handle_reg_mr_integrity()
373 set_reg_mkey_seg(struct mlx5_mkey_seg *seg, struct mlx5_ib_mr *mr, u32 key, int access) set_reg_mkey_seg() argument
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/kernel/linux/linux-5.10/drivers/net/ethernet/chelsio/cxgb4vf/
H A Dt4vf_hw.c84 * @access: the time (ms) needed to access the Firmware Mailbox
88 int size, int access, int execute) in t4vf_record_mbox()
104 entry->access = access; in t4vf_record_mbox()
135 u16 access = 0, execute = 0; in t4vf_wr_mbox_core() local
160 /* Queue ourselves onto the mailbox access list. When our entry is at in t4vf_wr_mbox_core()
161 * the front of the list, we have rights to access the mailbox. So we in t4vf_wr_mbox_core()
175 * mailbox access list but this is a start. We very rearely in t4vf_wr_mbox_core()
176 * contend on access t in t4vf_wr_mbox_core()
87 t4vf_record_mbox(struct adapter *adapter, const __be64 *cmd, int size, int access, int execute) t4vf_record_mbox() argument
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/kernel/linux/linux-5.10/drivers/memory/
H A Domap-gpmc.c505 pr_info("gpmc cs%i access configuration:\n", cs); in gpmc_cs_show_timings()
559 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 16, 20, "access-ns"); in gpmc_cs_show_timings()
561 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 24, 27, "page-burst-access-ns"); in gpmc_cs_show_timings()
574 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 24, 28, "wr-access-ns"); in gpmc_cs_show_timings()
781 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 16, 20, 0, t->access, in gpmc_cs_set_timings()
782 GPMC_CD_FCLK, "access"); in gpmc_cs_set_timings()
1517 /* access */ in gpmc_calc_sync_read_timings()
1520 * access = clk_activation + round to sync clk ? in gpmc_calc_sync_read_timings()
1527 gpmc_t->access = gpmc_round_ps_to_ticks(temp); in gpmc_calc_sync_read_timings()
1529 gpmc_t->oe_off = gpmc_t->access in gpmc_calc_sync_read_timings()
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/kernel/linux/linux-6.6/drivers/net/ethernet/chelsio/cxgb4vf/
H A Dt4vf_hw.c85 * @access: the time (ms) needed to access the Firmware Mailbox
89 int size, int access, int execute) in t4vf_record_mbox()
105 entry->access = access; in t4vf_record_mbox()
136 u16 access = 0, execute = 0; in t4vf_wr_mbox_core() local
161 /* Queue ourselves onto the mailbox access list. When our entry is at in t4vf_wr_mbox_core()
162 * the front of the list, we have rights to access the mailbox. So we in t4vf_wr_mbox_core()
176 * mailbox access list but this is a start. We very rearely in t4vf_wr_mbox_core()
177 * contend on access t in t4vf_wr_mbox_core()
88 t4vf_record_mbox(struct adapter *adapter, const __be64 *cmd, int size, int access, int execute) t4vf_record_mbox() argument
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/kernel/linux/linux-6.6/drivers/infiniband/hw/erdma/
H A Derdma_verbs.c160 FIELD_PREP(ERDMA_CMD_REGMR_RIGHT_MASK, mr->access); in regmr_cmd()
755 u64 start, u64 len, int access, u64 virt, in get_mtt_entries()
760 mem->umem = ib_umem_get(&dev->ibdev, start, len, access); in get_mtt_entries()
1042 mr->access = ERDMA_MR_ACC_LR | to_erdma_access_flags(acc); in erdma_get_dma_mr()
1087 mr->access = ERDMA_MR_ACC_LR | ERDMA_MR_ACC_LW | ERDMA_MR_ACC_RR | in erdma_ib_alloc_mr()
1145 u64 virt, int access, struct ib_udata *udata) in erdma_reg_user_mr()
1159 ret = get_mtt_entries(dev, &mr->mem, start, len, access, virt, in erdma_reg_user_mr()
1172 mr->access = ERDMA_MR_ACC_LR | to_erdma_access_flags(access); in erdma_reg_user_mr()
754 get_mtt_entries(struct erdma_dev *dev, struct erdma_mem *mem, u64 start, u64 len, int access, u64 virt, unsigned long req_page_size, bool force_continuous) get_mtt_entries() argument
1144 erdma_reg_user_mr(struct ib_pd *ibpd, u64 start, u64 len, u64 virt, int access, struct ib_udata *udata) erdma_reg_user_mr() argument
/kernel/linux/linux-6.6/drivers/infiniband/hw/mlx5/
H A Dwr.c191 u32 key, int access) in set_reg_mkey_seg()
203 seg->flags = get_umr_flags(access) | mr->access_mode; in set_reg_mkey_seg()
570 unlikely(wr->access & IB_ACCESS_REMOTE_ATOMIC) || in set_pi_umr_wr()
593 set_sig_mkey_segment(*seg, wr->mr, wr->access, xlt_size, region_len, in set_pi_umr_wr()
645 bool atomic = wr->access & IB_ACCESS_REMOTE_ATOMIC; in set_reg_wr()
648 /* Matches access in mlx5_set_umr_free_mkey(). in set_reg_wr()
652 if (!mlx5r_umr_can_reconfig(dev, 0, wr->access)) { in set_reg_wr()
655 "Fast update for MR access flags is not possible\n"); in set_reg_wr()
675 set_reg_mkey_seg(*seg, mr, wr->key, wr->access); in set_reg_wr()
868 reg_pi_wr.access in handle_reg_mr_integrity()
189 set_reg_mkey_seg(struct mlx5_mkey_seg *seg, struct mlx5_ib_mr *mr, u32 key, int access) set_reg_mkey_seg() argument
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/third_party/node/deps/uv/src/win/
H A Dpipe.c202 HANDLE* pipeHandle_ptr, DWORD access, in uv__pipe_server()
211 access | FILE_FLAG_FIRST_PIPE_INSTANCE, in uv__pipe_server()
400 /* The server needs inbound (read) access too, otherwise CreateNamedPipe() in uv__create_stdio_pipe_pair()
2276 FILE_ACCESS_INFORMATION access; in uv_pipe_open() local
2310 * just query the access flags and set the stream flags accordingly. in uv_pipe_open()
2314 &access, in uv_pipe_open()
2315 sizeof(access), in uv_pipe_open()
2321 if (!(access.AccessFlags & FILE_WRITE_DATA) || in uv_pipe_open()
2322 !(access.AccessFlags & FILE_READ_DATA)) { in uv_pipe_open()
2327 if (access in uv_pipe_open()
201 uv__pipe_server( HANDLE* pipeHandle_ptr, DWORD access, char* name, size_t nameSize, char* random) uv__pipe_server() argument
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/third_party/vk-gl-cts/modules/gles3/functional/
H A Des3fFragmentOutputTests.cpp502 void clearUndefined (const tcu::PixelBufferAccess& access, int numValidChannels) in clearUndefined() argument
504 for (int y = 0; y < access.getHeight(); y++) in clearUndefined()
505 for (int x = 0; x < access.getWidth(); x++) in clearUndefined()
507 switch (tcu::getTextureChannelClass(access.getFormat().type)) in clearUndefined()
511 const Vec4 srcPixel = access.getPixel(x, y); in clearUndefined()
517 access.setPixel(dstPixel, x, y); in clearUndefined()
526 const IVec4 bitDepth = tcu::getTextureFormatBitDepth(access.getFormat()); in clearUndefined()
527 const IVec4 srcPixel = access.getPixelInt(x, y); in clearUndefined()
533 access.setPixel(dstPixel, x, y); in clearUndefined()
/third_party/vk-gl-cts/framework/referencerenderer/
H A DrrFragmentOperations.cpp192 tcu::PixelBufferAccess access(depthBuffer.getFormat(), 1, 1, 1, &buffer); in executeDepthBoundsTest()
193 access.setPixDepth(minDepthBound, 0, 0, 0); in executeDepthBoundsTest()
194 minDepthBoundUint = access.getPixelUint(0, 0, 0).x(); in executeDepthBoundsTest()
199 tcu::PixelBufferAccess access(depthBuffer.getFormat(), 1, 1, 1, &buffer); in executeDepthBoundsTest()
200 access.setPixDepth(maxDepthBound, 0, 0, 0); in executeDepthBoundsTest()
201 maxDepthBoundUint = access.getPixelUint(0, 0, 0).x(); in executeDepthBoundsTest()
255 tcu::PixelBufferAccess access(depthBuffer.getFormat(), 1, 1, 1, &buffer); \ in executeDepthCompare()
256 access.setPixDepth(sampleDepthFloat, 0, 0, 0); \ in executeDepthCompare()
257 deUint32 sampleDepth = access.getPixelUint(0, 0, 0).x(); \ in executeDepthCompare()
/third_party/vk-gl-cts/modules/gles31/functional/
H A Des31fPrimitiveBoundingBoxTests.cpp1537 deUint8 scanRow (const tcu::ConstPixelBufferAccess& access, int row, int rowBegin, int rowEnd, int rowViewportBegin, int rowViewportEnd, const tcu::IVec2& numLines, int& floodCounter) const;
1538 deUint8 scanColumn (const tcu::ConstPixelBufferAccess& access, int column, int columnBegin, int columnEnd, int columnViewportBegin, int columnViewportEnd, const tcu::IVec2& numLines, int& floodCounter) const;
1539 bool checkAreaNumLines (const tcu::ConstPixelBufferAccess& access, const tcu::IVec4& area, int& floodCounter, int componentNdx, const tcu::IVec2& numLines) const;
1540 deUint8 checkLineContinuity (const tcu::ConstPixelBufferAccess& access, const tcu::IVec2& begin, const tcu::IVec2& end, int componentNdx, int& messageLimitCounter) const;
1541 tcu::IVec2 getNumMinimaMaxima (const tcu::ConstPixelBufferAccess& access, int componentNdx) const;
1542 deUint8 checkLineWidths (const tcu::ConstPixelBufferAccess& access, const tcu::IVec2& begin, const tcu::IVec2& end, int componentNdx, int& floodCounter) const;
2141 deUint8 LineRenderCase::scanRow (const tcu::ConstPixelBufferAccess& access, int row, int rowBegin, int rowEnd, int rowViewportBegin, int rowViewportEnd, const tcu::IVec2& numLines, int& messageLimitCounter) const
2143 const bool numLinesOk = checkAreaNumLines(access, tcu::IVec4(rowBegin, row, rowEnd - rowBegin, 1), messageLimitCounter, SCAN_ROW_COMPONENT_NDX, numLines);
2144 const deUint8 lineWidthRes = checkLineWidths(access, tcu::IVec2(rowBegin, row), tcu::IVec2(rowEnd, row), SCAN_ROW_COMPONENT_NDX, messageLimitCounter);
2145 const deUint8 lineContinuityRes = checkLineContinuity(access, tc
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/base/hiviewdfx/hidumper/frameworks/native/src/util/
H A Dfile_utils.cpp32 if (!access(path.c_str(), F_OK) || path == "") { in CreateFolder()
/base/hiviewdfx/hilog/services/hilogd/
H A Dlog_kmsg.cpp74 if (access(PROC_KMSG, R_OK) != 0) { in LinuxReadAllKmsg()
/base/inputmethod/imf/services/file/src/
H A Dfile_operator.cpp39 return access(path.c_str(), F_OK) == SUCCESS; in IsExist()

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