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/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/include/nvif/
H A Dif0001.h14 __s8 ustate_ac; /* out: target pstate index */
15 __s8 ustate_dc; /* out: target pstate index */
19 __s8 pstate; /* out: current pstate index */ member
26 __s8 state; /* in: index of pstate to query
27 * out: pstate identifier
43 __s8 ustate; /* in: pstate identifier */
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_hubbub.c123 /* pstate latency is ~20us so if we wait over 40us and pstate allow in hubbub1_verify_allow_pstate_change_high()
127 * pstate takes around ~100us on linux. Unknown currently as to in hubbub1_verify_allow_pstate_change_high()
139 /* we hacked to force pstate allow to prevent hang last time in hubbub1_verify_allow_pstate_change_high()
153 * 0: Pipe0 Plane0 Allow Pstate Change in hubbub1_verify_allow_pstate_change_high()
154 * 1: Pipe0 Plane1 Allow Pstate Change in hubbub1_verify_allow_pstate_change_high()
155 * 2: Pipe0 Cursor0 Allow Pstate Change in hubbub1_verify_allow_pstate_change_high()
156 * 3: Pipe0 Cursor1 Allow Pstate Change in hubbub1_verify_allow_pstate_change_high()
157 * 4: Pipe1 Plane0 Allow Pstate Change in hubbub1_verify_allow_pstate_change_high()
158 * 5: Pipe1 Plane1 Allow Pstate Chang in hubbub1_verify_allow_pstate_change_high()
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_hubbub.c121 /* pstate latency is ~20us so if we wait over 40us and pstate allow in hubbub1_verify_allow_pstate_change_high()
125 * pstate takes around ~100us (up to 200us) on linux. Unknown currently in hubbub1_verify_allow_pstate_change_high()
137 /* we hacked to force pstate allow to prevent hang last time in hubbub1_verify_allow_pstate_change_high()
151 * 0: Pipe0 Plane0 Allow Pstate Change in hubbub1_verify_allow_pstate_change_high()
152 * 1: Pipe0 Plane1 Allow Pstate Change in hubbub1_verify_allow_pstate_change_high()
153 * 2: Pipe0 Cursor0 Allow Pstate Change in hubbub1_verify_allow_pstate_change_high()
154 * 3: Pipe0 Cursor1 Allow Pstate Change in hubbub1_verify_allow_pstate_change_high()
155 * 4: Pipe1 Plane0 Allow Pstate Change in hubbub1_verify_allow_pstate_change_high()
156 * 5: Pipe1 Plane1 Allow Pstate Chang in hubbub1_verify_allow_pstate_change_high()
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/kernel/linux/linux-5.10/drivers/gpu/drm/arm/
H A Dmalidp_crtc.c256 const struct drm_plane_state *pstate; in malidp_crtc_atomic_check_scaling() local
271 drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) { in malidp_crtc_atomic_check_scaling()
282 h_upscale_factor = div_u64((u64)pstate->crtc_w << 32, in malidp_crtc_atomic_check_scaling()
283 pstate->src_w); in malidp_crtc_atomic_check_scaling()
284 v_upscale_factor = div_u64((u64)pstate->crtc_h << 32, in malidp_crtc_atomic_check_scaling()
285 pstate->src_h); in malidp_crtc_atomic_check_scaling()
290 if (pstate->rotation & MALIDP_ROTATED_MASK) { in malidp_crtc_atomic_check_scaling()
291 s->input_w = pstate->src_h >> 16; in malidp_crtc_atomic_check_scaling()
292 s->input_h = pstate->src_w >> 16; in malidp_crtc_atomic_check_scaling()
294 s->input_w = pstate in malidp_crtc_atomic_check_scaling()
343 const struct drm_plane_state *pstate; malidp_crtc_atomic_check() local
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/kernel/linux/linux-6.6/drivers/gpu/drm/arm/
H A Dmalidp_crtc.c259 const struct drm_plane_state *pstate; in malidp_crtc_atomic_check_scaling() local
274 drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) { in malidp_crtc_atomic_check_scaling()
285 h_upscale_factor = div_u64((u64)pstate->crtc_w << 32, in malidp_crtc_atomic_check_scaling()
286 pstate->src_w); in malidp_crtc_atomic_check_scaling()
287 v_upscale_factor = div_u64((u64)pstate->crtc_h << 32, in malidp_crtc_atomic_check_scaling()
288 pstate->src_h); in malidp_crtc_atomic_check_scaling()
293 if (pstate->rotation & MALIDP_ROTATED_MASK) { in malidp_crtc_atomic_check_scaling()
294 s->input_w = pstate->src_h >> 16; in malidp_crtc_atomic_check_scaling()
295 s->input_h = pstate->src_w >> 16; in malidp_crtc_atomic_check_scaling()
297 s->input_w = pstate in malidp_crtc_atomic_check_scaling()
348 const struct drm_plane_state *pstate; malidp_crtc_atomic_check() local
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/kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/mdp5/
H A Dmdp5_plane.c79 struct mdp5_plane_state *pstate = to_mdp5_plane_state(state); in mdp5_plane_atomic_print_state() local
82 drm_printf(p, "\thwpipe=%s\n", pstate->hwpipe ? in mdp5_plane_atomic_print_state()
83 pstate->hwpipe->name : "(null)"); in mdp5_plane_atomic_print_state()
86 pstate->r_hwpipe ? pstate->r_hwpipe->name : in mdp5_plane_atomic_print_state()
88 drm_printf(p, "\tblend_mode=%u\n", pstate->base.pixel_blend_mode); in mdp5_plane_atomic_print_state()
89 drm_printf(p, "\tzpos=%u\n", pstate->base.zpos); in mdp5_plane_atomic_print_state()
90 drm_printf(p, "\tnormalized_zpos=%u\n", pstate->base.normalized_zpos); in mdp5_plane_atomic_print_state()
91 drm_printf(p, "\talpha=%u\n", pstate->base.alpha); in mdp5_plane_atomic_print_state()
92 drm_printf(p, "\tstage=%s\n", stage2name(pstate in mdp5_plane_atomic_print_state()
131 struct mdp5_plane_state *pstate = to_mdp5_plane_state(state); mdp5_plane_destroy_state() local
862 struct drm_plane_state *pstate = plane->state; mdp5_plane_mode_set() local
976 struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state); mdp5_plane_pipe() local
986 struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state); mdp5_plane_right_pipe() local
996 struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state); mdp5_plane_get_flush() local
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/kernel/linux/linux-5.10/arch/sparc/kernel/
H A Drtrap_64.S11 #include <asm/pstate.h>
28 661: wrpr %g0, RTRAP_PSTATE, %pstate
31 * the ADI security, we must re-enable PSTATE.mcde before
36 wrpr %g0, RTRAP_PSTATE|PSTATE_MCDE, %pstate
39 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
44 661: wrpr %g0, RTRAP_PSTATE, %pstate
47 * the ADI security, we must re-enable PSTATE.mcde before
52 wrpr %g0, RTRAP_PSTATE|PSTATE_MCDE, %pstate
55 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
70 661: wrpr %g0, RTRAP_PSTATE, %pstate
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H A Dspiterrs.S159 rdpr %pstate, %g4
160 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
187 rdpr %pstate, %g4
188 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
207 rdpr %pstate, %g4
208 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
226 rdpr %pstate, %g4
227 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
/kernel/linux/linux-6.6/arch/sparc/kernel/
H A Drtrap_64.S11 #include <asm/pstate.h>
28 661: wrpr %g0, RTRAP_PSTATE, %pstate
31 * the ADI security, we must re-enable PSTATE.mcde before
36 wrpr %g0, RTRAP_PSTATE|PSTATE_MCDE, %pstate
39 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
44 661: wrpr %g0, RTRAP_PSTATE, %pstate
47 * the ADI security, we must re-enable PSTATE.mcde before
52 wrpr %g0, RTRAP_PSTATE|PSTATE_MCDE, %pstate
55 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
70 661: wrpr %g0, RTRAP_PSTATE, %pstate
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H A Dsmp_64.c396 static void spitfire_xcall_helper(u64 data0, u64 data1, u64 data2, u64 pstate, unsigned long cpu) in spitfire_xcall_helper() argument
419 "wrpr %1, %2, %%pstate\n\t" in spitfire_xcall_helper()
431 : "r" (pstate), "i" (PSTATE_IE), "i" (ASI_INTR_W), in spitfire_xcall_helper()
443 __asm__ __volatile__("wrpr %0, 0x0, %%pstate" in spitfire_xcall_helper()
444 : : "r" (pstate)); in spitfire_xcall_helper()
451 __asm__ __volatile__("wrpr %0, 0x0, %%pstate" in spitfire_xcall_helper()
452 : : "r" (pstate)); in spitfire_xcall_helper()
466 u64 pstate; in spitfire_xcall_deliver() local
469 __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate)); in spitfire_xcall_deliver()
486 u64 *mondo, pstate, ver, busy_mask; cheetah_xcall_deliver() local
1312 unsigned long pstate; cpu_play_dead() local
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H A Dspiterrs.S159 rdpr %pstate, %g4
160 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
187 rdpr %pstate, %g4
188 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
207 rdpr %pstate, %g4
208 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
226 rdpr %pstate, %g4
227 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_crtc.c69 struct dpu_plane_state *pstate, struct dpu_format *format) in _dpu_crtc_setup_blend_cfg()
86 lm->ops.setup_blend_config(lm, pstate->stage, in _dpu_crtc_setup_blend_cfg()
125 struct dpu_plane_state *pstate = NULL; in _dpu_crtc_blend_setup_mixer() local
140 pstate = to_dpu_plane_state(state); in _dpu_crtc_blend_setup_mixer()
147 pstate->stage, in _dpu_crtc_blend_setup_mixer()
152 format = to_dpu_format(msm_framebuffer_format(pstate->base.fb)); in _dpu_crtc_blend_setup_mixer()
154 if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable) in _dpu_crtc_blend_setup_mixer()
157 stage_idx = zpos_cnt[pstate->stage]++; in _dpu_crtc_blend_setup_mixer()
158 stage_cfg->stage[pstate->stage][stage_idx] = in _dpu_crtc_blend_setup_mixer()
160 stage_cfg->multirect_index[pstate in _dpu_crtc_blend_setup_mixer()
68 _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer, struct dpu_plane_state *pstate, struct dpu_format *format) _dpu_crtc_setup_blend_cfg() argument
164 state, pstate, stage_idx, _dpu_crtc_blend_setup_mixer() local
824 const struct drm_plane_state *pstate; dpu_crtc_atomic_check() local
1081 struct dpu_plane_state *pstate = NULL; _dpu_debugfs_status_show() local
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/kernel/linux/linux-6.6/arch/arm64/kvm/hyp/include/hyp/
H A Dsysreg-sr.h79 * Guest PSTATE gets saved at guest fixup time in all in __sysreg_save_el2_return_state()
83 ctxt->regs.pstate = read_sysreg_el2(SYS_SPSR); in __sysreg_save_el2_return_state()
169 /* Read the VCPU state's PSTATE, but translate (v)EL2 to EL1. */
172 u64 mode = ctxt->regs.pstate & (PSR_MODE_MASK | PSR_MODE32_BIT); in to_hw_pstate()
183 return (ctxt->regs.pstate & ~(PSR_MODE_MASK | PSR_MODE32_BIT)) | mode; in to_hw_pstate()
188 u64 pstate = to_hw_pstate(ctxt); in __sysreg_restore_el2_return_state() local
189 u64 mode = pstate & PSR_AA32_MODE_MASK; in __sysreg_restore_el2_return_state()
203 pstate = PSR_MODE_EL2h | PSR_IL_BIT; in __sysreg_restore_el2_return_state()
206 write_sysreg_el2(pstate, SYS_SPSR); in __sysreg_restore_el2_return_state()
/kernel/linux/linux-6.6/Documentation/arch/arm64/
H A Dsme.rst21 * PSTATE.SM, PSTATE.ZA, the streaming mode vector length, the ZA and (when
97 * On syscall PSTATE.ZA is preserved, if PSTATE.ZA==1 then the contents of the
100 * On syscall PSTATE.SM will be cleared and the SVE registers will be handled
107 PSTATE.SM cleared.
130 the value of PSTATE.ZA. The registers are present if and only if:
132 in which case PSTATE.ZA == 1.
146 * If ZTn is supported and PSTATE.ZA==1 then a signal frame record for ZTn will
165 PSTATE
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/kernel/linux/linux-5.10/arch/arm64/kvm/
H A Dinject_fault.c31 * and PSTATE into ELR and SPSR respectively, and compute the new PC/PSTATE.
33 * bit 0 being set (PSTATE.SP == 1).
35 * When an exception is taken, most PSTATE fields are left unchanged in the
88 // PSTATE.UAO is set to zero upon any exception to AArch64 in enter_exception64()
91 // PSTATE.PAN is unchanged unless SCTLR_ELx.SPAN == 0b0 in enter_exception64()
98 // PSTATE.SS is set to zero upon any exception to AArch64 in enter_exception64()
101 // PSTATE.IL is set to zero upon any exception to AArch64 in enter_exception64()
104 // PSTATE.SSBS is set to SCTLR_ELx.DSSBS upon any exception to AArch64 in enter_exception64()
109 // PSTATE in enter_exception64()
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/kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_crtc.c334 struct dpu_plane_state *pstate, struct dpu_format *format) in _dpu_crtc_setup_blend_cfg()
340 fg_alpha = pstate->base.alpha >> 8; in _dpu_crtc_setup_blend_cfg()
344 if (pstate->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE || in _dpu_crtc_setup_blend_cfg()
348 } else if (pstate->base.pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) { in _dpu_crtc_setup_blend_cfg()
373 lm->ops.setup_blend_config(lm, pstate->stage, in _dpu_crtc_setup_blend_cfg()
453 struct dpu_plane_state *pstate = NULL; in _dpu_crtc_blend_setup_mixer() local
470 pstate = to_dpu_plane_state(state); in _dpu_crtc_blend_setup_mixer()
473 format = to_dpu_format(msm_framebuffer_format(pstate->base.fb)); in _dpu_crtc_blend_setup_mixer()
475 if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable) in _dpu_crtc_blend_setup_mixer()
478 set_bit(pstate in _dpu_crtc_blend_setup_mixer()
333 _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer, struct dpu_plane_state *pstate, struct dpu_format *format) _dpu_crtc_setup_blend_cfg() argument
1190 const struct drm_plane_state *pstate; dpu_crtc_atomic_check() local
1279 struct dpu_plane_state *pstate = NULL; _dpu_debugfs_status_show() local
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/kernel/linux/linux-6.6/Documentation/admin-guide/pm/
H A Damd-pstate.rst5 ``amd-pstate`` CPU Performance Scaling Driver
16 ``amd-pstate`` is the AMD CPU performance scaling driver that introduces a
26 ``amd-pstate`` leverages the Linux kernel governors such as ``schedutil``,
30 Volume 2: System Programming [1]_). Currently, ``amd-pstate`` supports basic
45 interpreter for performance adjustments. ``amd-pstate`` will initialize a
117 effectively conveys the most efficient performance level to ``amd-pstate``.
130 ``amd-pstate`` passes performance goals through these registers. The
136 ``amd-pstate`` specifies the minimum allowed performance level.
141 ``amd-pstate`` specifies a limit the maximum performance that is expected
147 ``amd-pstate`` specifie
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/kernel/linux/linux-5.10/drivers/regulator/
H A Dpwm-regulator.c86 struct pwm_state pstate; in pwm_regulator_set_voltage_sel() local
89 pwm_init_state(drvdata->pwm, &pstate); in pwm_regulator_set_voltage_sel()
90 pwm_set_relative_duty_cycle(&pstate, in pwm_regulator_set_voltage_sel()
93 ret = pwm_apply_state(drvdata->pwm, &pstate); in pwm_regulator_set_voltage_sel()
154 struct pwm_state pstate; in pwm_regulator_get_voltage() local
158 pwm_get_state(drvdata->pwm, &pstate); in pwm_regulator_get_voltage()
160 voltage = pwm_get_relative_duty_cycle(&pstate, duty_unit); in pwm_regulator_get_voltage()
191 struct pwm_state pstate; in pwm_regulator_set_voltage() local
196 pwm_init_state(drvdata->pwm, &pstate); in pwm_regulator_set_voltage()
217 pwm_set_relative_duty_cycle(&pstate, dutycycl in pwm_regulator_set_voltage()
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/kernel/linux/linux-6.6/drivers/regulator/
H A Dpwm-regulator.c86 struct pwm_state pstate; in pwm_regulator_set_voltage_sel() local
89 pwm_init_state(drvdata->pwm, &pstate); in pwm_regulator_set_voltage_sel()
90 pwm_set_relative_duty_cycle(&pstate, in pwm_regulator_set_voltage_sel()
93 ret = pwm_apply_state(drvdata->pwm, &pstate); in pwm_regulator_set_voltage_sel()
154 struct pwm_state pstate; in pwm_regulator_get_voltage() local
158 pwm_get_state(drvdata->pwm, &pstate); in pwm_regulator_get_voltage()
160 voltage = pwm_get_relative_duty_cycle(&pstate, duty_unit); in pwm_regulator_get_voltage()
194 struct pwm_state pstate; in pwm_regulator_set_voltage() local
199 pwm_init_state(drvdata->pwm, &pstate); in pwm_regulator_set_voltage()
220 pwm_set_relative_duty_cycle(&pstate, dutycycl in pwm_regulator_set_voltage()
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/kernel/linux/linux-6.6/drivers/cpufreq/
H A Dapple-soc-cpufreq.c109 unsigned int pstate; in apple_soc_cpufreq_get_rate() local
114 pstate = (reg & priv->info->cur_pstate_mask) >> priv->info->cur_pstate_shift; in apple_soc_cpufreq_get_rate()
122 pstate = FIELD_GET(APPLE_DVFS_CMD_PS1, reg); in apple_soc_cpufreq_get_rate()
126 if (p->driver_data == pstate) in apple_soc_cpufreq_get_rate()
129 dev_err(priv->cpu_dev, "could not find frequency for pstate %d\n", in apple_soc_cpufreq_get_rate()
130 pstate); in apple_soc_cpufreq_get_rate()
138 unsigned int pstate = policy->freq_table[index].driver_data; in apple_soc_cpufreq_set_target() local
152 reg |= FIELD_PREP(APPLE_DVFS_CMD_PS1, pstate); in apple_soc_cpufreq_set_target()
153 reg |= FIELD_PREP(APPLE_DVFS_CMD_PS2, pstate); in apple_soc_cpufreq_set_target()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_xgmi.c374 hive->pstate = AMDGPU_XGMI_PSTATE_UNKNOWN; in amdgpu_get_xgmi_hive()
377 * hive pstate on boot is high in vega20 so we have to go to low in amdgpu_get_xgmi_hive()
378 * pstate on after boot. in amdgpu_get_xgmi_hive()
396 int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate) in amdgpu_xgmi_set_pstate() argument
402 bool is_hi_req = pstate == AMDGPU_XGMI_PSTATE_MAX_VEGA20; in amdgpu_xgmi_set_pstate()
403 bool init_low = hive->pstate == AMDGPU_XGMI_PSTATE_UNKNOWN; in amdgpu_xgmi_set_pstate()
406 /* fw bug so temporarily disable pstate switching */ in amdgpu_xgmi_set_pstate()
420 * Vega20 only needs single peer to request pstate high for the hive to in amdgpu_xgmi_set_pstate()
421 * go high but all peers must request pstate low for the hive to go low in amdgpu_xgmi_set_pstate()
423 if (hive->pstate in amdgpu_xgmi_set_pstate()
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/third_party/mesa3d/src/gallium/drivers/zink/
H A Dzink_render_pass.c63 create_render_pass2(struct zink_screen *screen, struct zink_render_pass_state *state, struct zink_render_pass_pipeline_state *pstate) in create_render_pass2() argument
75 pstate->num_attachments = state->num_cbufs; in create_render_pass2()
76 pstate->num_cresolves = state->num_cresolves; in create_render_pass2()
77 pstate->num_zsresolves = state->num_zsresolves; in create_render_pass2()
78 pstate->fbfetch = 0; in create_render_pass2()
84 pstate->attachments[i].format = attachments[i].format = rt->format; in create_render_pass2()
85 pstate->attachments[i].samples = attachments[i].samples = rt->samples; in create_render_pass2()
107 pstate->fbfetch = 1; in create_render_pass2()
132 pstate->attachments[num_attachments].format = attachments[num_attachments].format = rt->format; in create_render_pass2()
133 pstate in create_render_pass2()
234 zink_create_render_pass(struct zink_screen *screen, struct zink_render_pass_state *state, struct zink_render_pass_pipeline_state *pstate) zink_create_render_pass() argument
289 rp_state_size(const struct zink_render_pass_pipeline_state *pstate) rp_state_size() argument
433 struct zink_render_pass_pipeline_state pstate; get_render_pass() local
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/kernel/linux/linux-6.6/arch/arm64/kvm/hyp/
H A Dexception.c76 * and PSTATE into ELR and SPSR respectively, and compute the new PC/PSTATE.
78 * bit 0 being set (PSTATE.SP == 1).
80 * When an exception is taken, most PSTATE fields are left unchanged in the
139 // PSTATE.UAO is set to zero upon any exception to AArch64 in enter_exception64()
142 // PSTATE.PAN is unchanged unless SCTLR_ELx.SPAN == 0b0 in enter_exception64()
149 // PSTATE.SS is set to zero upon any exception to AArch64 in enter_exception64()
152 // PSTATE.IL is set to zero upon any exception to AArch64 in enter_exception64()
155 // PSTATE.SSBS is set to SCTLR_ELx.DSSBS upon any exception to AArch64 in enter_exception64()
160 // PSTATE in enter_exception64()
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/kernel/linux/linux-5.10/arch/arm64/kvm/hyp/include/hyp/
H A Dsysreg-sr.h58 * Guest PSTATE gets saved at guest fixup time in all in __sysreg_save_el2_return_state()
62 ctxt->regs.pstate = read_sysreg_el2(SYS_SPSR); in __sysreg_save_el2_return_state()
140 u64 pstate = ctxt->regs.pstate; in __sysreg_restore_el2_return_state() local
141 u64 mode = pstate & PSR_AA32_MODE_MASK; in __sysreg_restore_el2_return_state()
155 pstate = PSR_MODE_EL2h | PSR_IL_BIT; in __sysreg_restore_el2_return_state()
158 write_sysreg_el2(pstate, SYS_SPSR); in __sysreg_restore_el2_return_state()
/kernel/linux/linux-6.6/drivers/net/wwan/
H A Dwwan_hwsim.c62 } pstate; member
106 port->pstate = AT_PARSER_WAIT_A; in wwan_hwsim_port_start()
143 if (port->pstate == AT_PARSER_WAIT_A) { in wwan_hwsim_port_tx()
145 port->pstate = AT_PARSER_WAIT_T; in wwan_hwsim_port_tx()
147 port->pstate = AT_PARSER_SKIP_LINE; in wwan_hwsim_port_tx()
148 } else if (port->pstate == AT_PARSER_WAIT_T) { in wwan_hwsim_port_tx()
150 port->pstate = AT_PARSER_WAIT_TERM; in wwan_hwsim_port_tx()
152 port->pstate = AT_PARSER_SKIP_LINE; in wwan_hwsim_port_tx()
153 } else if (port->pstate == AT_PARSER_WAIT_TERM) { in wwan_hwsim_port_tx()
163 port->pstate in wwan_hwsim_port_tx()
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